GaN amplitude-phase control multifunctional chip and phased array system

Abstract

The invention provides a GaN amplitude-phase control multifunctional chip and a phased array system, and belongs to the technical field of microelectronics. The GaN amplitude-phase control multifunctional chip comprises an input port, an output port, a distributed current multiplexing amplifier, a phase shifter, a first blocking capacitor and a second blocking capacitor, the distributed current multiplexing amplifier comprises a first switching tube, a second switching tube, a first grid voltage supply circuit, a direct current self-bias circuit, a negative feedback circuit, a first choke filter circuit, a second grid voltage supply circuit, a second choke filter circuit and a voltage source. Based on all the components and the connection relation among all the components, the pushing-stage amplifier in the GaN amplitude-phase control multifunctional chip adopts a distributed current multiplexing structure, so that the power consumption of the pushing-stage amplifier can be reduced, the efficiency of the GaN amplitude-phase control multifunctional chip is improved, and the reliability of the GaN amplitude-phase control multifunctional chip is improved. Therefore, the GaN amplitude-phase control multifunctional chip is high in efficiency under the conditions of small size and high power.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic technology, and in particular to a GaN amplitude and phase control multifunctional chip and a phased array system. Background Art

[0002] As phased array systems are increasingly used in communications, detection, and other fields, the demand for miniaturization and high power of amplitude and phase control multifunctional chips as core devices is becoming more and more urgent. In recent years, due to the high breakdown, high power, and high efficiency of GaN HEMT devices, amplitude and phase chips based on GaN HEMT have also attracted much attention.

[0003] However, since the leakage current of GaN chips is generally a high voltage of more than +15V, the power consumption of GaN amplitude and phase control multifunctional chips in small-power driver-stage amplifiers is relatively large, resulting in low overall efficiency. Summary of the invention

[0004] The embodiments of the present invention provide a GaN amplitude-phase control multifunctional chip and a phased array system to solve the problem in the prior art that the power consumption of the driver amplifier is large, resulting in low efficiency of the GaN amplitude-phase control multifunctional chip.

[0005] In a first aspect, an embodiment of the present invention provides a GaN amplitude-phase control multifunctional chip, including an input port, an output port, a distributed current multiplexing amplifier, a phase shifter, a first DC blocking capacitor and a second DC blocking capacitor;

[0006] The distributed current multiplexing amplifier includes a first switch tube, a second switch tube, a first gate voltage supply circuit, a DC self-bias circuit, a negative feedback circuit, a first choke filter circuit, a second gate voltage supply circuit, a second choke filter circuit and a voltage source;

[0007] The first end of the first gate voltage providing circuit is connected to the input port, and the second end of the first gate voltage providing circuit is connected to the control end of the first switch tube and the first end of the negative feedback circuit; the first end of the first switch tube is connected to the second end of the negative feedback circuit, and the second end of the first switch tube is connected to the first end of the DC self-biasing circuit; the third end of the negative feedback circuit is connected to the first end of the first DC blocking capacitor and the first end of the first choke filter circuit; the second end of the first DC blocking capacitor is connected to the first end of the phase shifter, the second end of the phase shifter is connected to the first end of the second DC blocking capacitor, and the second end of the second DC blocking capacitor is connected to the first end of the second gate voltage providing circuit and the control end of the second switch tube; the first end of the second switch tube is connected to the first end of the second choke filter circuit, and the second end of the second switch tube is connected to the second end of the first choke filter circuit; the second end of the second gate voltage providing circuit and the second end of the second choke filter circuit are both connected to the positive pole of the voltage source; the third end of the second choke filter circuit is connected to the output port.

[0008] In a possible implementation, the first gate voltage providing circuit includes a first inductor, a second inductor and a first resistor;

[0009] The first end of the first inductor serves as the first end of the first gate voltage providing circuit, the second end of the first inductor is connected to the first end of the second inductor, and the second end of the first inductor also serves as the second end of the first gate voltage providing circuit; the second end of the second inductor is connected to the first end of the first resistor, and the second end of the first resistor is grounded.

[0010] In a possible implementation, the DC self-biasing circuit includes a first microstrip line, a second capacitor, and a third resistor;

[0011] The first end of the first microstrip line serves as the first end of the DC self-biasing circuit, the second end of the first microstrip line connects the first end of the second capacitor and the first end of the third resistor, and the second end of the second capacitor and the second end of the third resistor are both grounded.

[0012] In a possible implementation, the negative feedback circuit includes a third inductor, a third capacitor, and a second resistor;

[0013] The first end of the second resistor serves as the first end of the negative feedback circuit, the second end of the second resistor is connected to the first end of the third capacitor, and the second end of the third capacitor serves as the third end of the negative feedback circuit; the first end of the third inductor serves as the second end of the negative feedback circuit, and the second end of the third inductor is connected to the second end of the third capacitor.

[0014] In a possible implementation, the first choke filter circuit includes a second microstrip line, a third microstrip line, a fourth resistor and a fifth capacitor;

[0015] The first end of the third microstrip line serves as the first end of the first choke filter circuit, and the second end of the third microstrip line is connected to the first end of the fourth resistor; the first end of the second microstrip line serves as the second end of the first choke filter circuit, and the second end of the second microstrip line is connected to the second end of the fourth resistor and the first end of the fifth capacitor, and the second end of the fifth capacitor is grounded.

[0016] In a possible implementation, the second gate voltage providing circuit includes a fifth resistor, a sixth resistor and a seventh resistor;

[0017] The first end of the fifth resistor is grounded, the second end of the fifth resistor is connected to the first end of the sixth resistor and the first end of the seventh resistor, the second end of the seventh resistor serves as the first end of the second gate voltage providing circuit, and the second end of the sixth resistor serves as the second end of the second gate voltage providing circuit.

[0018] In a possible implementation, the second choke filter circuit includes a fifth inductor, a sixth inductor and a seventh capacitor;

[0019] The first end of the fifth inductor serves as the first end of the second choke filter circuit, the second end of the fifth inductor serves as the third end of the second choke filter circuit, the second end of the fifth inductor is also connected to the first end of the sixth inductor, the second end of the sixth inductor serves as the second end of the second choke filter circuit, the second end of the sixth inductor is also connected to the first end of the seventh capacitor, and the second end of the seventh capacitor is grounded.

[0020] In a possible implementation, the distributed current multiplexing amplifier further includes a first capacitor and a sixth capacitor;

[0021] A first terminal of the first gate voltage providing circuit is connected to the input port via a first capacitor;

[0022] The third terminal of the second choke filter circuit is connected to the output port through the sixth capacitor.

[0023] In a possible implementation, the GaN amplitude and phase control multifunctional chip further includes an attenuator and a power amplifier;

[0024] The third end of the second choke filter circuit is connected to the output port through the attenuator and the power amplifier in sequence.

[0025] In a second aspect, an embodiment of the present invention provides a phased array system, comprising the GaN amplitude and phase control multifunctional chip in the first aspect or any possible implementation of the first aspect.

[0026] The embodiment of the present invention provides a GaN amplitude-phase control multifunctional chip and a phased array system. The GaN amplitude-phase control multifunctional chip includes a distributed current multiplexing amplifier, a phase shifter, a first DC blocking capacitor and a second DC blocking capacitor. The distributed current multiplexing amplifier includes a first switch tube, a second switch tube, a first gate voltage providing circuit, a DC self-biasing circuit, a negative feedback circuit, a first choke filter circuit, a second gate voltage providing circuit, a second choke filter circuit and a voltage source. Based on the above components and the connection relationship between the components, the driver stage amplifier in the GaN amplitude-phase control multifunctional chip adopts a distributed current multiplexing structure, thereby reducing the power consumption of the driver stage amplifier, improving the efficiency of the GaN amplitude-phase control multifunctional chip, and achieving high efficiency in a small size and high power condition. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0028] Figure 1It is a schematic structural diagram of a GaN amplitude and phase control multifunctional chip provided by an embodiment of the present invention;

[0029] Figure 2 It is a schematic diagram of the layout of a GaN amplitude and phase control multifunctional chip provided by an embodiment of the present invention;

[0030] Figure 3 1 is a schematic diagram of an insertion loss curve of a phase shifter in a GaN amplitude-phase control multifunctional chip provided in an embodiment of the present invention;

[0031] Figure 4 1 is a schematic diagram of a phase shift accuracy RMS curve of a phase shifter in a GaN amplitude-phase control multifunctional chip provided in an embodiment of the present invention;

[0032] Figure 5 It is a schematic diagram of an insertion loss curve of an attenuator in a GaN amplitude and phase control multifunctional chip provided in one embodiment of the present invention;

[0033] Figure 6 1 is a schematic diagram of an attenuation accuracy RMS curve of an attenuator in a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention;

[0034] Figure 7 It is a schematic diagram of a power gain curve of a distributed current multiplexing amplifier in a GaN amplitude and phase control multifunctional chip provided by an embodiment of the present invention;

[0035] Figure 8 It is a schematic diagram of a stability factor curve of a distributed current multiplexing amplifier in a GaN amplitude and phase control multifunctional chip provided by an embodiment of the present invention;

[0036] Fig. 9 1 is a schematic diagram of an output power curve of a distributed current multiplexing amplifier in a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention;

[0037] Fig.10 This is a current schematic diagram of a distributed current multiplexing amplifier in a GaN amplitude and phase control multifunctional chip provided by an embodiment of the present invention;

[0038] Fig.11 1 is a schematic diagram of an output power curve of a GaN amplitude and phase control multifunctional chip provided by an embodiment of the present invention;

[0039] Fig.12 It is a schematic diagram of a current curve of a GaN amplitude and phase control multifunctional chip provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable people in the technical field to better understand the present solution, the technical solution in the embodiment of the present solution will be clearly described below in conjunction with the drawings in the embodiment of the present solution. Obviously, the described embodiment is an embodiment of a part of the present solution, not all of the embodiments. Based on the embodiments in the present solution, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present solution.

[0041] The term "including" and any other variations in the specification and claims of this solution and the above drawings mean "including but not limited to", and is intended to cover non-exclusive inclusions and is not limited to the examples listed in the text. In addition, the terms "first" and "second" are used to distinguish different objects, not to describe a specific order.

[0042] As the performance of phased array systems improves, the demand for single-channel output power, efficiency and miniaturization becomes more and more urgent. GaN amplitude-phase control multifunctional chips are the best solution for miniaturization and high power. In related technologies, the research on GaN amplitude-phase control multifunctional chips is all about its high power and miniaturization, but less about its high efficiency. For driver amplifiers with an output power lower than 20dBm, due to the influence of frequency and impedance matching, the HEMT gate width cannot be significantly reduced, and its power consumption is high, resulting in low efficiency of GaN amplitude-phase control multifunctional chips.

[0043] In the related art, in order to reduce the power consumption of the driver-stage amplifier, a structure in which two-stage amplifiers are placed together (without a passive functional module network in the middle) is generally used. However, when the GaN amplitude and phase control multifunctional chip is designed in a link, the local gain of the link is relatively high, and the use of this structure cannot solve the problem of high power consumption.

[0044] In order to solve the above problems, an embodiment of the present application provides a GaN amplitude and phase control multifunctional chip.

[0045] Figure 1 A schematic diagram of the structure of a GaN amplitude and phase control multifunctional chip provided by an embodiment of the present invention. Figure 1 , the GaN amplitude and phase control multifunctional chip includes an input port, an output port, a distributed current multiplexing amplifier, a phase shifter S1, a first DC blocking capacitor C4 and a second DC blocking capacitor C8;

[0046] The distributed current multiplexing amplifier includes a first switch tube Q1, a second switch tube Q2, a first gate voltage supply circuit 11, a DC self-bias circuit 12, a negative feedback circuit 13, a first choke filter circuit 14, a second gate voltage supply circuit 15, a second choke filter circuit 16 and a voltage source V1;

[0047] The first end of the first gate voltage providing circuit 11 is connected to the input port, and the second end of the first gate voltage providing circuit 11 is connected to the control end of the first switch tube Q1 and the first end of the negative feedback circuit 13; the first end of the first switch tube Q1 is connected to the second end of the negative feedback circuit 13, and the second end of the first switch tube Q1 is connected to the first end of the DC self-biasing circuit 12; the third end of the negative feedback circuit 13 is connected to the first end of the first DC blocking capacitor C4 and the first end of the first choke filter circuit 14; the second end of the first DC blocking capacitor C4 is connected to the first end of the phase shifter S1, the second end of the phase shifter S1 is connected to the first end of the second DC blocking capacitor C8, and the second end of the second DC blocking capacitor C8 is connected to the first end of the second gate voltage providing circuit 15 and the control end of the second switch tube Q2; the first end of the second switch tube Q2 is connected to the first end of the second choke filter circuit 16, and the second end of the second switch tube Q2 is connected to the second end of the first choke filter circuit 14; the second end of the second gate voltage providing circuit 15 and the second end of the second choke filter circuit 16 are both connected to the positive electrode of the voltage source V1; the third end of the second choke filter circuit 16 is connected to the output port.

[0048] The distributed current multiplexing amplifier in the embodiment of the present application is used as a driving stage amplifier, including two driving amplifiers, namely a first driving amplifier and a second driving amplifier. The first driving amplifier and the second driving amplifier adopt a distributed structure, and the current of the first driving amplifier and the second driving amplifier is multiplexed. Figure 1 , Figure 1 The arrows in the figure represent the current, which is Figure 1 As can be seen from the arrows in FIG. 1 , the current of the first push amplifier and the second push amplifier are multiplexed.

[0049] In the link structure, a phase shifter S1 is connected between the first push amplifier and the second push amplifier. The first push amplifier, the phase shifter S1 and the second push amplifier adopt a distributed current multiplexing structure. The specific topology can be found in Figure 1 After adopting the distributed current multiplexing structure provided in the embodiment of the present application, the current of the first push amplifier and the second push amplifier is about 70mA, and the gain power and stability thereof can meet the use requirements of the chip.

[0050] In order to ensure the normal DC operating point of the distributed current multiplexing amplifier, and because there is an RF branch to the ground in the phase shifter S1, the embodiment of the present application needs to add DC blocking capacitors before and after the phase shifter S1, that is, the first DC blocking capacitor C4 and the second DC blocking capacitor C8. That is, the first DC blocking capacitor C4 is the DC blocking capacitor between the first driving amplifier and the phase shifter S1, and the second DC blocking capacitor C8 is the DC blocking capacitor between the phase shifter S1 and the second driving amplifier.

[0051] In order to ensure the phase shift accuracy, it is necessary to ensure that after the phase shift is disconnected, the output after the first DC blocking capacitor C4 and the input before the second DC blocking capacitor C8 are 50Ω matched.

[0052] The first gate voltage providing circuit 11 can also be called the first gate voltage providing network, which can provide gate voltage zero potential for the first drive amplifier, and can also serve as an input matching network or input matching circuit. Therefore, the first gate voltage providing circuit 11 can be called the first input matching and gate voltage zero potential providing circuit or the first input matching and gate voltage zero potential providing network.

[0053] The DC self-biasing circuit 12 may also be referred to as a DC self-biasing network.

[0054] The negative feedback circuit 13 may also be referred to as a negative feedback network, which may be used to improve stability, and therefore, may also be referred to as a negative feedback stability network or a negative feedback stability circuit.

[0055] The first choke filter circuit 14 may also be referred to as a first choke filter network, specifically a choke filter network of a first driver amplifier.

[0056] The second gate voltage providing circuit 15 may also be referred to as a second gate voltage providing network, and may provide a gate voltage for the second driving amplifier.

[0057] The second choke filter circuit 16 may also be referred to as a second choke filter network, which is a choke filter network of the second driver amplifier, specifically a choke and filter network of the second driver amplifier DC network.

[0058] Among them, the input port can also be called a RF input port, and the output port can also be called a RF output port.

[0059] The current source can provide a +15V voltage, and the negative terminal of the current source is grounded.

[0060] The first switch tube Q1 and the second switch tube Q2 can be any applicable type of switch tubes, and are not specifically limited here.

[0061] The GaN amplitude-phase control multifunctional chip provided in the embodiment of the present application includes a distributed current multiplexing amplifier, a phase shifter S1, a first DC blocking capacitor C4 and a second DC blocking capacitor C8. The distributed current multiplexing amplifier includes a first switch tube Q1, a second switch tube Q2, a first gate voltage providing circuit 11, a DC self-biasing circuit 12, a negative feedback circuit 13, a first choke filter circuit 14, a second gate voltage providing circuit 15, a second choke filter circuit 16 and a voltage source V1. Based on the above-mentioned components and the connection relationship between the components, the driver stage amplifier in the GaN amplitude-phase control multifunctional chip adopts a distributed current multiplexing structure, which can reduce the power consumption of the driver stage amplifier and improve the efficiency of the GaN amplitude-phase control multifunctional chip, so that the GaN amplitude-phase control multifunctional chip can achieve high efficiency under small size and high power conditions.

[0062] Among them, the structure of the GaN amplitude and phase control multifunctional chip provided in the embodiment of the present application can reduce the power consumption of the driver-stage amplifier to half of the original.

[0063] The above-mentioned embodiment introduces a distributed current multiplexing amplifier including a first gate voltage supply circuit 11, a DC self-bias circuit 12, a negative feedback circuit 13, a first choke filter circuit 14, a second gate voltage supply circuit 15 and a second choke filter circuit 16. The specific structures of the first gate voltage supply circuit 11, the DC self-bias circuit 12, the negative feedback circuit 13, the first choke filter circuit 14, the second gate voltage supply circuit 15 and the second choke filter circuit 16 are further introduced below.

[0064] In some embodiments, see Figure 1 , the first gate voltage providing circuit 11 includes a first inductor L1, a second inductor L2 and a first resistor R1;

[0065] The first end of the first inductor L1 serves as the first end of the first gate voltage providing circuit 11, the second end of the first inductor L1 is connected to the first end of the second inductor L2, and the second end of the first inductor L1 also serves as the second end of the first gate voltage providing circuit 11; the second end of the second inductor L2 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is grounded.

[0066] In some embodiments, see Figure 1 , the DC self-biasing circuit 12 includes a first microstrip line MLIN1, a second capacitor C2 and a third resistor R3;

[0067] The first end of the first microstrip line MLIN1 serves as the first end of the DC self-biasing circuit 12 , the second end of the first microstrip line MLIN1 connects the first end of the second capacitor C2 and the first end of the third resistor R3 , and the second end of the second capacitor C2 and the second end of the third resistor R3 are both grounded.

[0068] In some embodiments, see Figure 1 , the negative feedback circuit 13 includes a third inductor L3, a third capacitor C3 and a second resistor R2;

[0069] The first end of the second resistor R2 serves as the first end of the negative feedback circuit 13, the second end of the second resistor R2 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 serves as the third end of the negative feedback circuit 13; the first end of the third inductor L3 serves as the second end of the negative feedback circuit 13, and the second end of the third inductor L3 is connected to the second end of the third capacitor C3.

[0070] In some embodiments, see Figure 1 , the first choke filter circuit 14 includes a second microstrip line MLIN2, a third microstrip line MLIN3, a fourth resistor R4 and a fifth capacitor C5;

[0071] The first end of the third microstrip line MLIN3 serves as the first end of the first choke filter circuit 14, and the second end of the third microstrip line MLIN3 is connected to the first end of the fourth resistor R4; the first end of the second microstrip line MLIN2 serves as the second end of the first choke filter circuit 14, and the second end of the second microstrip line MLIN2 is connected to the second end of the fourth resistor R4 and the first end of the fifth capacitor C5, and the second end of the fifth capacitor C5 is grounded.

[0072] See also Figure 2 , which shows a schematic diagram of the layout of the GaN amplitude-phase control multifunctional chip. Due to the large size of the phase shifter S1, the first push amplifier and the second push amplifier are far apart in the layout, and the interstage choke inductor (between the first push amplifier and the second push amplifier) ​​needs to be represented by a longer microstrip line, namely the third microstrip line MLIN3.

[0073] In some embodiments, see Figure 1 , the second gate voltage providing circuit 15 includes a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7;

[0074] The first end of the fifth resistor R5 is grounded, the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7, the second end of the seventh resistor R7 serves as the first end of the second gate voltage providing circuit 15, and the second end of the sixth resistor R6 serves as the second end of the second gate voltage providing circuit 15.

[0075] In some embodiments, see Figure 1 , the second choke filter circuit 16 includes a fifth inductor L5, a sixth inductor L6 and a seventh capacitor C7;

[0076] The first end of the fifth inductor L5 serves as the first end of the second choke filter circuit 16, the second end of the fifth inductor L5 serves as the third end of the second choke filter circuit 16, the second end of the fifth inductor L5 is also connected to the first end of the sixth inductor L6, the second end of the sixth inductor L6 serves as the second end of the second choke filter circuit 16, the second end of the sixth inductor L6 is also connected to the first end of the seventh capacitor C7, and the second end of the seventh capacitor C7 is grounded.

[0077] In some embodiments, see Figure 1 , the distributed current multiplexing amplifier further includes a first capacitor C1 and a sixth capacitor C6;

[0078] A first terminal of the first gate voltage providing circuit 11 is connected to the input port via a first capacitor C1;

[0079] The third terminal of the second choke filter circuit 16 is connected to the output port via the sixth capacitor C6.

[0080] The first capacitor C1 is used as an input DC blocking capacitor; the sixth capacitor C6 is used as an output DC blocking capacitor.

[0081] In some embodiments, see Figure 2 , the GaN amplitude and phase control multifunctional chip also includes an attenuator and a power amplifier;

[0082] The third terminal of the second choke filter circuit 16 is connected to the output port via the attenuator and the power amplifier in sequence.

[0083] The link sequence of the GaN amplitude and phase control multifunctional chip provided in the embodiment of the present application is input port, first driving amplifier, phase shifter S1, second driving amplifier, attenuator, power amplifier and output port.

[0084] In some possible implementations, in combination with other embodiments, the third end of the second choke filter circuit 16 is connected to the output port via the sixth capacitor C6, the attenuator, and the power amplifier in sequence.

[0085] The topological structure of the distributed current multiplexing amplifier provided in the embodiment of the present application can reduce the power consumption of the GaN high-drain voltage amplitude-phase multifunctional chip, can be promoted and applied to other microwave radio frequency multifunctional chips, and has broad application prospects in the fields of communication and detection.

[0086] The GaN amplitude and phase control multifunctional chip provided in the embodiment of the present application can be applied to phased array systems, providing technical support for the miniaturization, high precision and low power consumption of phased array systems, and providing solutions to the energy saving and heat dissipation problems of phased array systems.

[0087] For the GaN amplitude-phase control multifunctional chip provided in the embodiment of the present application, when designing, first design the circuit of the phase shifter S1 and the attenuator to meet the high-precision requirements and confirm the insertion loss. For specific simulation results, see Figures 3 to 6 .in, Figure 3 It is a schematic diagram of the insertion loss curve of the phase shifter S1 in the GaN amplitude-phase control multifunctional chip, where the abscissa is the frequency and the ordinate is the insertion loss of the phase shifter S1; Figure 4 It is a schematic diagram of the phase shift accuracy RMS curve of the phase shifter S1 in the GaN amplitude-phase control multifunctional chip, where the horizontal axis is the frequency and the vertical axis is the phase shift accuracy RMS; Figure 5 This is a schematic diagram of the insertion loss curve of the attenuator in the GaN amplitude and phase control multifunctional chip, where the horizontal axis is the frequency and the vertical axis is the insertion loss of the attenuator; Figure 6 This is a schematic diagram of the attenuation accuracy RMS curve of the attenuator in the GaN amplitude and phase control multifunctional chip, where the horizontal axis is the frequency and the vertical axis is the attenuation accuracy RMS.

[0088] Then, according to the output power and power gain requirements of the entire multifunctional circuit of the GaN amplitude and phase control multifunctional chip, the position of the multifunctional middle-stage amplifier in the entire link is reasonably optimized from the perspective of power consumption and stability. Finally, the link structure of the first push amplifier, phase shifter S1, and the second push amplifier is selected. In order to reduce power consumption, a distributed current multiplexing amplifier structure is adopted. Through the cascade design of two-stage amplification and phase shifter S1, the output power and current simulation are as follows Figures 7 to 10 As shown, its current is reduced by half based on the ordinary two-stage amplifier.

[0089] in, Figure 7 It is a schematic diagram of the power gain curve of the distributed current multiplexing amplifier in the GaN amplitude and phase control multifunctional chip, where the horizontal axis is the frequency and the vertical axis is the power gain of the distributed current multiplexing amplifier; Figure 8 It is a schematic diagram of the stability factor curve of the distributed current multiplexing amplifier in the GaN amplitude and phase control multifunctional chip, where the horizontal axis is the frequency and the vertical axis is the stability factor of the distributed current multiplexing amplifier; Fig. 9 It is a schematic diagram of the output power curve of the distributed current multiplexing amplifier in the GaN amplitude and phase control multifunctional chip, where the horizontal axis is the frequency and the vertical axis is the output power of the distributed current multiplexing amplifier; Fig.10 This is a current schematic diagram of a distributed current multiplexing amplifier in a GaN amplitude and phase control multifunctional chip. The horizontal axis is the frequency, and the vertical axis is the current of the distributed current multiplexing amplifier.

[0090] Fig.11 and Fig.12 This is a schematic diagram of the overall simulation curve of the GaN amplitude and phase control multifunctional chip. Fig.11It is a schematic diagram of the output power curve of the GaN amplitude and phase control multifunctional chip, where the horizontal axis is the frequency and the vertical axis is the output power of the GaN amplitude and phase control multifunctional chip; Fig.12 This is a schematic diagram of the current curve of the GaN amplitude and phase control multifunctional chip, where the horizontal axis is the frequency and the vertical axis is the current of the GaN amplitude and phase control multifunctional chip.

[0091] Corresponding to the above-mentioned GaN amplitude and phase control multifunctional chip, an embodiment of the present application further provides a phased array system, including any one of the above-mentioned GaN amplitude and phase control multifunctional chips, having the beneficial effects of any one of the above-mentioned GaN amplitude and phase control multifunctional chips.

[0092] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GaN amplitude and phase control multifunctional chip, characterized in that: It includes an input port, an output port, a distributed current multiplexing amplifier, a phase shifter, a first DC blocking capacitor and a second DC blocking capacitor; The distributed current multiplexing amplifier comprises a first switch tube, a second switch tube, a first gate voltage supply circuit, a DC self-bias circuit, a negative feedback circuit, a first choke filter circuit, a second gate voltage supply circuit, a second choke filter circuit and a voltage source; The first end of the first gate voltage providing circuit is connected to the input port, and the second end of the first gate voltage providing circuit is connected to the control end of the first switch tube and the first end of the negative feedback circuit; the first end of the first switch tube is connected to the second end of the negative feedback circuit, and the second end of the first switch tube is connected to the first end of the DC self-biasing circuit; the third end of the negative feedback circuit is connected to the first end of the first DC blocking capacitor and the first end of the first choke filter circuit; the second end of the first DC blocking capacitor is connected to the first end of the phase shifter, the second end of the phase shifter is connected to the first end of the second DC blocking capacitor, and the second end of the second DC blocking capacitor is connected to the first end of the second gate voltage providing circuit and the control end of the second switch tube; the first end of the second switch tube is connected to the first end of the second choke filter circuit, and the second end of the second switch tube is connected to the second end of the first choke filter circuit; the second end of the second gate voltage providing circuit and the second end of the second choke filter circuit are both connected to the positive electrode of the voltage source; the third end of the second choke filter circuit is connected to the output port.

2. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that: The first gate voltage providing circuit includes a first inductor, a second inductor and a first resistor; The first end of the first inductor serves as the first end of the first gate voltage providing circuit, the second end of the first inductor is connected to the first end of the second inductor, and the second end of the first inductor also serves as the second end of the first gate voltage providing circuit; the second end of the second inductor is connected to the first end of the first resistor, and the second end of the first resistor is grounded.

3. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that: The DC self-biasing circuit includes a first microstrip line, a second capacitor and a third resistor; The first end of the first microstrip line serves as the first end of the DC self-biasing circuit, the second end of the first microstrip line connects the first end of the second capacitor and the first end of the third resistor, and the second end of the second capacitor and the second end of the third resistor are both grounded.

4. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that: The negative feedback circuit includes a third inductor, a third capacitor and a second resistor; The first end of the second resistor serves as the first end of the negative feedback circuit, the second end of the second resistor is connected to the first end of the third capacitor, and the second end of the third capacitor serves as the third end of the negative feedback circuit; the first end of the third inductor serves as the second end of the negative feedback circuit, and the second end of the third inductor is connected to the second end of the third capacitor.

5. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that: The first choke filter circuit includes a second microstrip line, a third microstrip line, a fourth resistor and a fifth capacitor; The first end of the third microstrip line serves as the first end of the first choke filter circuit, and the second end of the third microstrip line is connected to the first end of the fourth resistor; The first end of the second microstrip line serves as the second end of the first choke filter circuit, the second end of the second microstrip line is connected to the second end of the fourth resistor and the first end of the fifth capacitor, and the second end of the fifth capacitor is grounded.

6. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that: The second gate voltage providing circuit includes a fifth resistor, a sixth resistor and a seventh resistor; The first end of the fifth resistor is grounded, the second end of the fifth resistor is connected to the first end of the sixth resistor and the first end of the seventh resistor, the second end of the seventh resistor serves as the first end of the second gate voltage providing circuit, and the second end of the sixth resistor serves as the second end of the second gate voltage providing circuit.

7. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that: The second choke filter circuit includes a fifth inductor, a sixth inductor and a seventh capacitor; The first end of the fifth inductor serves as the first end of the second choke filter circuit, the second end of the fifth inductor serves as the third end of the second choke filter circuit, the second end of the fifth inductor is also connected to the first end of the sixth inductor, the second end of the sixth inductor serves as the second end of the second choke filter circuit, the second end of the sixth inductor is also connected to the first end of the seventh capacitor, and the second end of the seventh capacitor is grounded.

8. The GaN amplitude and phase control multifunctional chip according to any one of claims 1 to 7, characterized in that: The distributed current multiplexing amplifier also includes a first capacitor and a sixth capacitor; The first end of the first gate voltage providing circuit is connected to the input port through the first capacitor; The third terminal of the second choke filter circuit is connected to the output port through the sixth capacitor.

9. The GaN amplitude and phase control multifunctional chip according to any one of claims 1 to 7, characterized in that: The GaN amplitude and phase control multifunctional chip also includes an attenuator and a power amplifier; The third end of the second choke filter circuit is connected to the output port through the attenuator and the power amplifier in sequence.

10. A phased array system, characterized in that: It comprises the GaN amplitude and phase control multifunctional chip as claimed in any one of claims 1 to 9.

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