SIMD-based matrix operation method, apparatus and device, and medium

Abstract

The invention provides an SIMD (Single Instruction Multiple Data)-based matrix operation method, device and equipment and a medium, which are applied to a single instruction multiple data SIMD architecture, and the method comprises the following steps: obtaining a plurality of input parameters of a linear equation, the input parameters comprising a coefficient matrix, a vector, an initial solution vector, a maximum number of iterations, convergence tolerance and a relaxation factor; the coefficient matrix is a square matrix; in response to the first SIMD instruction set, preprocessing the coefficient matrix to obtain a preprocessed matrix and calculating an inverse matrix of the preprocessed matrix; performing segmentation processing on the preprocessing matrix and the corresponding inverse matrix to obtain a plurality of sub-blocks; and for each sub-block, in response to the second SIMD instruction set, performing iterative processing on the initial solution vector by adopting an iterative algorithm according to the input parameter, the preprocessing matrix and the inverse matrix in parallel, and determining an optimal solution of the linear equation. According to the scheme, the calculation operation of the matrix and the vector can be loaded and executed in parallel, the increasing scientific calculation and engineering application requirements are met, and then the processing efficiency and the calculation performance are improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular, to a SIMD-based matrix operation method, device, equipment and medium. Background Art

[0002] With the continuous development of computer technology, matrix, as a mathematical tool, is widely used in quantum mechanics calculations in physics, circuit analysis, molecular structure simulation in chemistry, structural mechanics analysis in engineering, information processing, computer graphics and many other fields. Due to the large amount of calculation in matrix solving problems, hardware architecture is required to handle computing tasks. Therefore, in order to improve computing efficiency, it is particularly important to study how to perform matrix operations based on hardware architecture.

[0003] At present, the relevant technology adopts the Single Instruction Single Data (SISD) mode, that is, at any point in time, the processor only executes one instruction on one data element. However, when processing large-scale matrix and vector data, such as matrix-vector multiplication and accumulation, vector multiplication and accumulation, vector-vector multiplication and accumulation, etc., the processing efficiency of this scheme is low, resulting in poor computing performance. Summary of the invention

[0004] The embodiments of the present application provide a SIMD-based matrix operation method, apparatus, device and medium.

[0005] A first aspect of an embodiment of the present application provides a SIMD-based matrix operation method, comprising:

[0006] Acquire multiple input parameters of the linear equation, the input parameters including: coefficient matrix, vector, initial solution vector, maximum number of iterations, convergence tolerance, relaxation factor; the coefficient matrix is ​​a square matrix;

[0007] In response to a first SIMD instruction set, preprocessing the coefficient matrix to obtain a preprocessing matrix and calculating an inverse matrix of the preprocessing matrix;

[0008] Segmenting the preprocessing matrix and the corresponding inverse matrix to obtain a plurality of sub-blocks;

[0009] For each of the sub-blocks, in response to a second SIMD instruction set, an iterative algorithm is used to iteratively process the initial solution vector in parallel according to the input parameters, the preprocessing matrix and the inverse matrix to determine an optimal solution to the linear equation.

[0010] In an optional embodiment of the present application, in response to the first SIMD instruction set, the coefficient matrix is ​​preprocessed to obtain a preprocessed matrix, including:

[0011] In response to the first SIMD instruction set, the diagonal elements of the coefficient matrix are obtained in parallel, a diagonal matrix is ​​formed according to the diagonal elements, and the diagonal matrix is ​​used as the preprocessing matrix;

[0012] In response to the first SIMD instruction set, the coefficient matrix is ​​subjected to incomplete LU decomposition in parallel to obtain a first decomposition result and the first decomposition result is used as the preprocessing matrix; the first decomposition result is the product of an upper triangular matrix and a lower triangular matrix;

[0013] In response to the first SIMD instruction set, when the coefficient matrix is ​​a symmetric positive definite matrix, Cholesky decomposition is performed on the symmetric positive definite matrix in parallel to obtain a second decomposition result and use the second decomposition result as the preprocessing matrix.

[0014] In an optional embodiment of the present application, in response to a second SIMD instruction set, in parallel, according to the input parameters, the preprocessing matrix and the inverse matrix, an iterative algorithm is used to iteratively process the initial solution vector to determine the optimal solution of the linear equation, including:

[0015] In response to the second SIMD instruction set, a current residual vector is calculated according to the coefficient matrix, the solution vector of the current iteration step and the vector; when the current iteration step is executed for the first time, the solution vector of the current iteration step is the initial solution vector, and when the current iteration step is not executed for the first time, the solution vector of the current iteration step is the solution vector updated in the previous iteration step;

[0016] Update the solution vector space according to the relaxation factor, the solution vector of the current iteration step, the inverse matrix, and the current residual vector;

[0017] Based on the current residual vector, determining whether the iterative process meets the convergence condition;

[0018] When the iterative process meets the convergence condition, the solution vector of the current iterative step when the convergence condition is met is used as the optimal solution of the linear equation.

[0019] In an optional embodiment of the present application, updating the solution vector space according to the relaxation factor, the solution vector of the current iteration step, the inverse matrix, and the current residual vector includes:

[0020] Get the number of data operations performed in a single cycle;

[0021] In response to the second SIMD instruction set, a preset algorithm is used to update the solution vector of the current iteration step according to the number of data operations, the relaxation factor, the inverse matrix, and the current residual vector to obtain the updated solution vector; the preset algorithm includes: matrix-vector multiplication, vector multiplication and accumulation, vector multiplication, and matrix decomposition.

[0022] In an optional embodiment of the present application, obtaining the number of data operations performed in a single cycle includes:

[0023] Obtain the granularity of data loaded by the system, the granularity size of a single data, the number of components used for calculation after data loading, and the parallelism of data processing;

[0024] The number of data operations performed in the single cycle is calculated based on the granularity of the data loaded by the system, the granularity size of a single data, the number of components used for calculation after the data is loaded, and the parallelism of data processing.

[0025] In an optional embodiment of the present application, judging whether the iterative process satisfies a convergence condition based on the current residual vector includes:

[0026] Calculating the norm of the current residual vector according to the current residual vector; the norm of the current residual vector is used to characterize the size of the current residual;

[0027] Comparing the norm of the current residual vector with a preset threshold;

[0028] When the norm of the current residual vector is less than a preset threshold, it is determined that the iterative process meets the convergence condition; when the norm of the current residual vector is not less than the preset threshold, it is determined that the iterative process does not meet the convergence condition.

[0029] In an optional embodiment of the present application, the method further includes:

[0030] Storing the optimal solution of the linear equation into a target register;

[0031] Store the calculation result in the target register to the target memory location.

[0032] A second aspect of an embodiment of the present application provides a SIMD-based matrix operation device, comprising:

[0033] An acquisition module is used to acquire multiple input parameters of the linear equation, wherein the input parameters include: a coefficient matrix, a vector, an initial solution vector, a maximum number of iterations, a convergence tolerance, and a relaxation factor; the coefficient matrix is ​​a square matrix;

[0034] A preprocessing module, configured to preprocess the coefficient matrix in response to a first SIMD instruction set, obtain a preprocessing matrix and calculate an inverse matrix of the preprocessing matrix;

[0035] A segmentation module, used for segmenting the preprocessing matrix and the corresponding inverse matrix to obtain a plurality of sub-blocks;

[0036] A processing module is used for iteratively processing the initial solution vector according to the input parameters, the preprocessing matrix and the inverse matrix in parallel for each of the sub-blocks in response to a second SIMD instruction set, so as to determine the optimal solution of the linear equation.

[0037] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0038] A fourth aspect of the embodiments of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0039] In the embodiment of the present application, multiple input parameters of the linear equation are obtained, and the input parameters include: a coefficient matrix, a vector, an initial solution vector, a maximum number of iterations, a convergence tolerance, and a relaxation factor; the coefficient matrix is ​​a square matrix; in response to a first SIMD instruction set, the coefficient matrix is ​​preprocessed to obtain a preprocessed matrix and the inverse matrix of the preprocessed matrix is ​​calculated; the preprocessed matrix and the corresponding inverse matrix are divided and processed to obtain multiple sub-blocks; for each sub-block, in response to a second SIMD instruction set, the initial solution vector is iteratively processed in parallel according to the input parameters, the preprocessed matrix and the inverse matrix using an iterative algorithm to determine the optimal solution of the linear equation. The technical solution in the present application adopts SIMD hardware architecture, and by expanding the number and bit width of storage registers and computing registers, allows the processor to process multiple data elements in one instruction cycle. When processing large-scale matrix and vector data, the first SIMD instruction set can simultaneously load and store these data, thereby preprocessing the coefficient matrix in parallel, obtaining the preprocessing matrix and calculating the inverse matrix of the preprocessing matrix, greatly improving the parallelism and efficiency of data processing. Then, for each block, through the second SIMD instruction set, due to the single instruction multiple data (SIMD) hardware architecture and parallel processing capabilities, it is possible to load and execute matrix and vector operations in parallel, thereby improving the speed and efficiency of matrix solving, meeting the growing needs of scientific computing and engineering applications, and thereby improving processing efficiency and computing performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0041] Figure 1 A schematic diagram of the structure of a computer device provided in one embodiment of the present application;

[0042] Figure 2 A flowchart of a SIMD-based matrix operation method provided for one embodiment of the present application;

[0043] Figure 3 A schematic diagram for comparing calculations of a single instruction single data SISD and a single instruction multiple data SIMD provided in one embodiment of the present application;

[0044] Figure 4 A flowchart of a method for iteratively processing an initial solution vector using an iterative algorithm to determine an optimal solution to a linear equation provided in one embodiment of the present application;

[0045] Figure 5 A schematic diagram of a structure for performing matrix-vector multiplication using SIMD instructions provided in another embodiment of the present application;

[0046] Figure 6 A schematic diagram of a SIMD-based matrix operation process provided by one embodiment of the present application;

[0047] Figure 7 A schematic diagram of the structure of a SIMD-based matrix operation device provided for one embodiment of the present application. DETAILED DESCRIPTION

[0048] In the process of implementing the present application, the inventors found that the traditional SISD mode has low processing efficiency when processing large-scale matrix and vector data, resulting in poor computing performance.

[0049] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0050] As mentioned in the background technology, the traditional computing architecture uses SISD mode for data processing. For example, for an array addition operation: adding two integer arrays a and b with a length of 100, and storing the result in array c, it can be expressed in the following form:

[0051]

[0052] In the implementation of the above array addition, each loop iteration requires the processor to perform the following operations: load, compute, and store. The load operation is to load two source operands (a[i] and b[i]) from the memory into two registers; the compute operation is to execute the addition instruction, add the two operands in the register, and store the result in the target register; the store operation is to store the data in the target register into the target memory location (c[i]). The above operations are performed once per loop. For large-scale data, for example, for an array of length n, a total of 3n memory access operations and n addition operations need to be performed, which makes the processing efficiency low and leads to poor computing performance.

[0053] Based on the above-mentioned defects, the present application provides a matrix operation method based on SIMD, which adopts SIMD hardware architecture and allows the processor to process multiple data elements in one instruction cycle by expanding the number and bit width of storage registers and calculation registers. When processing large-scale matrix and vector data, the first SIMD instruction set can be used to simultaneously load and store these data, so that the coefficient matrix is ​​preprocessed in parallel to obtain the preprocessed matrix and calculate the inverse matrix of the preprocessed matrix, thereby greatly improving the parallelism and efficiency of data processing. Then, for each block, the second SIMD instruction set is used. Due to the single instruction multiple data (SIMD) hardware architecture and parallel processing capabilities, matrix and vector operation operations can be loaded and executed in parallel, thereby improving the speed and efficiency of matrix solving, meeting the growing needs of scientific computing and engineering applications, and thereby improving processing efficiency and computing performance.

[0054] Among them, the solutions in the embodiments of the present application can be implemented using various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0055] See also Figure 1 , a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 1As shown, the computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium can be, for example, a disk. The non-volatile storage medium stores files (which can be files to be processed or processed files), operating systems, computer programs, etc. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a matrix operation method based on SIMD is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a button, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0056] See also Figure 2 The following embodiments take the above-mentioned computer device as the execution subject, and apply the SIMD-based matrix operation method provided in the embodiment of the present application to the above-mentioned computer device to perform instruction processing as an example for specific description. The SIMD-based matrix operation method provided in the embodiment of the present application is applied to the single instruction multiple data SIMD architecture, including the following steps 201-204:

[0057] Step 201, obtaining multiple input parameters of the linear equation, the input parameters include: coefficient matrix, vector, initial solution vector, maximum number of iterations, convergence tolerance, relaxation factor; the coefficient matrix is ​​a square matrix.

[0058] It should be noted that the multiple input parameters of the above linear equation can be understood as multiple data elements. The linear equation can be input through a preset interface, and the preset interface can be, for example, an interface of a linear system. The linear equation can be Ax = b. The above coefficient matrix A can be represented in a matrix form, and the vector b can be represented in a vector form.

[0059] Understandably, see Figure 3 As shown, Figure 3A schematic diagram for the calculation comparison of single instruction single data SISD and single instruction multiple data SIMD provided in the embodiment of the present application, in which the left side of the figure is a schematic diagram for single instruction single data calculation, and the right side is a schematic diagram for single instruction multiple data calculation. In the calculation process of single instruction single data, data is executed one by one, for example, two operands A0 and B0 are first loaded from the memory to the source register, and the addition instruction is executed to obtain the calculation result C0, and stored in the target register, and then stored (Store) to the target memory location, and the above operation is performed on the next group of data until all data are executed. In the calculation process of single instruction multiple data, multiple data are executed, for example, multiple operands A0, A1, ..., A7, B0, B1, ..., B7 are first loaded from the memory to the source register, and then each group of data elements in the source register is calculated in parallel to obtain the corresponding calculation results C0, C1, ..., C7 and store them in the target register, and the calculation results in the target register are stored in the target memory location.

[0060] In the above case, if the hardware supports reading and calculating multiple sets of data at a time, common matrix operations and vector operations can be accelerated extremely quickly, and SIMD is very suitable for computationally intensive tasks. The fundamental reason for its acceleration is that it jumps from processing one data at a time to processing a group of data at a time, thereby completing the same computing task with fewer cycles.

[0061] In the process of solving linear equations in this application, the generalized Richardson iteration method is used. Among them, the generalized Richardson iteration method is also called the generalized stabilized Richardson iteration method, which is an extension of the basic Richardson iteration method. By using different relaxation factors to optimize the convergence performance, it can provide a more effective convergence strategy when dealing with specific types of linear systems, especially when the single matrix has specific characteristics. The basic idea of ​​the generalized Richardson iteration method is to start from an initial guess value, and gradually approach the solution of the linear system through continuous iteration. The correction amount of each iteration is determined by the current residual and a preset relaxation factor (relaxation parameter). The convergence of the generalized Richardson iteration method depends on the selection of M and the adjustment of ω. Reasonable selection of these two parameters can significantly speed up the convergence speed, especially for ill-conditioned or large-scale problems. The relaxation factor ω is usually selected through experiments or based on the specific mathematical characteristics of the problem.

[0062] The SIMD architecture may obtain multiple input parameters of the linear equation, including: coefficient matrix, vector, initial solution vector, maximum number of iterations, convergence tolerance, relaxation factor. The format and meaning of each input parameter may be represented by the following Table 1:

[0063] Table 1

[0064]

[0065]

[0066] The above initial solution vector can be obtained by guessing based on preset experience, b is the constant vector on the right, the preprocessing matrix M is usually easy to invert and close to the inverse matrix or partial inverse matrix of A, the relaxation factor ω is used to control the step size and direction of the iteration, which is usually in the range of (0,2), and the maximum number of iterations is used to control the length of the iterative process. When the maximum number of iterations is reached, it indicates that the iterative process has ended.

[0067] A square matrix is ​​a prerequisite for the generalized Richardson iteration method. After obtaining the above coefficient matrix, it can be determined whether the coefficient matrix is ​​a square matrix, which can include: a symmetric matrix or an asymmetric matrix. When it is not a square matrix, it is processed into a symmetric or asymmetric matrix to meet the prerequisite of the generalized Richardson iteration method.

[0068] Optionally, the above-mentioned multiple input parameters can be obtained by importing from an external device, or obtained from a database or blockchain, or obtained through an input interface. This embodiment does not impose any limitation on the method of obtaining the input parameters.

[0069] Step 202: In response to the first SIMD instruction set, preprocess the coefficient matrix to obtain a preprocessing matrix and calculate the inverse matrix of the preprocessing matrix.

[0070] It should be noted that the first SIMD instruction set is an instruction set in the SIMD architecture, and the first SIMD instruction set is used to characterize the parallel preprocessing of the coefficient matrix to obtain the preprocessing result. The inverse matrix corresponding to the preprocessing matrix can be obtained by performing an inverse operation on the preprocessing matrix.

[0071] After the input parameters are obtained, the coefficient matrix can be preprocessed using a preset preprocessing algorithm in response to the first SIMD instruction set to obtain a preprocessing matrix. The preprocessing algorithm may include, for example, diagonal preprocessing, incomplete LU decomposition (ILU), incomplete Cholesky decomposition, etc. After the preprocessing matrix is ​​obtained, an inverse operation is performed on the preprocessing matrix to obtain a corresponding inverse matrix.

[0072] Step 203: Segment the preprocessing matrix and the corresponding inverse matrix to obtain a plurality of sub-blocks.

[0073] Step 204: For each sub-block, in response to the second SIMD instruction set, an iterative algorithm is used in parallel to iteratively process the initial solution vector according to the input parameters, the preprocessing matrix and the inverse matrix to determine the optimal solution of the linear equation.

[0074] After obtaining the preprocessing matrix and the corresponding inverse matrix, they can be segmented according to the preset segmentation rules to obtain multiple sub-blocks. The segmentation rule can be an average segmentation method or a segmentation method based on the amount of data. By dividing into multiple sub-blocks, each sub-block can be processed in parallel, thereby improving the processing speed, especially when processing large sparse matrices, the matrix is ​​divided into multiple small blocks, each of which can be processed independently on different processors.

[0075] The above-mentioned second SIMD instruction set is an instruction set in the SIMD architecture, and the second SIMD instruction set is used to characterize parallel computing processing. The second SIMD instruction set may be, for example, SSE instructions or AVX instructions, and can process multiple data points simultaneously, reduce CPU idle time, and improve computing speed.

[0076] Specifically, after being divided into a plurality of sub-blocks, for each sub-block, an iterative algorithm can be used to iteratively process the initial solution vector in parallel according to the input parameters, the preprocessing matrix and the inverse matrix in response to the second SIMD instruction set to determine the optimal solution of the linear equation Ax=b. The preset algorithm may include matrix multiplication by matrix, vector multiplication by vector, etc.

[0077] In the embodiment of the present application, multiple input parameters of the linear equation are obtained, and the input parameters include: a coefficient matrix, a vector, an initial solution vector, a maximum number of iterations, a convergence tolerance, and a relaxation factor; the coefficient matrix is ​​a square matrix; in response to a first SIMD instruction set, the coefficient matrix is ​​preprocessed to obtain a preprocessed matrix and the inverse matrix of the preprocessed matrix is ​​calculated; the preprocessed matrix and the corresponding inverse matrix are divided and processed to obtain multiple sub-blocks; for each sub-block, in response to a second SIMD instruction set, the initial solution vector is iteratively processed in parallel according to the input parameters, the preprocessed matrix and the inverse matrix using an iterative algorithm to determine the optimal solution of the linear equation. The technical solution in the present application adopts SIMD hardware architecture, and by expanding the number and bit width of storage registers and computing registers, allows the processor to process multiple data elements in one instruction cycle. When processing large-scale matrix and vector data, the first SIMD instruction set can simultaneously load and store these data, thereby preprocessing the coefficient matrix in parallel, obtaining the preprocessing matrix and calculating the inverse matrix of the preprocessing matrix, greatly improving the parallelism and efficiency of data processing. Then, for each block, through the second SIMD instruction set, due to the single instruction multiple data (SIMD) hardware architecture and parallel processing capabilities, it is possible to load and execute matrix and vector operations in parallel, thereby improving the speed and efficiency of matrix solving, meeting the growing needs of scientific computing and engineering applications, and thereby improving processing efficiency and computing performance.

[0078] In an optional embodiment of the present application, the above-mentioned preprocessing of the coefficient matrix in response to the first SIMD instruction set to obtain the preprocessing matrix includes:

[0079] In response to the first SIMD instruction set, diagonal elements of the coefficient matrix are obtained in parallel, a diagonal matrix is ​​formed according to the diagonal elements, and the diagonal matrix is ​​used as a preprocessing matrix;

[0080] In response to the first SIMD instruction set, the coefficient matrix is ​​decomposed incompletely in parallel to obtain a first decomposition result and the first decomposition result is used as a preprocessing matrix; the first decomposition result is the product of an upper triangular matrix and a lower triangular matrix;

[0081] In response to the first SIMD instruction set, when the coefficient matrix is ​​a symmetric positive definite matrix, Cholesky decomposition is performed on the symmetric positive definite matrix in parallel to obtain a second decomposition result and use the second decomposition result as a preprocessing matrix.

[0082] As an implementable method, after obtaining the coefficient matrix, the diagonal elements of the coefficient matrix A can be obtained, and a diagonal matrix is ​​formed according to the diagonal elements, and the diagonal matrix is ​​used as the preprocessing matrix M, through M = diag (A), that is, a diagonal matrix composed of the diagonal elements of A. For some matrices, their diagonal elements may have certain particularities, such as diagonal dominance, etc., and the use of diagonal preprocessing can improve the convergence of iterations to a certain extent. Use the first SIMD instruction set to extract the diagonal elements of A. Since the SIMD instruction set can perform the same operation on multiple data in a single instruction cycle, for the extraction of diagonal elements of the matrix, elements in multiple positions can be processed simultaneously, thereby improving the extraction efficiency. For example, assuming that the matrix is ​​stored in rows, the SIMD instructions can be used to read the diagonal elements of multiple rows at one time, and then perform subsequent processing.

[0083] As another feasible method, the coefficient matrix A is subjected to incomplete LU decomposition: A is approximately decomposed into the product of the lower triangular matrix L and the upper triangular matrix U, that is, M≈LU. However, some small elements are ignored to reduce the amount of calculation. This method can better utilize the structural information of the matrix. For some asymmetric matrices, incomplete LU decomposition can reduce the number of iterations to a certain extent and improve the convergence speed. It decomposes the matrix A into the product (approximately) of a lower triangular matrix L and an upper triangular matrix U, so that operations such as matrix-vector multiplication can be performed more efficiently during the iteration process. For example, in the process of parallelizing the incomplete LU decomposition, the first SIMD instruction set is used to accelerate vector operations. For example, when calculating the elements of the L and U matrices, for operations such as vector addition, subtraction and multiplication, SIMD instructions can be used to operate on multiple elements at the same time. For example, when calculating the elements of a row, the calculation of multiple columns can be processed at the same time to improve the calculation efficiency.

[0084] As another implementable method, when the coefficient matrix is ​​a symmetric positive definite matrix, the coefficient matrix A is subjected to incomplete Cholesky decomposition to obtain a second decomposition result, and the second decomposition result is used as a preprocessing matrix, M≈LL^T. SIMD instructions are used to parallelize vector and matrix operations in Cholesky decomposition. When calculating the elements of the L matrix, SIMD instructions can be used to process multiple elements simultaneously for vector operations (such as calculating the square root of the elements, multiplication, etc.) and matrix update operations. For example, when updating a row or a column of the matrix, element calculations at multiple positions can be processed simultaneously.

[0085] In this embodiment, by preprocessing the coefficient matrix A, the first SIMD instruction set can be used to accelerate the extraction of diagonal elements and basic arithmetic operations in LU or Cholesky decomposition, thereby increasing the convergence speed and further improving the computational efficiency.

[0086] In an optional embodiment of the present application, see Figure 4 As shown, in response to the second SIMD instruction set, the initial solution vector is iteratively processed in parallel according to the input parameters, the preprocessing matrix and the inverse matrix using an iterative algorithm to determine the optimal solution of the linear equation, including the following method steps:

[0087] Step 301, in response to the second SIMD instruction set, calculate the current residual vector according to the coefficient matrix, the solution vector of the current iteration step and the vector; when the current iteration step is executed for the first time, the solution vector of the current iteration step is the initial solution vector, and when the current iteration step is not executed for the first time, the solution vector of the current iteration step is the updated solution vector of the previous iteration step.

[0088] Step 302: Update the solution vector space according to the relaxation factor, the solution vector of the current iteration step, the inverse matrix, and the current residual vector.

[0089] Step 303: Based on the current residual vector, determine whether the iterative process meets the convergence condition.

[0090] Step 304: When the iterative process meets the convergence condition, the solution vector of the current iterative step that meets the convergence condition is used as the optimal solution of the linear equation.

[0091] It should be noted that the optimal solution of the linear equation Ax=b is approached through an iterative process.

[0092] Specifically, after obtaining the input parameters, preprocessing matrix and inverse matrix, an iterative operation is performed on the initial solution vector. During the iteration process, the maximum number of iterations is max_iteration-1. For k=0, 1, 2, ..., max_iteration-1, the current residual vector of the kth iteration can be calculated first, which can be expressed by the following formula:

[0093] r (k) = b-Ax (k) ;

[0094] Among them, b is a vector, is a known quantity, A is a coefficient matrix, and x (k) is the residual vector of the kth iteration, indicating the gap between the current approximate solution and the optimal solution.

[0095] After obtaining the current residual vector, the updated solution vector space is calculated using the following formula:

[0096] x (k+1) =x (k) +ωM -1 (b-Ax (k) );

[0097] Among them, b is a vector, v is a known quantity, A is a coefficient matrix, x (k) is the residual vector of the kth iteration, ω is the relaxation factor, which is used to control the convergence speed of the iteration, usually 0<ω≤2, M -1 is the inverse matrix of the preprocessing matrix, x (k+1) is the approximate solution vector of the k+1th iteration, that is, the updated solution vector space.

[0098] After obtaining the current residual vector, it can be determined whether the iterative process meets the convergence condition according to the current residual vector. When the convergence condition is met, the solution vector corresponding to the current iteration step is used as the optimal solution of the linear equation; when the convergence condition is not met, the iterative process continues until the maximum number of iterations is completed. The convergence condition is customized according to actual needs, for example, it can be a comparison of a preset threshold.

[0099] In this embodiment, by responding to the second SIMD instruction set, an iterative algorithm is used to iteratively process the initial solution vector in parallel according to input parameters, a preprocessing matrix and an inverse matrix, thereby accelerating the speed of determining the optimal solution of the linear equation and improving the calculation efficiency.

[0100] In an optional embodiment of the present application, the above-mentioned updating of the solution vector space according to the relaxation factor, the solution vector of the current iteration step, the inverse matrix, the current residual vector, includes the following method steps:

[0101] Obtain the number of data operations performed in a single cycle; in response to the second SIMD instruction set, use a preset algorithm to update the solution vector of the current iteration step according to the number of data operations, relaxation factor, inverse matrix, and current residual vector to obtain an updated solution vector; the preset algorithms include: matrix-vector multiplication, vector multiplication and accumulation, vector multiplication, and matrix decomposition.

[0102] It should be noted that the number of data operations performed in the above single cycle can be obtained by performing operations using a SIMD hardware architecture.

[0103] Specifically, in the parallel processing process, the solution vector of the current iteration step can be updated according to the number of data operations, the relaxation factor, the inverse matrix, and the current residual vector in response to the second SIMD instruction set, to obtain an updated solution vector, where Ax (k) It is a matrix-vector multiplication, which can be accelerated using SIMD instructions; b-Ax (k) It is vector subtraction, which can also be accelerated by SIMD instructions; updating the solution vector can also use SIMD instructions to accelerate matrix-vector multiplication M -1 (b-Ax (k) ) and x (k) +ωM -1 (b-Ax (k) )Vector addition operation.

[0104] During the iteration process, the following calculation steps can be accelerated by parallelization (for example, using SIMD instructions), by using various function parallelization interfaces based on the SIMD architecture to perform parallel calculation processing and execute the iteration process. For example, the following may be the function parallelization interface format:

[0105] / / 1. Parallelization of matrix-vector multiplication

[0106] void matrix_vector_multiply(double*A, double*x, double*result, int n);

[0107] / / 2. Parallelization of vector operations

[0108] / / Vector addition

[0109] void vectoradd(double*vec 1, double*vec2, double*output, int n);

[0110] / / Vector dot product

[0111] double vectordot_product(double*vec 1, double*vec2, int n);

[0112] / / 3. Parallel construction of preprocessing matrix M

[0113] void build_diagonal_preconditioner(double*A, double*M_inv, int n);

[0114] / / 4. Parallelization of preprocessing steps

[0115] void apply_preconditioner(double*M_inv,double*r,double*result,doubleomega,int n);

[0116] / / 5. Parallelization of convergence check

[0117] double compute_residual_norm(double*residual, int n);

[0118] / / 6. Block parallel processing

[0119] void block_parallel_processing(double*A, double*x, double*b, int n);

[0120] For the matrix-vector multiplication Ax (k) , whose physical meaning is to calculate the current approximate solution x (k) The mapping under the coefficient matrix A obtains the left-hand value of the linear system. In the parallelization process, each row of the coefficient matrix A is related to the vector x (k) The inner products of can be calculated independently, which is suitable for parallel processing using SIMD instructions.

[0121] For vector subtraction b-Ax (k) , whose physical meaning is to calculate the residual vector r (k) , which measures the error of the current solution. During the parallelization process, each element operation in vector subtraction is independent of each other, and SIMD instructions can be used to perform multiple subtraction operations simultaneously.

[0122] For the preconditioning matrix multiplication M -1 (b-Ax (k)), whose physical meaning is to improve the convergence and stability of the iterative method by applying the inverse of the preprocessing matrix to the residual vector. In the parallelization process, if the preprocessing matrix M is a diagonal matrix or a sparse matrix, the multiplication of its inverse matrix can be decomposed into independent element-level operations, which is suitable for parallel computing. Matrix-vector multiplication can also be parallelized, and the calculation of each element is independent of each other.

[0123] After obtaining the current residual vector, the solution vector space x is updated according to the current residual vector calculation. (k+1) In the process, through the formula x (k+1) =x (k) +ωM -1 (b-Ax (k) ), its physical meaning is to update the current solution according to the correction amount so that it gradually approaches the optimal solution. In the parallelization process, the update of the solution vector involves vector addition and scalar multiplication. The element-level operations are independent of each other and can be executed in parallel using SIMD instructions.

[0124] It is understandable that the hardware will parallelize some modules in the matrix solution, such as the matrix preprocessing module, the matrix-matrix multiplication module, the matrix-vector multiplication module, the multiply-accumulate module, the vector multiplication module, and other modules such as square root calculation. For example, see Figure 5 As shown, Figure 5 The figure is a schematic diagram of using SIMD instructions for matrix-vector multiplication. INPUT VECTOR is the input vector, SIMDDIRECTION is the SIMD instruction, ACCUMULATION DIRECTION is the calculation direction, and OUTPUTVECTOR is the output vector. In the process of using SIMD instructions to perform matrix-vector multiplication, the SIMD instructions can be used to calculate the input vector according to the calculation direction shown in the figure to obtain the corresponding output vector.

[0125] In this embodiment, by responding to the second SIMD instruction set, a preset algorithm is used to update the solution vector of the current iteration step according to the number of data operations, relaxation factor, inverse matrix, and current residual vector, and the updated solution vector is obtained to realize parallel calculation of modules such as matrix-vector multiplication, vector multiplication and accumulation, and vector-vector multiplication, which can process more data in a single clock cycle and reduce computing time and resource consumption.

[0126] In an optional embodiment of the present application, the above-mentioned obtaining the number of data operations performed in a single cycle includes the following method steps:

[0127] Obtain the granularity of the data loaded by the system, the granularity size of a single data, the number of components used for calculation after the data is loaded, and the data processing parallelism; calculate the number of data operations performed in a single cycle based on the granularity of the data loaded by the system, the granularity size of a single data, the number of components used for calculation after the data is loaded, and the data processing parallelism.

[0128] It should be noted that the granularity of data loaded by the above system refers to the data width that the hardware can process in one operation. For example, if the hardware supports 256-bit wide operations, this value is 256. Width of Data: The width of a single data item. For example, if it is a 32-bit floating point number, this value is 32. Number of Operator: The number of computing units that can be used for parallel computing in the hardware. Parallel Degree: Parallelism refers to the number of groups of data loading, calculation and storage processing performed simultaneously. The number of data operations performed in the above single cycle can be expressed by the following formula:

[0129]

[0130] Among them, N represents the number of data operations performed in a single clock cycle, Width of Device is the granularity at which the system can load data, width of data represents the particle size of a single data, Number of Operator represents the number of components that can be used for calculation after the data is loaded, and Parallel Degree represents the degree of parallelism, that is, how many groups of data can be loaded, calculated, and stored at the same time. Divide the granularity at which the system can load data by the particle size of a single data to get how much data a group can load.

[0131] Optionally, the granularity of data loaded by the above system, the granularity size of single data, the number of components used for calculation after data loading, and the data processing parallelism can be pre-customized in the SIMD hardware architecture according to the actual needs of the user.

[0132] It is understandable that through the above optimization, the generalized Richardson iteration method can improve the computational efficiency by more than two orders of magnitude compared with the traditional method. This is mainly because the SIMD architecture can process more data in a single clock cycle, reducing the computing time and resource consumption. With the development of hardware technology, the parallelism and the number of computing units can be continuously increased, thereby improving the scalability of the hardware architecture in data loading, computing and storage, and further improving computing efficiency.

[0133] In this embodiment, the granularity of the data loaded by the system, the granularity size of the single data, the number of components used for calculation after the data is loaded, and the data processing parallelism are obtained; according to the granularity of the data loaded by the system, the granularity size of the single data, the number of components used for calculation after the data is loaded, and the data processing parallelism, the number of data operations performed in a single cycle is calculated, data can be loaded and stored in parallel, and multiple data items can be processed simultaneously through parallel computing, thereby improving computing efficiency.

[0134] In an optional embodiment of the present application, judging whether the iterative process meets the convergence condition based on the current residual vector includes the following method steps:

[0135] According to the current residual vector, the norm of the current residual vector is calculated; the norm of the current residual vector is used to characterize the size of the current residual; the norm of the current residual vector is compared with a preset threshold; when the norm of the current residual vector is less than the preset threshold, it is determined that the iterative process meets the convergence condition; when the norm of the current residual vector is not less than the preset threshold, it is determined that the iterative process does not meet the convergence condition.

[0136] Specifically, after obtaining the current residual vector, the norm of the current residual vector || r can be calculated according to the current residual vector (k) ||, the norm of the current residual vector can be, for example, the Euclidean norm, which indicates the size of the current residual, and then the norm of the current residual vector ||r (k) ||Compare with the preset threshold ε to determine whether the convergence condition is met:

[0137] ||r (k) ||<ε;

[0138] If the norm of the current residual vector || r (k) || is less than the preset threshold ε, it means that the convergence condition is met, the iteration process is stopped, and the optimal solution of the linear equation is obtained; if the norm of the current residual vector ||r (k) When || is not less than the preset threshold ε, it is determined that the iterative process does not meet the convergence condition and the next iterative process needs to be executed.

[0139] In this embodiment, by comparing the norm of the current residual vector with a preset threshold, determining whether to execute the iterative process based on the comparison result, computing time and resources are saved, and the optimal solution of the linear equation can be accurately solved, while helping to reasonably allocate computing resources. For example, when a task has converged, resources can be reallocated to other unconverged tasks to improve the overall system utilization. And based on the SIMD hardware architecture design, it can be compatible with the existing SIMD instruction set without modifying the hardware structure, which improves the feasibility and flexibility of implementation.

[0140] In an optional embodiment of the present application, the above method further includes the following method steps:

[0141] Store the optimal solution of the linear equation into the destination register; store the calculation result in the destination register into the destination memory location.

[0142] Specifically, see Figure 6 As shown, the solution provided by the present application includes four stages, namely, the initialization stage, the iterative calculation stage, the convergence check stage and the output stage. In the initialization stage, the input parameters for solving the linear equation Ax=b can be input, including the coefficient matrix A, the vector b, the initial solution vector, the maximum number of iterations, the convergence tolerance, and the relaxation factor. Then, the preprocessing module constructs a suitable preprocessing matrix M according to the coefficient matrix A, and stores the input parameters, the preprocessing matrix, etc. through the storage unit and the corresponding storage location in the main controller, and then initializes the counter and SIMD marker through the controller. In the iterative calculation stage, the controller starts to execute the iterative loop operation, and executes the SIMD calculation operation in parallel through the multi-core processor. First, the current residual vector r is calculated according to the coefficient matrix, the solution vector and the vector of the current iteration step. (k) = b-Ax (k) , and then apply preprocessing to get the updated solution vector x (k+1) =x (k) +ωM -1 (b-Ax (k) ), and synchronize multi-core data through the communication unit, update the counter through the controller, and check convergence. For the convergence check stage, the norm of the current residual vector is calculated by the multi-core processor, and the norm of the current residual vector is compared with the preset threshold through the controller. According to the comparison result, it is determined whether to perform the iteration process. For the output stage, when the iteration operation is completed, a stop signal is sent through the controller, and the result is refreshed to the main memory through the storage unit, and then the output data is prepared through the output unit, and the final result is output through the I / O unit. The final result is the optimal solution of the linear equation Ax=b.

[0143] In this embodiment, the generalized Richardson iteration method is combined with the SIMD hardware architecture, which fully utilizes the parallel processing capability of SIMD instructions, accelerates matrix solving operations, improves the computational efficiency and performance of the generalized Richardson iteration method, and provides a basis for future hardware upgrades and performance expansions. The results are stored to avoid data loss and achieve result reuse.

[0144] In an optional embodiment of the present application, the efficiency of divide-and-conquer data processing can be improved by using the SIMD hardware architecture, wherein the SIMD hardware architecture includes multiple computing units. The specific process includes:

[0145] Split the data model to be processed into multiple data processing sub-models;

[0146] Sending each of the data processing sub-models to each of the computing units for parallel iterative calculations to obtain calculation results of each of the computing units;

[0147] Integrate and process the calculation results according to a preset data processing method to obtain an iterative calculation result of the data model to be processed;

[0148] For each iterative operation, the obtained iterative calculation result and the displacement amount when merging in the corresponding divide-and-conquer method are sent to each of the calculation units for parallel iterative operation to obtain each array element respectively;

[0149] Each of the array elements is integrated to obtain an updated calculation array.

[0150] In an optional embodiment of the present application, the data model to be processed is a tridiagonal matrix model in the divide-and-conquer method; correspondingly, the data processing sub-model is a data iterative processing model.

[0151] In an optional embodiment of the present application, the data model to be processed is:

[0152] v(i)=(orig(j)+tau(j)-delta(i))*(1 / (delta(j)-delta(i)))

[0153] Correspondingly, the plurality of data processing sub-models include at least one of the following two data processing sub-models:

[0154] The first data processing sub-model: orig(j)+tau(j)-delta(i)

[0155] Second data processing submodel: 1 / (delta(j)-delta(i))

[0156] Among them, (orig(j)+tau(j)-delta(i))*(1 / (delta(j)-delta(i))) represents the data model to be processed, v(i) represents the single vector eigenvalue obtained by the i-th solution, orig(j) represents the vertical initial vector eigenvalue of the matrix, tau(j) represents the vertical correction scaling factor of the vector eigenvalue in the vertical direction of the matrix, delta(i) represents the horizontal displacement when merging arrays in the divide-and-conquer method, delta(j) represents the vertical displacement when merging arrays in the divide-and-conquer method, i represents the horizontal index of the matrix, j represents the vertical index of the matrix, and i≠j.

[0157] In an optional embodiment of the present application, the plurality of data processing sub-models include the first data processing sub-model and the second data processing sub-model. Correspondingly, the calculation results are integrated and processed according to a preset data processing method to obtain the iterative calculation result of the data model to be processed, including:

[0158] The first calculation result of the first data processing sub-model and the second calculation result of the second data processing sub-model are multiplied to obtain the iterative calculation result.

[0159] In an optional embodiment of the present application, for the first data processing sub-model, sending each of the data processing sub-models to each of the computing units for parallel iterative calculations to obtain calculation results of each of the computing units at least includes:

[0160] Sending each of the lateral displacements to each of the calculation units respectively, and sending the first sum of the first longitudinal initial eigenvalue and the first longitudinal correction scaling factor to each of the calculation units respectively for parallel iterative calculation to obtain a first iterative calculation result;

[0161] The sums of the other longitudinal initial eigenvalues ​​and the corresponding longitudinal correction scaling factors are sequentially sent to the calculation units for parallel iterative calculations, and the iterative calculation results are sequentially obtained;

[0162] For each of the calculation units, all iterative calculation results are integrated to obtain a first calculation result of the calculation unit; wherein the first calculation result refers to the calculation result of the first data processing sub-model.

[0163] In an optional embodiment of the present application, for the second data processing sub-model, sending each of the data processing sub-models to each of the computing units for parallel iterative calculations to obtain calculation results of each of the computing units at least includes:

[0164] Sending each of the lateral displacements to each of the calculation units respectively;

[0165] Sending the first longitudinal displacement to each of the calculation units respectively, and each of the calculation units respectively calculating the difference between the first longitudinal displacement and each of the lateral displacements;

[0166] The other longitudinal displacements are sent to the calculation units in sequence, and the calculation units calculate the difference between the other longitudinal displacements and the lateral displacements in sequence;

[0167] The difference values ​​obtained each time are integrated and the inverse is calculated to obtain the second calculation result of each calculation unit; wherein the second calculation result refers to the calculation result of the second data processing sub-model.

[0168] In an optional embodiment of the present application, for each iterative operation, the obtained iterative calculation result and the displacement amount when merging in the corresponding divide-and-conquer method are sent to each of the computing units for parallel iterative operation to obtain each array element respectively, including:

[0169] Sending the first calculation result and the first longitudinal displacement to each of the calculation units respectively, and each of the calculation units respectively calculates the first array element;

[0170] The other calculation results and the corresponding other longitudinal displacements are sent to each of the calculation units in turn, and each of the calculation units calculates and obtains other array elements respectively.

[0171] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0172] In another embodiment provided in the present application, a matrix operation device based on SIMD is also provided, see Figure 7 As shown, the device comprises:

[0173] The receiving module 810 is used to obtain multiple input parameters of the linear equation, the input parameters include: coefficient matrix, vector, initial solution vector, maximum number of iterations, convergence tolerance, relaxation factor; the coefficient matrix is ​​a square matrix;

[0174] A preprocessing module 820, configured to preprocess the coefficient matrix in response to the first SIMD instruction set, obtain a preprocessing matrix and calculate an inverse matrix of the preprocessing matrix;

[0175] A segmentation module 830 is used to segment the preprocessing matrix and the corresponding inverse matrix to obtain a plurality of sub-blocks;

[0176] The processing module 840 is used for iteratively processing the initial solution vector according to the input parameters, the preprocessing matrix and the inverse matrix in parallel for each sub-block in response to the second SIMD instruction set, so as to determine the optimal solution of the linear equation.

[0177] Optionally, the preprocessing module 820 is specifically configured to:

[0178] In response to the first SIMD instruction set, diagonal elements of the coefficient matrix are obtained in parallel, a diagonal matrix is ​​formed according to the diagonal elements, and the diagonal matrix is ​​used as a preprocessing matrix;

[0179] In response to the first SIMD instruction set, the coefficient matrix is ​​decomposed incompletely in parallel to obtain a first decomposition result and the first decomposition result is used as a preprocessing matrix; the first decomposition result is the product of an upper triangular matrix and a lower triangular matrix;

[0180] In response to the first SIMD instruction set, when the coefficient matrix is ​​a symmetric positive definite matrix, Cholesky decomposition is performed on the symmetric positive definite matrix in parallel to obtain a second decomposition result and use the second decomposition result as a preprocessing matrix.

[0181] Optionally, the processing module 840 is specifically configured to:

[0182] In response to the second SIMD instruction set, the current residual vector is calculated according to the coefficient matrix, the solution vector of the current iteration step and the vector; when the current iteration step is executed for the first time, the solution vector of the current iteration step is the initial solution vector, and when the current iteration step is not executed for the first time, the solution vector of the current iteration step is the updated solution vector of the previous iteration step;

[0183] Update the solution vector space according to the relaxation factor, the solution vector of the current iteration step, the inverse matrix, and the current residual vector;

[0184] Based on the current residual vector, determine whether the iterative process meets the convergence condition;

[0185] When the iterative process meets the convergence condition, the solution vector of the current iteration step that meets the convergence condition is taken as the optimal solution of the linear equation.

[0186] Optionally, the processing module 840 is further configured to:

[0187] Get the number of data operations performed in a single cycle;

[0188] In response to the second SIMD instruction set, a preset algorithm is used to update the solution vector of the current iteration step according to the number of data operations, relaxation factor, inverse matrix, and current residual vector to obtain an updated solution vector; the preset algorithms include: matrix-vector multiplication, vector multiplication and accumulation, vector multiplication, and matrix decomposition.

[0189] Optionally, the processing module 840 is further configured to:

[0190] Obtain the granularity of data loaded by the system, the granularity size of a single data, the number of components used for calculation after data loading, and the parallelism of data processing;

[0191] The number of data operations performed in a single cycle is calculated based on the granularity of the data loaded by the system, the granularity size of a single data, the number of components used for calculation after the data is loaded, and the parallelism of data processing.

[0192] Optionally, the processing module 840 is further configured to:

[0193] According to the current residual vector, the norm of the current residual vector is calculated; the norm of the current residual vector is used to characterize the size of the current residual;

[0194] Compare the norm of the current residual vector with a preset threshold;

[0195] When the norm of the current residual vector is less than a preset threshold, it is determined that the iterative process meets the convergence condition; when the norm of the current residual vector is not less than the preset threshold, it is determined that the iterative process does not meet the convergence condition.

[0196] Optionally, the above device is also used for:

[0197] Store the optimal solution of the linear equation into the target register;

[0198] Store the result of the computation in the destination register to the destination memory location.

[0199] For the specific definition of the above-mentioned SIMD-based matrix operation device, please refer to the definition of the SIMD-based matrix operation method above, which will not be repeated here. Each module in the above-mentioned SIMD-based matrix operation device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0200] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 1 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a SIMD-based matrix operation method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the SIMD-based matrix operation method as described above is implemented.

[0201] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above SIMD-based matrix operation method can be implemented.

[0202] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0203] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0204] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0205] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0206] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0207] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A matrix operation method based on SIMD, characterized in that: Applied to a single instruction multiple data (SIMD) architecture, the SIMD-based matrix operation method includes: Acquire multiple input parameters of the linear equation, the input parameters including: coefficient matrix, vector, initial solution vector, maximum number of iterations, convergence tolerance, relaxation factor; the coefficient matrix is ​​a square matrix; In response to a first SIMD instruction set, preprocessing the coefficient matrix to obtain a preprocessing matrix and calculating an inverse matrix of the preprocessing matrix; Segmenting the preprocessing matrix and the corresponding inverse matrix to obtain a plurality of sub-blocks; For each of the sub-blocks, in response to a second SIMD instruction set, an iterative algorithm is used to iteratively process the initial solution vector in parallel according to the input parameters, the preprocessing matrix and the inverse matrix to determine an optimal solution to the linear equation.

2. The method according to claim 1, characterized in that In response to the first SIMD instruction set, preprocessing the coefficient matrix to obtain a preprocessing matrix includes: In response to the first SIMD instruction set, the diagonal elements of the coefficient matrix are obtained in parallel, a diagonal matrix is ​​formed according to the diagonal elements, and the diagonal matrix is ​​used as the preprocessing matrix; In response to the first SIMD instruction set, the coefficient matrix is ​​subjected to incomplete LU decomposition in parallel to obtain a first decomposition result and the first decomposition result is used as the preprocessing matrix; the first decomposition result is the product of an upper triangular matrix and a lower triangular matrix; In response to the first SIMD instruction set, when the coefficient matrix is ​​a symmetric positive definite matrix, Cholesky decomposition is performed on the symmetric positive definite matrix in parallel to obtain a second decomposition result and use the second decomposition result as the preprocessing matrix.

3. The method according to claim 1, characterized in that In response to the second SIMD instruction set, in parallel, according to the input parameters, the preprocessing matrix and the inverse matrix, an iterative algorithm is used to iteratively process the initial solution vector to determine the optimal solution of the linear equation, including: In response to the second SIMD instruction set, a current residual vector is calculated according to the coefficient matrix, the solution vector of the current iteration step and the vector; when the current iteration step is executed for the first time, the solution vector of the current iteration step is the initial solution vector, and when the current iteration step is not executed for the first time, the solution vector of the current iteration step is the solution vector updated in the previous iteration step; Update the solution vector space according to the relaxation factor, the solution vector of the current iteration step, the inverse matrix, and the current residual vector; Based on the current residual vector, determining whether the iterative process meets the convergence condition; When the iterative process meets the convergence condition, the solution vector of the current iterative step when the convergence condition is met is used as the optimal solution of the linear equation.

4. The method according to claim 3, characterized in that According to the relaxation factor, the solution vector of the current iteration step, the inverse matrix, and the current residual vector, updating the solution vector space includes: Get the number of data operations performed in a single cycle; In response to the second SIMD instruction set, a preset algorithm is used to update the solution vector of the current iteration step according to the number of data operations, the relaxation factor, the inverse matrix, and the current residual vector to obtain the updated solution vector; the preset algorithm includes: matrix-vector multiplication, vector multiplication and accumulation, vector multiplication, and matrix decomposition.

5. The method according to claim 4, characterized in that Get the number of data operations performed in a single cycle, including: Obtain the granularity of data loaded by the system, the granularity size of a single data, the number of components used for calculation after data loading, and the parallelism of data processing; The number of data operations performed in the single cycle is calculated based on the granularity of the data loaded by the system, the granularity size of a single data, the number of components used for calculation after the data is loaded, and the parallelism of data processing.

6. The method according to claim 3, characterized in that Based on the current residual vector, judging whether the iterative process satisfies a convergence condition includes: Calculating the norm of the current residual vector according to the current residual vector; the norm of the current residual vector is used to characterize the size of the current residual; Comparing the norm of the current residual vector with a preset threshold; When the norm of the current residual vector is less than a preset threshold, it is determined that the iterative process meets the convergence condition; when the norm of the current residual vector is not less than the preset threshold, it is determined that the iterative process does not meet the convergence condition.

7. The method according to claim 1, characterized in that The method further comprises: Storing the optimal solution of the linear equation into a target register; Store the calculation result in the target register to the target memory location.

8. A matrix operation device based on SIMD, characterized in that: The device comprises: An acquisition module is used to acquire multiple input parameters of the linear equation, wherein the input parameters include: a coefficient matrix, a vector, an initial solution vector, a maximum number of iterations, a convergence tolerance, and a relaxation factor; the coefficient matrix is ​​a square matrix; A preprocessing module, configured to preprocess the coefficient matrix in response to a first SIMD instruction set, obtain a preprocessing matrix and calculate an inverse matrix of the preprocessing matrix; A segmentation module, used for segmenting the preprocessing matrix and the corresponding inverse matrix to obtain a plurality of sub-blocks; A processing module is used for iteratively processing the initial solution vector according to the input parameters, the preprocessing matrix and the inverse matrix in parallel for each of the sub-blocks in response to a second SIMD instruction set, so as to determine the optimal solution of the linear equation.

9. A computer device comprising: A memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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