Read operation processing method for storage device and storage device

Abstract

The invention discloses a read operation processing method for a storage device and the storage device. The method is completed by a read processing program and a reread processing program, the read processing program writes read error information of each storage page of a first flash memory particle into a first linked list, and the reread processing program comprises the following steps: sequentially reading a plurality of pieces of read error information from the first linked list; determining an adaptive re-reading voltmeter for each piece of read error information; for each piece of read error information, multiple groups of read voltages are sequentially read from an adaptive re-reading voltmeter, multi-round re-reading is performed on the corresponding storage page based on the multiple groups of read voltages until data error correction succeeds, each round of re-reading comprises a first stage and a second stage, and in the multi-round re-reading of the multiple storage pages, the re-reading of the multiple storage pages is completed. And performing the first stage of one round of rereading of the next storage page at the second stage of one round of rereading of the previous storage page, wherein the first stage is different from the second stage. The method can improve the rereading efficiency.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of memory technology, and more specifically, to a read operation processing method for a storage device and a storage device. Background Art

[0002] Currently, many storage devices, such as USB flash memory, SD card, CF card, SSD, eMMC embedded storage card, UFS device, etc., use flash storage media, especially NAND flash storage media as the main storage media, and gradually become the mainstream form. Compared with the traditional magnetic media memory, the performance has made a qualitative leap. Flash storage media is composed of a large number of storage cells, each of which is composed of floating gate transistors. The charge stored in the floating gate level of the floating gate transistor will change over time.

[0003] For data security, such storage devices are generally equipped with an ECC (Error Check Correction) circuit for data recovery and error correction. The ECC circuit is set in the controller. In the data writing stage, the coded data generated based on the original data coding is stored in the flash storage medium. In the data reading stage, the data is read from the flash storage medium, and the error correction code (ECC) is used to correct a certain number of erroneous data bits and obtain the original data. The ECC circuit can reduce the bit error rate and improve the product yield.

[0004] In the data reading stage, before using the error correction code to correct the data, it is necessary to set a set of appropriate read voltages to be applied to the bit lines connected to the corresponding storage cells. If the grade of the flash memory storage medium is good, or in a good use environment (for example, the charge number in the floating gate level of the floating gate transistor does not change much), the data reading can be completed by using the default voltage once, but when the flash memory grade is poor or at the end of its life, or the use environment is not good, it is necessary to call the retry table for rereading. However, the prior art rereads in a first-in-first-out manner, resulting in a relatively slow error correction speed for the later read commands. It is necessary to wait until the final error correction result of the previously read erroneous read command is obtained before the error correction can begin, which is relatively inefficient. Summary of the invention

[0005] In view of the above problems, an object of the embodiments of the present disclosure is to provide a read operation processing method for a storage device and a storage device to solve the problems existing in the prior art.

[0006] According to a first aspect of an embodiment of the present disclosure, a read operation processing method for a storage device is provided, wherein the storage device comprises a controller and a flash memory storage medium, wherein the flash memory storage medium comprises a plurality of flash memory particles, each of which is configured with at least one reread voltage table, and the read operation processing method is performed by a read processing program and a reread processing program, wherein the read processing program writes read error information of each storage page of a first flash memory particle among the plurality of flash memory particles into a first linked list, and the reread processing program performs the following steps:

[0008] Reading a plurality of read error information from the first linked list in sequence;

[0009] For each read error message, determining an adapted re-read voltage table according to the targeted storage page;

[0010] For each read error information, multiple groups of read voltages are sequentially read from the adapted re-read voltage table, and multiple rounds of re-reading are performed on the targeted storage page based on the multiple groups of read voltages until the re-read data can be successfully corrected.

[0011] Among them, each round of rereading includes a first stage and a second stage. In multiple rounds of rereading of multiple storage pages, the first stage of a round of rereading of the next storage page is performed in the second stage of a round of rereading of the previous storage page, and the first stage is different from the second stage.

[0012] In some embodiments, determining an adapted re-read voltage table according to the targeted storage page includes:

[0013] The adapted reread voltage table is determined according to one or more of the number of write / erase times, the error data ratio, and the error occurrence location of the storage block where the targeted storage page is located.

[0014] In some embodiments, determining the adapted reread voltage table according to one or more of the number of write / erase times, the proportion of error data, and the location where the error occurs of the storage block where the targeted storage page is located comprises:

[0015] Obtaining a first index number according to the number of write / erase operations of the storage block where the targeted storage page is located;

[0016] Determine the error type according to the error data ratio and the error occurrence location, and obtain a second index number according to the error type;

[0017] The adapted reread voltage table is determined from at least one reread voltage table configured for the flash memory particle where the targeted storage page is located according to the first index number and the second index number.

[0018] In some embodiments, the reread processing procedure further includes:

[0019] The adapted re-read voltage table is loaded from the flash storage medium into the controller.

[0020] In some embodiments, the re-read voltage tables adapted to the multiple storage pages of the same storage block are the same re-read voltage tables.

[0021] In some embodiments, the first stage reads data from the flash storage medium to a register, and the second stage reads data from the register to a system memory.

[0022] In some embodiments, each node unit of the first linked list includes a bit map in addition to the read error information, and each element of the bit map is used to indicate whether the corresponding retry voltage table has been used.

[0023] In some embodiments, the read handler and the reread handler are implemented as firmware in the controller; the read handler writes the read error information of the storage page in the same flash memory particle into the same linked list, the number of linked lists is equal to the number of flash memory particles, and the read handler writes the read error information to one or more linked lists in parallel or serially; the reread handler reads the read error information from one or more linked lists and processes it, and the reread handler processes each linked list serially or in parallel.

[0024] According to a second aspect of an embodiment of the present disclosure, a controller of a storage device is provided, which is used to execute the above-mentioned read operation processing method.

[0025] According to a third aspect of an embodiment of the present disclosure, there is provided a storage device, comprising a coupled controller and a flash memory storage medium, wherein the controller is used to implement the above-mentioned read operation processing method.

[0026] In the read operation processing method provided by the embodiment of the present disclosure, in multiple rounds of rereading of multiple storage pages, the first stage of a rereading of the next storage page is performed in the second stage of a rereading of the previous storage page, so as to hide part of the time overhead of rereading the next storage page in the time overhead of rereading the previous storage page, thereby improving the rereading efficiency. Furthermore, the use of the rereading voltage table is indicated by a bit map to avoid omission of the rereading voltage table. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects, features and advantages of the embodiments of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0028] Figure 1 A schematic block diagram showing an exemplary host system;

[0029] Figure 2is a flow chart of a method for processing a read operation of a storage device according to an embodiment of the present disclosure;

[0030] Figure 3 The timing relationship of performing three rounds of rereading on three storage pages Page0 to Page2 according to one embodiment of the present disclosure is shown;

[0031] Figure 4 This is a schematic diagram of the principle of cache read of Nand type flash memory;

[0032] Figure 5 It is a flowchart of a method for processing a read operation of a storage device provided by another embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present disclosure based on the embodiments, but the embodiments of the present disclosure are not limited to these embodiments. In the detailed description of the embodiments of the present disclosure below, some specific details are described in detail. For those skilled in the art, the embodiments of the present disclosure can be fully understood without the description of these details. In order to avoid confusing the essence of the embodiments of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0034] The flowcharts and block diagrams in the accompanying drawings illustrate the possible system frameworks, functions and operations of the systems, methods and devices of the embodiments of the present disclosure. The boxes on the flowcharts and block diagrams can represent a module, a program segment or just a piece of code, and the modules, program segments and codes are all executable instructions for implementing the specified logical functions. It should also be noted that the executable instructions for implementing the specified logical functions can be recombined to generate new modules and program segments. Therefore, the boxes and the order of the boxes in the accompanying drawings are only used to better illustrate the processes and steps of the embodiments, and should not be used as a limitation on the invention itself.

[0035] Figure 1 1 is a schematic block diagram of an exemplary host system 100. The host system 100 is, for example, a personal computer, a notebook computer, or a server.

[0036] The host system 100 includes a host device 110 (e.g., a computer system including a main processor and a memory) and a storage device. The host device 110 may issue a host command to the storage device so that the storage device manages the host data stored in the storage device according to the command. For example, the host device 110 may be communicatively connected to the storage device (e.g., through a host interface 121) and issue various commands (e.g., READ, WRITE, UNMAP, REASSIGNBLOCK, TRIM, etc.) to the storage device. The storage device may store, update, read, and / or otherwise manage host data according to the address range prompted by the command. Once the command is executed, the storage device may transmit a response to the host device 110, indicating that the command has been successfully completed.

[0037] The storage device is composed of a controller 120 and a flash storage medium 130. The controller 120 includes a host interface 121, a processor 123, a cache unit 124 and a storage medium interface 128. The host interface 121 of the controller 120 is connected to the host device 110 for caching and transmitting host commands and host data. The processor 123 is connected to the host interface 121, the cache unit 124 and the storage medium interface 128, and the processor 123 parses the host command and performs corresponding operations. The cache unit 124 is, for example, a static random access memory (SRAM) and / or a dynamic random access memory (DRAM), which can be used to store the mapping relationship between the logical address and the physical address and some configuration data. The storage medium interface 128 includes an interface circuit for realizing data transmission between the controller 120 and the storage medium 130. The flash storage medium 130 includes a plurality of flash memory particles (dies), each of which is divided into a plurality of storage blocks (blocks), and each storage block is divided into a plurality of storage pages (pages).

[0038] The controller 120 may also include an ECC (Error Check Correction) circuit for data recovery and error correction. In addition, the controller 120 should also include various software programs, which, together with the above-mentioned hardware components, implement various management functions and data reading and writing. These software programs include a data writing program and a data reading program. The data writing program performs LDPC (Low Density Parity Check Code) encoding on the original data through the ECC circuit, generates storage data, and writes the storage data into the flash storage medium 130. The data reading program reads the storage data from the flash storage medium 130, and then performs LDPC decoding through the ECC circuit to obtain the original data, but if the number (or proportion) of erroneous data is too large and the ECC circuit fails to correct the error, then as described in the background technology, it is necessary to call a retry table for rereading.

[0039] In order to improve the rereading efficiency, the present disclosure provides a method as follows: Figure 2 As shown in Figure 1 The read operation processing method of the storage device shown. The read operation processing method can be implemented as a read processing program and a reread processing program presented in a software program. Among them, the read processing program is responsible for processing the read commands for each storage page, and specifically may include: for the read command, reading the corresponding storage page data based on the default read voltage, and then recovering and correcting the data through the ECC circuit to obtain the original data. For the storage page data that cannot be corrected by ECC, the read error information is recorded in a linked list. For the linked list, the read processing program writes the read error information of the storage page in the same flash memory particle into the same linked list. The number of linked lists is equal to the number of flash memory particles. The read processing program can write the read error information to one or more linked lists in parallel or serially; the reread processing program reads the read error information from one or more linked lists and processes it. The reread processing program can process each linked list serially or in parallel. After configuring the table, all read error information commands are sent in parallel, which can reduce the average delay of the read command after the read error. The flowchart of the reread processing program is as follows Figure 2 As shown below. Figure 1 Detailed Description Figure 2 Flowchart of the process.

[0040] In step S201, multiple read error information is read from the first linked list in sequence. The first linked list corresponds to the first flash memory particle, and the first flash memory particle is any one of the multiple flash memory particles of the flash memory storage medium 130. The first linked list refers to a linked list generated by the read processing program to store the read error information of each storage page in the first flash memory particle. The read error information may include the error location (corresponding to the storage block and storage page), the number of error data (or proportion), the error description, the error type, etc.

[0041] In step S202, for each read error message, an adapted reread voltage table is determined according to the storage page targeted. Each flash memory particle in the flash memory storage medium 130 is configured with at least one reread voltage table, which is stored in the flash memory storage medium 130 and / or the cache unit 124. After determining the adapted reread voltage table, it is determined whether the table is in the cache unit 124. If not, the table is uploaded from the flash memory storage medium 130 to the cache unit 124. How to retrieve to obtain the adapted reread voltage table depends on the organization and indexing method of the reread voltage table. For example, the adapted reread voltage table is determined according to one or more of the write / erase times of the storage block and the error type (the proportion of error data and the location where the error occurs). The adapted reread voltage table for each read error message can be one or more, and the adapted reread voltage tables for multiple read error messages can correspond to the same reread voltage table. In addition, each reread voltage table generally stores multiple groups of read voltages.

[0042] In step S203, for each read error information, multiple groups of read voltages are read in sequence from the adapted reread voltage table, and the targeted storage page is reread accordingly until the reread data is successfully corrected, and then the rereading is stopped.

[0043] Based on this embodiment, multiple read error information is read from the first linked list in sequence. For each read error information, a reread voltage table adapted to the targeted storage page is determined and obtained, and then multiple groups of read voltages are read from the reread voltage table in sequence. Data is reread based on the multiple groups of read voltages. If the reread data can be successfully corrected by the ECC circuit, data rereading is stopped.

[0044] Furthermore, each round of rereading includes two stages: the first stage and the second stage, and the first stage is different from the second stage. Generally, the first stage reads data from the flash storage medium to the register, and the second stage reads data from the register to the system memory. In multiple rounds of rereading of multiple storage pages, the first stage of a round of rereading of the next storage page is performed in the second stage of a round of rereading of the previous storage page. Figure 3 This is explained by taking this as an example. Figure 3 The timing relationship of three rounds of rereading of three storage pages Page0 to Page2 according to an embodiment of the present disclosure is shown. As shown in the figure, a round of rereading of each storage page from Page0 to Page2 includes a first stage and a second stage, and then the second stage of rereading Page0 is performed in the second stage of rereading Page1, and the first stage of rereading Page2 is performed in the second stage of rereading Page1. In this way, part of the overhead of rereading the next storage page can be hidden in the time overhead of rereading the previous storage page, thereby improving the efficiency of the rereading process.

[0045] according to Figure 3 For example, assume that Page2 is successfully corrected after 4 rounds of rereading, Page1 is successfully corrected after 8 rounds of rereading, and Page0 is successfully corrected after 10 rounds of rereading. Assume that the system frequency is 667Hz, then the time consumed in the second stage of each storage page is 94us, the time consumed in the first stage is 68us, and the remaining operations (such as setting the read voltage) can be considered to not occupy time overhead. The time required for a round of rereading according to the method of this embodiment is: 68+94*3=486us, and the time consumed for a round of rereading of Page0~Page2 is: 486*4+4*(68+94*2)+2*(68+94)=3292us. If the original method of rereading a storage page and then rereading the next storage page is followed, the time consumed is: 10*(68+94)+8*(68+94)+4*(68+94)=3564us. It can be seen that the time consumed by rereading in the manner of this embodiment is less than the time consumed by rereading one storage page and then rereading the next storage page.

[0046] Figure 4 This is a schematic diagram of the principle of cache read of Nand-type flash memory. In the first step, the data of storage page Page N of Nand-type flash memory is taken out and placed into the data register; in the second step, the data of Page N is taken out from the data register and placed into the cache register; in the third step, while the data of Page N is taken out from the cache register and placed into the system register, the data of storage page Page N+1 is taken out from the Nand-type flash memory and placed into the data register. At the same time, the operation completion (ready) signal of cache read is earlier than that of normal read. Therefore, for Nand-type flash memory, the mechanism provided by cache read can be used to complete multiple rounds of rereading of this embodiment.

[0047] Figure 5 FIG. 1 is a flowchart of a method for processing a read operation of a storage device provided by another embodiment of the present disclosure. Figure 2 The examples provide more details.

[0048] In step S501, the bitmap is cleared to zero, indicating that all re-read voltage meters are not used.

[0049] In step S502, the number of programming / erasing times of the corresponding storage block is obtained according to the read error information, and the first index number is determined according to the number of programming / erasing times.

[0050] In step S503, the error type is determined according to the error data ratio and the error occurrence location, and a second index number is obtained according to the error type. The error data ratio and the error occurrence location may be included in the read error information. In addition, the error type of this reread may be determined in combination with the past state (e.g., past error type) of the storage block where the storage page where the error occurs is located.

[0051] In step S504, the adapted reread voltage table is loaded from the flash memory storage medium into the cache unit of the controller, and the reread voltage table is used for rereading. The first index number and the second index number determine the name of the adapted reread voltage table.

[0052] In step S505, the corresponding bit in the bitmap is set to indicate that the corresponding re-read voltage table has been used.

[0053] In step S506, the next read error information to be processed in the linked list is read.

[0054] In step S507, it is determined whether there is a next read error message in the linked list. If yes, the process jumps to step S502 for execution. If not, the process ends.

[0055] In this embodiment, the reread voltage table is organized and indexed according to the number of write / erase times and the error type. As shown in Table 1, the first index number is determined according to the number of program / erase times, that is, when the number of program / erase times of a certain storage block is in the interval of [0~1 / 5] of the total number of program / erase times, the first index code is 1, when the number of program / erase times of a certain storage block is in the interval of [1 / 5~2 / 5] of the total number of program / erase times, the first index code is 2, and so on.

[0056] Table 1 Program / erase times 0~1 / 5 1 / 5~2 / 5 2 / 5~3 / 5 3 / 5~4 / 5 4 / 5~1 First index code 1 2 3 4 5

[0057] Referring to Table 2, the second index number is determined according to the error type, that is, when the error type is related to read disturbance, the second index number is *.1, when the error type is related to data retention, the second index number is *.2, and so on.

[0058] When the programming / erasing times of a storage block is in the range of [0~1 / 5] of the total programming / erasing times, the first index code is *.1; when the programming / erasing times of a storage block is in the range of [1 / 5~2 / 5] of the total programming / erasing times, the first index code is 2, and so on.

[0059] Table 2 Second index number Error Type *.1 Read disturb related tables *.2 Data retention related tables *.3 Open block related tables are mainly *.4 Mainly cross-temperature related tables

[0060] Then, the name of the adapted re-read voltage table is organized according to the first index number and the second index number. For example, if the first index number is 1 and the second index number is *.1, the adapted re-read voltage table is Table1.1. Of course, this is only an exemplary description, and the re-read voltage table can also be organized and indexed in other ways, and the embodiments of the present disclosure are not limited thereto.

[0061] In this embodiment, a bit map is used to indicate whether one or more adapted reread voltage tables have been used for each read error message, and the bit map may be a one-dimensional or two-dimensional table. Referring to Table 3, the bit map is in the form of a two-dimensional table, and each data in the table is a bit '0' or '1', where bit '0' indicates that the corresponding reread voltage table is not used, and bit '1' indicates that the corresponding reread voltage table has been used. For example, bit '1' in the third row and fourth column indicates that table2.3 has been used. Thus, by maintaining the bit map, the current usage of the reread voltage table can be determined. Furthermore, the bit map can be used to determine whether the adapted reread voltage table has been previously uploaded from the flash storage medium to the cache unit.

[0062] Table 3 table 1 2 3 4 5 *.1 0 0 0 0 0 *.2 0 0 1 0 0 *.3 0 0 0 0 0 *.4 0 0 0 0 0

[0063] In some embodiments, if the adapted re-read voltage table obtained according to the read error information cannot successfully correct the data error, other re-read voltage tables may be selected.

[0064] Accordingly, an embodiment of the present disclosure also provides a computer-readable storage medium for storing software program codes formed according to the data reading operation method.

[0065] Those skilled in the art will appreciate that the various modules or units of the data processing system according to the embodiments of the present disclosure can be implemented by hardware, firmware or software. Software, for example, includes coding programs formed by various programming languages ​​such as JAVA, C / C++ / C#, SQL, etc. Although the steps and the order of the steps of the embodiments of the present disclosure are given in the method and the method legend, the executable instructions for implementing the specified logical functions of the steps can be recombined to generate new steps. The order of the steps should not be limited to the order of the steps in the method and the method legend, and can be adjusted at any time according to the needs of the function. For example, some of the steps are executed in parallel or in reverse order.

[0066] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

[0067] The embodiments according to the embodiments of the present disclosure are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of the present disclosure, so that those skilled in the art can make good use of the embodiments of the present disclosure and the modified use based on the embodiments of the present disclosure. The embodiments of the present disclosure are limited only by the claims and their full scope and equivalents.

Claims

1. A read operation processing method for a storage device, the storage device comprising a controller and a flash memory storage medium, the flash memory storage medium comprising a plurality of flash memory particles, each flash memory particle being configured with at least one reread voltage table, the read operation processing method being completed by a read processing program and a reread processing program, the read processing program writing read error information of each storage page of a first flash memory particle among the plurality of flash memory particles into a first linked list, The reread processing procedure then performs the following steps: Reading a plurality of read error information sequentially from the first linked list; For each read error message, determining an adapted re-read voltage table according to the targeted storage page; For each read error information, multiple groups of read voltages are sequentially read from the adapted re-read voltage table, and multiple rounds of re-reading are performed on the targeted storage page based on the multiple groups of read voltages until the re-read data can be successfully corrected. Among them, each round of rereading includes a first stage and a second stage. In multiple rounds of rereading of multiple storage pages, the first stage of a round of rereading of the next storage page is performed in the second stage of a round of rereading of the previous storage page, and the first stage is different from the second stage.

2. The read operation processing method according to claim 1, wherein: The step of determining an adapted reread voltage table according to the targeted storage page comprises: The adapted reread voltage table is determined according to one or more of the number of write / erase times, the error data ratio, and the error occurrence location of the storage block where the targeted storage page is located.

3. The read operation processing method according to claim 2, wherein: The method of determining the adapted reread voltage table according to one or more of the number of write / erase times, the proportion of error data, and the location where the error occurs of the storage block where the targeted storage page is located comprises: Obtaining a first index number according to the number of write / erase operations of the storage block where the targeted storage page is located; Determine the error type according to the error data ratio and the error occurrence location, and obtain a second index number according to the error type; The adapted reread voltage table is determined from at least one reread voltage table configured for the flash memory particle where the targeted storage page is located according to the first index number and the second index number.

4. The read operation processing method according to claim 1 or 2, wherein: The reread processing procedure also includes: The adapted re-read voltage table is loaded from the flash storage medium into the controller.

5. The read operation processing method according to claim 1, wherein: The re-read voltage tables adapted to the multiple storage pages of the same storage block are the same re-read voltage tables.

6. The read operation processing method according to claim 1, wherein: The first stage reads data from the flash storage medium to a register, and the second stage reads data from the register to a system memory.

7. According to the read operation processing method according to claim 1 or 2, each node unit of the first linked list not only contains the read error information, but also contains a bit map, and each element of the bit map is used to indicate whether the corresponding retry voltage table has been used.

8. The read operation processing method according to claim 1, wherein: The read processing program and the re-read processing program are implemented as firmware in the controller; the read processing program writes the read error information of the storage page in the same flash memory particle into the same linked list, the number of linked lists is equal to the number of flash memory particles, and the read processing program writes the read error information to one or more linked lists in parallel or serially; The re-read processing program reads the read error information from one or more linked lists and processes the information. The re-read processing program processes each linked list in series or in parallel.

9. A controller of a storage device, configured to execute the read operation processing method according to any one of claims 1 to 8.

10. A storage device comprising a coupled controller and a flash memory storage medium, wherein the controller is used to implement the read operation processing method according to any one of claims 1 to 8.

Images