Chip and starting and testing method thereof, electronic equipment and storage medium

Abstract

The invention discloses a chip and a starting and testing method thereof, electronic equipment and a storage medium, and is applied to the field of chip starting and testing. The method comprises the steps that a chip is powered on and reset; a starting mode is changed, and the slave SRAM is selected to be started; a non-Debug logic reset request is initiated to the chip; the chip responds to the non-Debug logic reset request; the non-Debug logic of the chip is reset and released; the SRAM executes a boot program. The starting mode is changed through the processor, the test starting address SRAM is flexibly selected, under the condition that power-on reset and system reset do not need to happen, a starting program is flexibly debugged, repeated erasing of Flash is avoided, the test time is shortened, and the test efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of chip startup testing, and in particular to a chip and startup and testing methods thereof, an electronic device and a storage medium. Background Art

[0002] With the continuous development of chips, the application of chips in various fields of social life is becoming more and more extensive. At present, a boot ROM is deployed on the chip, and the boot firmware is stored in the boot ROM. After the chip is powered on, the processor on the chip can start the chip based on the boot firmware. When designing a chip, the default startup method of the chip is usually to start from Flash, which is also the most common startup method. The program instructions are stored in the Flash memory, and the instructions are directly read from the Flash for execution after power-on. However, if the startup program needs to be debugged during testing, it is often necessary to power on and reset again, and download the iterated startup program to the Flash. This method makes it impossible to debug the program in real time, and the Flash is frequently erased and written, which increases the extra testing time.

[0003] When designing a chip, the boot mode is usually selected by setting the IO interface. When the number of IO interfaces is limited or cannot be reused, the boot mode is rewritten by accessing the internal register. When testing internal devices or modules of a chip, analog devices are particularly difficult to test, and when testing modules, there are problems such as constantly debugging the test program, repeatedly downloading the debug program, and difficulty observing analog signals.

[0004] Based on this, a new technical solution is needed. Summary of the invention

[0005] The present invention provides a chip and a startup and test method thereof, an electronic device and a storage medium, so as to realize flexible debugging of a startup program, avoid repeated erasure of Flash, shorten the test time and improve the test efficiency.

[0006] The first object of the present invention is to provide a method for starting and testing a chip, which specifically comprises the following steps:

[0007] Chip power-on reset;

[0008] Change the boot mode and choose to boot from SRAM;

[0009] Initiate a non-Debug logic reset request to the chip;

[0010] The chip responds to the non-Debug logic reset request;

[0011] Reset the non-Debug logic of the chip and release it;

[0012] The SRAM executes the boot procedure.

[0013] Furthermore, the method further comprises the steps of:

[0014] Download the device under test program to SRAM;

[0015] Sending a download completion flag to the outside through the IO interface, and judging whether the program of the device under test has been downloaded;

[0016] If the download is not complete, continue to wait for the download;

[0017] If the downloading is completed, starting the device under test;

[0018] Determining whether the device under test is an analog module;

[0019] If yes, configure the pin and input the stimulus value to be tested;

[0020] The analog information output by the device under test is monitored.

[0021] Furthermore, it also includes:

[0022] If the device under test is not an analog module, inputting an expected value of the test result;

[0023] Monitoring output data of the device under test;

[0024] Comparing the output data with the expected result value;

[0025] If the output data is within the expected value of the result, the test ends;

[0026] If the output data is not within the expected result value, the expected result value is re-entered and the test is performed again.

[0027] Furthermore, before the chip is powered on and reset, the process further includes:

[0028] Unlock Debug resources;

[0029] Access the Debug module and initiate a debugging request;

[0030] Check whether it is in debugging state;

[0031] If it is in debugging state, start to execute the next step;

[0032] If it is not in debugging state, continue querying until it enters debugging state.

[0033] A second object of the present invention is to provide a chip, comprising a first chip startup device and a second chip startup device;

[0034] The first chip startup device includes a first processor, a Debug module, a startup mode controller module, and a Memory bank controller;

[0035] The first processor is used to execute chip startup, specifically including power-on reset of the chip;

[0036] The memory bank controller and the boot mode controller module are used to configure the SRAM start address, specifically including changing the boot mode and selecting to boot from SRAM;

[0037] The startup mode controller modules are connected to the first processor via a Bus matrix; the first processor and the Debug module can both control the startup mode controller modules.

[0038] Furthermore, the second chip startup device includes a Debug module and a second processor;

[0039] The debug module is connected to the second processor via a bus matrix; both the second processor and the debug module can control the startup mode controller module.

[0040] Furthermore, the Debug module is used to flexibly debug the startup program and flexibly configure the pins to select different startup modes, including:

[0041] Initiate a non-Debug logic reset request to the chip;

[0042] The chip responds to the non-Debug logic reset request;

[0043] Release the non-debug logic reset of the chip.

[0044] Furthermore, the first processor and the second processor are both provided with SRAM and Flash storage blocks;

[0045] The SRAM is used to execute the startup program and store the device under test program, specifically including:

[0046] Download the device under test program to SRAM;

[0047] Sending a download completion flag to the outside through the IO interface, and judging whether the program of the device under test has been downloaded;

[0048] If the download is not complete, continue to wait for the download;

[0049] If the downloading is completed, starting the device under test;

[0050] Determining whether the device under test is an analog module;

[0051] If yes, configure the pin and input the stimulus value to be tested;

[0052] Monitoring analog information output by the device under test;

[0053] If the device under test is not an analog module, inputting an expected value of the test result;

[0054] Monitoring output data of the device under test;

[0055] Comparing the output data with the expected result value;

[0056] If the output data is within the expected value of the result, the test ends;

[0057] If the output data is not within the expected result value, the expected result value is re-entered and the test is performed again.

[0058] The third object of the present invention is to provide an electronic device, comprising: a memory on which a program code is stored; a processor, which is connected to the memory and when the program code is executed by the processor, implements the chip startup and testing method described in any embodiment of the present invention.

[0059] A fourth object of the present invention is to provide a computer-readable storage medium having program instructions stored thereon, wherein the program instructions, when executed, implement the chip startup and testing method described in any embodiment.

[0060] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0061] The present application provides a chip startup and test method. In the absence of power-on reset and system reset, the processor can flexibly select the test start address according to the startup mode, and can choose to start from SRAM; in addition, this solution does not require power-on reset, can flexibly debug the startup program, avoid repeated erasing of Flash, shorten the test time, and improve test efficiency.

[0062] For the test of the device under test or the analog module, the present invention can perform real-time debugging during the test, and can also perform repeated debugging, thereby improving the debugging efficiency. By debugging the test program in the SRAM, the interrupt can be responded to more quickly. When testing the analog device, the pin configuration can be flexibly changed through the debug module, the analog stimulus can be reasonably input, and the analog output can be observed in real time, which is convenient for debugging and tracking, thereby reducing the test cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0064] Figure 1 This is a flowchart of a startup method of a chip startup and testing method provided in Embodiment 1 of the present invention;

[0065] Figure 2 This is a debugging preparation flow chart of a chip startup and testing method provided in Embodiment 1 of the present invention;

[0066] Figure 3 This is a test method flow chart of a chip startup and test method provided in Embodiment 2 of the present invention;

[0067] Figure 4 This is a schematic diagram of the structure of a chip provided in the third embodiment of the present invention. Figure 1 ;

[0068] Figure 5 This is a schematic diagram of the structure of a chip provided in the third embodiment of the present invention. Figure 2 ;

[0069] Figure 6 is a schematic diagram of an electronic device provided by a fourth embodiment of the present invention; Figure 7 It is a schematic diagram of a storage medium provided in Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0070] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0071] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0072] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0073] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0074] Embodiment 1

[0075] Figure 1 The present invention provides a flowchart of a chip startup and test method. The present invention is applicable to the case of changing the startup test program and real-time debugging test program during chip design. The method can be executed by a chip startup device, which can be implemented in the form of hardware and can be configured in an electronic device. Figure 1 As shown, a chip startup and testing method specifically includes the following steps:

[0076] S101: Chip power-on reset.

[0077] S102: Change the boot mode and select boot from SRAM.

[0078] Specifically, if you choose to boot from SRAM, you need to program the starting address of SRAM to 0x0000. However, the implementation of SRAM remapping is related to the processor. If the processor does not have a dedicated register to select remapping, then you need to make an external memory bank control register to configure the starting address of SRAM. If there is a register in the processor that can remap the address externally, the debug host can directly rewrite the remapping register inside the processor.

[0079] S103: Initiate a non-debug logic reset request to the chip.

[0080] It should be noted that this is a non-Debug logic reset request. This request resets the processor and other functions except the debug logic, and requests to leave the debug mode.

[0081] S104: The chip responds to a non-debug logic reset request.

[0082] Specifically, the chip exits the debug mode after responding to the non-Debug logic reset request.

[0083] S105: Reset and release the non-debug logic of the chip.

[0084] S106: SRAM executes the startup procedure.

[0085] In particular, if the startup program needs to be debugged or the exception vector table needs to be changed, you can repeat Figure 1 Steps S101 to S106 in the embodiment can avoid the time required for powering on again and repeatedly erasing the Flash.

[0086] It should be noted that before the chip is powered on and reset, the following steps are also performed:

[0087] S1: Unlock Debug module resources;

[0088] Specifically, after the chip is powered on and reset, the Debug lock register is accessed by configuring JTAG, and the secret key is entered to unlock the Debug resources.

[0089] The debug module resources include but are not limited to flexible debug pin assignment, support for different power modes and control of peripheral clocks, controllable debug reset and other reset logic. The debug host can establish a connection with the processor during system reset and program the processor debug registers. When the debug host releases the system reset through the debug module, the processor will stop immediately and will not execute any instructions. In addition, the debug features can be configured when the processor is in reset state.

[0090] S2: Access the Debug module and initiate a Debug request;

[0091] Specifically, after the debug host initiates a debug mode request, the debug host can control the processor through the external debug interface and can access the memory, all processor states, etc.

[0092] S3: Check whether it is in debugging state;

[0093] Specifically, if yes, execute S101;

[0094] If not, execute S4.

[0095] S4: Continue querying until entering the debugging state.

[0096] Specifically, the query method is recommended to poll the debug status register until the result of the register is 1, which can determine that the debug mode is in place.

[0097] According to the chip startup and testing method of the above-mentioned embodiment of the present invention, as well as the selection of the startup mode controlled by the Debug module, the startup program that is easy to regulate can control the processor to execute the program in the SRAM module, thereby saving testing time and reducing testing costs.

[0098] Embodiment 2

[0099] Figure 3 A test method flow chart of a chip startup and test method provided in the second embodiment of the present invention. Based on the above embodiment, this embodiment changes the chip startup mode and then starts the chip, and then performs device testing or analog module testing, and further includes the following steps:

[0100] S201: Download the device under test program to SRAM.

[0101] S202: Determine whether the program of the device under test has been downloaded.

[0102] Specifically, if the download is not completed, execute S201 to continue waiting for downloading;

[0103] If the download is complete, execute S203.

[0104] S203: Send a download completion flag to the outside of the chip through the IO interface.

[0105] S204: Start the device under test.

[0106] Among them, the IO interface can be a low-speed interface such as SPI, UART, etc. In this embodiment, the SPI interface is used to send a program download completion flag to the outside of the chip. When the debugging host outside the chip detects the SPI receiving interface test program download completion flag, the debugging host can send a program start flag to the SPI sending interface. If the debugging host does not detect that the SPI receiving interface has the expected flag data, it means that the test program has not been downloaded, and it is necessary to wait or re-download the test program.

[0107] S205: Determine whether the device under test is an analog module.

[0108] Specifically, if the device under test is an analog module, execute S206;

[0109] If the device under test is not an analog module, execute S208.

[0110] S206: Configure the pins and input the stimulus value to be tested.

[0111] S207: Monitor the analog information output by the device under test.

[0112] Specifically, if the test module is an analog device, the output is an analog signal or voltage. In order to monitor the results, the desired pins can be configured through the internal Debug module. The pins are connected to the output of the analog device, and the analog voltage can be observed or analog data can be collected at the interface. The Debug module flexibly configures the pins and completes it before monitoring the output of the analog information of the device under test, avoiding problems such as missing collected analog data.

[0113] S208: Input the expected value of the test result;

[0114] S209: monitoring output data of the device under test;

[0115] Specifically, when the test program starts running, the output data of the device under test is monitored and stored in a designated area. If the output data is digital information, the program will read and identify it, perform corresponding processing and store it in SRAM.

[0116] S210: Determine whether the output data is within the expected value of the result;

[0117] Specifically, if the output data is within the expected result value, execute S211;

[0118] If the output data is not within the expected result value, execute S212.

[0119] S211: The comparison is successful and the test ends;

[0120] S212: The comparison fails. Re-enter the expected result value and test again.

[0121] It should be noted that if the output is digital information, it will be compared with the expected value written, and whether it is within the expected value range, the comparison result and test data will be sent through the UART interface. When the comparison fails, the SPI transmission interface can be used to control the retest and debug the expected data.

[0122] If the output is analog information, there is no need to enter the comparison. The analog information can be processed outside the chip. When unexpected data is observed, the test can be restarted through the SPI interface control.

[0123] The above-mentioned real-time debuggable test method solves the problem that it is difficult to test analog devices inside the chip and difficult to monitor analog signals, optimizes the debug vector, and can monitor the test system in real time. Executing the test program in SRAM can respond to interrupts more quickly. The debug module can flexibly adjust the pins, facilitate the testing of analog devices, and collect analog information. In addition, the present invention optimizes the test system and can monitor and track in real time.

[0124] Embodiment 3

[0125] A chip such as Figure 4 , 5 , comprising a first chip startup device 100 and a second chip startup device 200;

[0126] The first chip startup device 100 includes a first processor 10, a debug module 20, a startup mode controller module 30, and a memory bank controller 40;

[0127] The first processor 10 is used to execute chip startup, specifically including chip power-on reset;

[0128] The memory bank controller 40 and the boot mode controller module 30 are used to configure the SRAM start address, including changing the boot mode and selecting to boot from SRAM;

[0129] The boot mode controller module 40 and the debug module 20 are both connected to the first processor 10 via a Bus matrix; the first processor 10 and the debug module 20 can both control the boot mode controller module 30 .

[0130] The second chip startup device 200 includes a Debug module 20 and a second processor 100;

[0131] The debug module 20 is connected to the second processor via a Bus matrix; both the second processor 100 and the debug module 20 can control the startup mode controller module 30 .

[0132] Specifically, the debug module 30 is used to flexibly debug the startup program and flexibly configure the pins to select different startup modes, including:

[0133] Initiate a non-Debug logic reset request to the chip;

[0134] The chip responds to non-Debug logic reset request;

[0135] Release the non-Debug logic reset of the chip.

[0136] It should be noted that at that time, both the first processor and the second processor are provided with SRAM and Flash storage blocks;

[0137] SRAM is used to execute the startup program and store the device under test program, including:

[0138] Download the device under test program to SRAM;

[0139] Send a download completion flag to the outside through the IO interface, and determine whether the program of the device under test has been downloaded;

[0140] If the download is not complete, continue to wait for the download;

[0141] If the download is complete, start the device under test;

[0142] Determine whether the device under test is an analog module;

[0143] If yes, configure the pin and input the stimulus value to be tested;

[0144] Monitor the analog information output by the device under test;

[0145] If the device under test is not an analog module, enter the expected value of the test result;

[0146] Monitor the output data of the device under test;

[0147] Compare the output data with the expected value of the result;

[0148] If the output data is within the expected value of the result, the test ends;

[0149] If the output data is not within the expected result value, re-enter the expected result value and test again.

[0150] Adding a debug module 20 outside the processor can respond faster to the startup program from SRAM, and can also debug the startup program repeatedly to improve debugging efficiency. The debug module 20 can also flexibly adjust the pins, facilitate the testing of analog devices and the collection of analog information.

[0151] When the processor is powered on or the system is reset, the processor can fetch instructions from 0x0000. To ensure that there are instructions at 0x0000 that can be executed when the system is powered on, the address 0x0000 is often designed to be ROM or Flash. However, in order to speed up the startup, change the exception vector table conveniently, and speed up the interrupt response, the exception vector table is mapped to a faster and wider (32bit / 16bit) SRAM. However, the starting address of the exception vector table is determined by the processor and must be located at the address 0x0000. Therefore, if you want to achieve startup from SRAM, you must map SRAM to 0x0000.

[0152] The implementation of SRAM remapping is related to the processor. If the processor does not have a dedicated register to select remapping, then an external memory bank control register is required to configure the starting address of the SRAM. The starting address of the SRAM needs to be programmed to 0x0000. Figure 4 The processor 10 in the chip startup device 100 does not have a dedicated register, so a memory bank controller 40 is set to specifically configure the start address of the SRAM and program the start address of the SRAM to 0x0000.

[0153] If the processor has a dedicated register to complete the address remapping, there is no need to externally make a memory bank control register to configure the starting address of the SRAM. Figure 5 , the chip startup device 200 is designed, and the processor 110 has a dedicated register to complete address remapping.

[0154] The above two devices are suitable for different processors. The processor 110 has a dedicated register to complete address remapping. On the contrary, there is no dedicated register in the processor 10 to complete address remapping. Through different processors, the test start address can be flexibly selected according to the startup mode, which shortens the test time and improves the test efficiency.

[0155] Embodiment 4

[0156] An electronic device 300, such as Figure 6 As shown, it includes: a memory 301 on which program codes are stored; a processor 302, which is connected to the memory and implements a chip startup and test method when the program codes are executed by the processor. For a detailed description of the method, reference can be made to the corresponding description in the above method embodiment, which will not be repeated here.

[0157] Embodiment 5

[0158] A computer readable storage medium 400, such as Figure 7 As shown, a program instruction 401 is stored thereon, and when the program instruction is executed, a chip startup and test method is implemented. For a detailed description of the method, reference may be made to the corresponding description in the above method embodiment, and no further description is given here.

[0159] The number of devices and processing scales described here are used to simplify the description of the present invention. Applications, modifications and variations of the present invention will be obvious to those skilled in the art.

[0160] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and implementation modes. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

[0161] The apparatus, electronic device, non-volatile computer storage medium and method provided in the embodiments of this specification correspond to each other, and therefore, the apparatus, electronic device and non-volatile computer storage medium also have similar beneficial technical effects as the corresponding method. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the corresponding apparatus, electronic device and non-volatile computer storage medium will not be repeated here.

[0162] Those skilled in the art also know that, in addition to implementing the controller in a purely computer-readable program code, the controller can be made to implement the same function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, such a controller can be considered as a hardware component, and the devices for implementing various functions included therein can also be considered as structures within the hardware component. Or even, the devices for implementing various functions can be considered as both software units for implementing the method and structures within the hardware component.

[0163] The systems, devices or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. For the convenience of description, the above devices are described separately by functions in various units. Of course, when implementing one or more embodiments of this specification, the functions of each unit can be implemented in the same or more software and / or hardware.

[0164] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification may be in the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the embodiments of this specification may be in the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0165] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0166] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0167] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0168] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0169] The specification may be described in the general context of computer-executable instructions executed by a computer, such as program units. Generally, program units include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communications network. In a distributed computing environment, program units may be located in local and remote computer storage media, including storage devices.

[0170] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0171] The above description is only an embodiment of this specification and is not intended to limit one or more embodiments of this specification. For those skilled in the art, one or more embodiments of this specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included in the scope of the claims of one or more embodiments of this specification.

Claims

1. A chip startup and testing method, characterized in that: The specific steps include: Chip power-on reset; Change the boot mode and choose to boot from SRAM; Initiate a non-Debug logic reset request to the chip; The chip responds to the non-Debug logic reset request; Reset the non-Debug logic of the chip and release it; The SRAM executes the boot procedure.

2. The chip startup and testing method according to claim 1, characterized in that: Also includes the steps: Download the device under test program to SRAM; Sending a download completion flag to the outside through the IO interface, and judging whether the program of the device under test has been downloaded; If the download is not complete, continue to wait for the download; If the downloading is completed, starting the device under test; Determining whether the device under test is an analog module; If yes, configure the pin and input the stimulus value to be tested; The analog information output by the device under test is monitored.

3. The chip startup and testing method according to claim 2, characterized in that: Also includes: If the device under test is not an analog module, inputting an expected value of the test result; Monitoring output data of the device under test; Comparing the output data with the expected result value; If the output data is within the expected value of the result, the test ends; If the output data is not within the expected result value, the expected result value is re-entered and the test is performed again.

4. The chip startup and testing method according to claim 1, characterized in that: The chip also includes the following steps before powering on and resetting: Unlock Debug resources; Access the Debug module and initiate a debugging request; Check whether it is in debugging state; If it is in debugging state, start to execute the next step; If it is not in debugging state, continue querying until it enters debugging state.

5. A chip, characterized in that: It includes a first chip startup device and a second chip startup device; The first chip startup device includes a first processor, a Debug module, a startup mode controller module, and a Memorybank controller; The first processor is used to execute chip startup, specifically including power-on reset of the chip; The memory bank controller and the boot mode controller module are used to configure the SRAM start address, specifically including changing the boot mode and selecting to boot from SRAM; The startup mode controller modules are connected to the first processor via a Bus matrix; the first processor and the Debug module can both control the startup mode controller modules.

6. The chip according to claim 5, characterized in that: The second chip startup device includes a Debug module and a second processor; The debug module is connected to the second processor via a bus matrix; both the second processor and the debug module can control the startup mode controller module.

7. The chip according to any one of claims 5 or 6, characterized in that: The Debug module is used to flexibly debug the startup program and flexibly configure the pins to select different startup modes, including: Initiate a non-Debug logic reset request to the chip; The chip responds to the non-Debug logic reset request; Release the non-debug logic reset of the chip.

8. The chip according to claim 5, characterized in that: The first processor and the second processor are both provided with SRAM and Flash storage blocks; The SRAM is used to execute the startup program and store the device under test program, specifically including: Download the device under test program to SRAM; Sending a download completion flag to the outside through the IO interface, and judging whether the program of the device under test has been downloaded; If the download is not complete, continue to wait for the download; If the downloading is completed, starting the device under test; Determining whether the device under test is an analog module; If yes, configure the pin and input the stimulus value to be tested; Monitoring analog information output by the device under test; If the device under test is not an analog module, inputting an expected value of the test result; Monitoring output data of the device under test; Comparing the output data with the expected result value; If the output data is within the expected value of the result, the test ends; If the output data is not within the expected result value, the expected result value is re-entered and the test is performed again.

9. An electronic device, characterized in that: include: A memory having program code stored therein; A processor is connected to the memory, and when the program code is executed by the processor, the startup and testing method of the chip as claimed in any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium, characterized in that: Program instructions are stored thereon, and when the program instructions are executed, the chip startup and testing method as described in any one of claims 1 to 8 is implemented.

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