Bus timeout monitoring method, device and system based on AXI protocol

Abstract

The embodiment of the invention discloses a bus timeout monitoring method, device and system based on an AXI protocol, which are applied to the bus timeout monitoring system and comprise at least one AXI host and at least one AXI slave, a plurality of communication channels sharing a watchdog counter are arranged between the AXI host and the AXI slave, and the AXI host and the AXI slave share the watchdog counter. The method comprises the following steps: initiating an access request to a target AXI slave through a target communication channel, and recording request information associated with the access request to a register array in the target communication channel; obtaining a timeout time point corresponding to the access request; if response information of the target AXI slave is not received when the value of the watchdog counter reaches the timeout time point, determining that the access request is timeout; and triggering interruption, and reporting request timeout according to the information recorded by the register array. According to the technical scheme provided by the embodiment of the invention, the overtime problem in AXI transmission can be solved, and the accuracy and the real-time performance of overtime detection are ensured.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a bus timeout monitoring method, device and system based on the AXI (Advanced eXtensible Interface) protocol. Background Art

[0002] The AMBA (Advanced Microcontroller Bus Architecture, AMBA) bus protocol is a type of high-performance, high-compatibility, and high-scalability chip-on-chip interconnection protocol, including APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), AXI (Advanced Extensible Interface), ACE (AXI Coherency Extensions), CHI (Coherent Hub Interface), etc., which are widely used in various types of SoC (System on Chip) chip designs.

[0003] Currently, the AXI protocol supports the following features: Out-of-order transmission, Outstanding transmission, and Interleaving transmission.

[0004] In complex SoCs, AXI hosts and slaves are connected through an interconnect matrix. As chip scale increases and chip core frequency increases, the host-slave matrix becomes more complex and flexible. However, the AXI protocol itself is not robust enough to meet all complex scenarios. Therefore, when the AXI host and slave interact, transactions may get stuck or not respond for a long time, resulting in bus transmission abnormalities. Summary of the invention

[0005] To solve the above technical problems, the embodiments of the present application provide a bus timeout monitoring method, device, system, electronic device, storage medium and program product based on the AXI protocol.

[0006] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0007] In a first aspect, a bus timeout monitoring method based on an AXI protocol is provided, which is applied to a bus timeout monitoring system, wherein the bus timeout monitoring system comprises at least one AXI host and at least one AXI slave, wherein a plurality of communication channels are arranged between the AXI host and the AXI slave, and the plurality of communication channels share a watchdog counter. The method is executed by the AXI host, and comprises: initiating an access request to a target AXI slave through a target communication channel, and recording request information associated with the access request to a register array in the target communication channel; obtaining a timeout time point corresponding to the access request; determining that the access request has timed out if no response information from the target AXI slave is received when the value of the watchdog counter reaches the timeout time point; triggering an interrupt, and reporting the request timeout according to the information recorded in the register array.

[0008] In one embodiment of the present application, based on the aforementioned scheme, after initiating an access request to the target AXI slave through the target communication channel, the method further includes: obtaining a timeout threshold corresponding to the access request, and obtaining the timeout time point according to the initiation time of the access request and the timeout threshold; recording the timeout time point to a timeout register corresponding to the register array; and opening a comparator corresponding to the timeout register, the comparator being used to determine whether the value of the watchdog counter reaches the timeout time point.

[0009] In one embodiment of the present application, based on the aforementioned scheme, obtaining the timeout threshold corresponding to the access request includes: obtaining an initial time threshold for the target AXI slave; obtaining an access type of the access request, adjusting the initial time threshold according to the access type, and obtaining the timeout threshold corresponding to the access request.

[0010] In one embodiment of the present application, based on the aforementioned scheme, the number of the access requests includes multiple, and one access request corresponds to one register array and one comparator; the method also includes: if a response message of the target AXI slave is received before the value of the watchdog counter reaches the timeout point, then searching for a target register array from multiple register arrays and searching for a target comparator from multiple comparators according to the response information; clearing the information recorded in the target register array, and stopping the target comparator.

[0011] In one embodiment of the present application, based on the aforementioned scheme, the information recorded by the register array includes an access ID; searching for a target register array from multiple register arrays according to the response information, and searching for a target comparator from multiple comparators, include: extracting a response ID from the response information; retrieving the access IDs recorded by each register array according to the response ID to obtain a target access ID that matches the response ID; using the register array that records the target access ID as the target register array, and determining a target comparator corresponding to the target register.

[0012] In one embodiment of the present application, based on the aforementioned scheme, the reporting of the request timeout according to the information recorded in the register array includes: reading the request information from the register array; determining the access type of the access request according to the type of the register array, and generating the timeout information for reporting according to the request information and the access type of the access request.

[0013] In one embodiment of the present application, based on the aforementioned scheme, the bus timeout monitoring protocol system includes at least two AXI hosts and at least two AXI slaves; before recording the request information corresponding to the access request into the register array in the target communication channel, it also includes: obtaining the slave address of the target AXI slave; obtaining the host number and host unique identifier of the AXI host itself, and concatenating the host number and the host unique identifier to obtain the host information; generating the request information according to the host information and the slave address.

[0014] In a second aspect, a bus timeout monitoring device based on the AXI protocol is provided, which is applied to a bus timeout monitoring system. The bus timeout monitoring system includes at least one AXI host and at least one AXI slave. Multiple communication channels are set between the AXI host and the AXI slave. The multiple communication channels share a watchdog counter. The device is deployed on the AXI host, including: a sending module, configured to initiate an access request to a target AXI slave through a target communication channel, and record request information associated with the access request to a register array in the target communication channel; an acquisition module, configured to obtain a timeout time point corresponding to the access request; a monitoring module, configured to determine that the access request has timed out if no response information from the target AXI slave is received when the value of the watchdog counter reaches the timeout time point; and a reporting module, configured to trigger an interrupt and report the request timeout according to the information recorded in the register array.

[0015] In a third aspect, a bus timeout monitoring system comprises at least one AXI host and at least one AXI slave, wherein a plurality of communication channels are arranged between the AXI host and the AXI slave, the plurality of communication channels share a watchdog counter, and the watchdog counter is used for counting; a plurality of register arrays for recording information are arranged in the communication channel; and the AXI host is used to execute the bus timeout monitoring method based on the AXI protocol as described in any one of the above items.

[0016] In one embodiment of the present application, based on the aforementioned scheme, the system also includes an interrupt controller for generating an interrupt based on the trigger of the AXI host; a plurality of comparators corresponding to the plurality of register arrays are also provided in the communication channel, and the comparators are used to determine whether the value of the watchdog counter reaches a timeout point.

[0017] In a fourth aspect, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the bus timeout monitoring method based on the AXI protocol as described in any one of the above items.

[0018] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor of an electronic device, the electronic device executes the bus timeout monitoring method based on the AXI protocol as described above.

[0019] In a sixth aspect, an embodiment of the present application provides a computer program product, including a computer program, wherein the computer program is stored in a computer-readable storage medium, and a processor of an electronic device reads and executes the computer program from the computer-readable storage medium, so that the electronic device executes the bus timeout monitoring method based on the AXI protocol as described above.

[0020] In the technical solution provided in the embodiments of the present application, in order to cope with the timeout problem in AXI transmission, a design scheme of a shared watchdog counter is proposed, allowing the communication channels between multiple AXI hosts and slaves to share a watchdog counter, thereby significantly reducing the system's power consumption and hardware area occupancy; when the host initiates an access request, the scheme will record the relevant request information in the register array, and determine whether the response information of the slave is received by detecting whether the watchdog counter reaches the timeout time point of the access request, thereby ensuring the accuracy and real-time performance of the timeout detection.

[0021] When a timeout occurs, the interrupt mechanism will be automatically triggered and the information recorded in the register array will be reported, allowing the chip to quickly locate the problem, ensuring that the AXI bus can still operate stably in high-performance, high-concurrency complex scenarios, and effectively handle timeout problems, avoiding data loss or system hangs due to transmission delays or device abnormalities, further improving the robustness and processing efficiency of the bus.

[0022] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 It is a schematic diagram of an implementation environment involved in this application.

[0025] Figure 2 It is a flowchart of a bus timeout monitoring method based on the AXI protocol shown in an exemplary embodiment of the present application.

[0026] Figure 3 Another exemplary embodiment of the present application is shown in Figure 2 The flowchart shows the steps of adding a timeout point for recording based on the time shown.

[0027] Figure 4 Another exemplary embodiment of the present application is shown in Figure 2 A flowchart of the clearing record process is added based on the shown.

[0028] Figure 5 Another exemplary embodiment of the present application shows Figure 2 Flowchart of step S240 in an exemplary embodiment.

[0029] Figure 6 It is a structural diagram of timeout monitoring of an AXI master and a slave shown in an exemplary embodiment of the present application.

[0030] Figure 7 It is a structural block diagram of a bus timeout monitoring device based on the AXI protocol shown in an exemplary embodiment of the present application.

[0031] Figure 8 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0032] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0033] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0034] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all contents and operations, nor must they be executed in the order described. For example, some operations may be decomposed, while some operations may be combined or partially combined, so the actual execution order may change according to actual conditions.

[0035] The present application is further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present application, but are not intended to limit the scope of the present application. Similarly, the following examples are only some embodiments of the present application rather than all embodiments, and all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of the present application.

[0036] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here, for example, can be implemented in an order other than those illustrated or described here. In addition, in the embodiments shown in the drawings, the indication of directions (such as up, down, left, right, front and back) is used to explain that the structure and movement of various elements of the present application are not absolute but relative. When these elements are in the positions shown in the drawings, these instructions are appropriate. If the instructions of the positions of these elements change, the instructions of these directions also change accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] It should also be noted that the "multiple" mentioned in this application refers to two or more than two. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship.

[0038] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of an application scenario of a bus timeout monitoring method based on the AXI protocol, shown in an exemplary embodiment of the present application. Figure 1 As shown, it includes at least one AXI host 10 and at least one AXI slave 20, and multiple communication channels 30 are set between the AXI host 10 and the AXI slave 20. For example, the multiple communication channels include a read channel and a write channel; the multiple communication channels 30 share a watchdog counter 40, and the host can send an access request to the slave through the communication channel, and a register array is set in the communication channel.

[0039] The AXI host initiates an access request to the target AXI slave through the target communication channel, and records the request information associated with the access request to the register array in the target communication channel; obtains the timeout time point corresponding to the access request; if no response information is received from the target AXI slave when the value of the watchdog counter reaches the timeout time point, it is determined that the access request has timed out; triggers an interrupt, and reports the request timeout according to the information recorded in the register array.

[0040] The target AXI slave may receive the access request sent by the AXI host through the target communication channel, generate response information according to the access request, and may send the response information to the target AXI host.

[0041] See also Figure 2 , Figure 2 FIG. 1 is a flowchart of a bus timeout monitoring method based on the AXI protocol, shown in an exemplary embodiment of the present application. Figure 2 As shown, the bus timeout monitoring method based on the AXI protocol is executed by any AXI host and may include steps S210 to S240.

[0042] S210 , initiating an access request to a target AXI slave through a target communication channel, and recording request information associated with the access request into a register array in the target communication channel.

[0043] In an embodiment of the present application, when an AXI host wants to access an AXI slave, it can select a target communication channel according to an access request. For example, if the access request is a write request, the selected target communication channel is the write channel; if the access request is a read request, the selected target communication channel is the read channel.

[0044] In one example, when the AXI host generates an access request, request information associated with the access request is generated. The request information does not involve the access content. For example, the request information includes the slave information of the target AXI slave, such as the address of the slave, the unique identifier of the slave, and the unique identifier of the AXI host. When the AXI host sends an access request, the AXI host records the request information to the register array in the target communication channel. It should be noted that since read and write transactions are separate, read and write requests each use independent register arrays.

[0045] In one example, the number of access requests may be one or more, and a group of register arrays is used to record request information corresponding to one access request.

[0046] S220: Obtain a timeout point corresponding to the access request.

[0047] In an embodiment of the present application, in order to avoid access requests being stuck or not being responded to for a long time, each access request corresponds to a timeout point, which can be pre-set or set when the access request is generated; the timeout points corresponding to the various access requests can be the same, or the timeout points corresponding to the various access requests can be different, for example, the timeout point of a read request is smaller than the timeout point of a write request. It can be understood that the timeout point corresponding to the access request can be flexibly adjusted according to actual conditions and is not limited here.

[0048] S230: If no response information from the target AXI slave is received when the value of the watchdog counter reaches the timeout time point, it is determined that the access request has timed out.

[0049] S240: trigger an interrupt, and report a request timeout according to the information recorded in the register array.

[0050] In an embodiment of the present application, the watchdog counter starts counting when the AXI host initiates an access request. The watchdog counter can be a decrementing counter, such as the counter decrements from the count value corresponding to the timeout time point until it decrements to 0; the watchdog counter can also be an incrementing counter, which increases based on the access time of the AXI host sending the access request until the timeout time point is reached; when the watchdog counter reaches the timeout time point of the access request, the host will check whether a response from the slave has been received; if no response is received, it is determined that the access request has timed out.

[0051] If the access request times out, it means that there is an abnormality in the transmission between the host and the slave. In order to avoid abnormal bus transmission caused by the abnormal situation, an interrupt needs to be triggered. The interrupt will notify the processor (CPU) that there is a timeout event that needs to be processed to ensure that the processor can respond and handle the abnormal situation in time. Through the interrupt mechanism, the processor can manage resources more effectively and avoid resource waste due to unresponsive requests.

[0052] In one example, the host determines that an access request has timed out, reads recorded information from a register array, sends the information to an interrupt controller, and the interrupt controller generates an interrupt and reports the information to indicate that a request timeout has occurred.

[0053] In one example, the information recorded by the register array includes request information of the access request. The recorded information needs to be read from the register array and reported to indicate that the interrupt is due to an access request timeout. In addition, the read information can be saved to an external debug register to avoid information loss. The processor can then execute a corresponding error handling procedure based on the reported information, such as retrying the request, recording an error log, or taking other corrective measures.

[0054] In an embodiment of the present application, in order to cope with the timeout problem in AXI transmission, a design scheme of a shared watchdog counter is proposed, which allows the communication channels between multiple AXI hosts and slaves to share a watchdog counter, thereby significantly reducing the power consumption and hardware area occupied by the system; when the host initiates an access request, the scheme will record the relevant request information in the register array, and determine whether the response information of the slave is received by detecting whether the watchdog counter reaches the timeout time point of the access request, thereby ensuring the accuracy and real-time performance of the timeout detection.

[0055] When a timeout occurs, the interrupt mechanism will be automatically triggered and the information recorded in the register array will be reported, allowing the chip to quickly locate the problem, ensuring that the AXI bus can still operate stably in high-performance, high-concurrency complex scenarios, and effectively handle timeout problems, avoiding data loss or system hangs due to transmission delays or device abnormalities, further improving the robustness and processing efficiency of the bus.

[0056] See also Figure 3 , Figure 3 FIG. 1 is a flowchart of a bus timeout monitoring method based on the AXI protocol shown in another exemplary embodiment of the present application. Figure 3 As shown in the figure, the bus timeout monitoring method based on AXI protocol is Figure 2 Based on the above, after initiating an access request to the target AXI slave, steps S310 to S330 may be further included.

[0057] S310: Obtain a timeout threshold corresponding to the access request, and obtain a timeout time point according to the sending time of the access request and the timeout threshold.

[0058] S320, recording the timeout time point into the timeout register corresponding to the register array.

[0059] S330: Turn on the comparator corresponding to the timeout register, where the comparator is used to determine whether the watchdog counter reaches the timeout point.

[0060] In an embodiment of the present application, an access request corresponds to a timeout threshold, which can be flexibly adjusted according to actual conditions, such as 10 minutes. When the host initiates an access request, the sending time of the access request is recorded, and the sum of the sending time and the timeout threshold is used as the timeout time point of the access request.

[0061] It should be noted that in the target communication tunnel, the register array, the timeout register and the comparator correspond one to one, and the timeout time point can be recorded in the timeout register corresponding to the register array, and the comparator corresponding to the timeout register can be turned on. The comparator is connected to the watchdog counter, and then the value output by the watchdog counter can be compared with the timeout time point to determine whether the timeout time point is reached, and then detect whether a timeout occurs.

[0062] It should be noted that the timeout threshold is fixed and applicable to most channels; however, as the complexity of the chip increases, different types of transactions may require different timeout strategies, so a dynamic timeout adjustment mechanism can be introduced.

[0063] In one example, obtaining a timeout threshold corresponding to an access request includes: obtaining an initial time threshold for a target AXI slave; obtaining an access type of the access request, and adjusting the initial time threshold according to the access type to obtain a timeout threshold corresponding to the access request.

[0064] In an embodiment of the present application, the host may set an initial time threshold for each AXI slave, where the initial time threshold is a fixed time threshold. The initial time thresholds corresponding to different AXI slaves may be the same or different. For example, the initial time threshold for the target AXI slave may be determined based on the past response time of the target AXI slave, such as taking the average response time of the target AXI slave over a period of time as the initial time threshold.

[0065] The host can dynamically adjust the time threshold based on the initial time threshold, where the access request corresponds to different access types, and different access types have different response requirements. Therefore, the initial time threshold is increased or decreased according to the access type of the access request to obtain the timeout threshold corresponding to the access request; wherein the increase or decrease of the initial time threshold can be flexibly adjusted.

[0066] For example, the initial time threshold of the target AXI slave set by the host is 8 minutes, and the access type of the access request is an instant read type, which requires an immediate response and may take a shorter time, so the 8 minutes is adjusted to 5 minutes as the timeout threshold; if the access type of the access request is a large amount of data write type, which requires an accurate response and takes a longer time, so the 8 minutes is adjusted to 15 minutes as the timeout threshold.

[0067] In the embodiment of the present application, by recording the timeout point in the timeout register and then turning on the comparator, and determining whether the watchdog has reached the timeout point through the comparator, it is possible to ensure that the timeout detection is accurate.

[0068] See also Figure 4 , Figure 4 FIG. 1 is a flowchart of a bus timeout monitoring method based on the AXI protocol shown in another exemplary embodiment of the present application. Figure 4 As shown, in Figure 2 On the basis of what is shown, a clearing record process is added, including step S410 to step S420.

[0069] S410: If a response message from the target AXI slave is received before the value of the watchdog counter reaches a timeout point, a target register array is searched from a plurality of register arrays and a target comparator is searched from a plurality of comparators according to the response message.

[0070] S420, clear the information recorded in the target register array, and stop the target comparator.

[0071] Among them, the number of access requests sent by the host to the target AXI slave includes multiple, and one access request corresponds to one register array and one comparator. Therefore, if the value of the watchdog counter reaches the timeout time point and it is detected that the response information of the target AXI slave has been received, it means that a target access request among the multiple access requests has not timed out, and the target access request is processed normally by the slave. Since the slave has responded to the access request, but the comparator is still running, it may mistakenly believe that the target access request has timed out, thereby triggering unnecessary interrupts. Since one access request corresponds to one register array and one comparator, there are multiple register arrays and multiple comparators. In order to avoid invalid timeout, it is necessary to find the corresponding target register array and target comparator, clear the information recorded in the target register array, and stop the target comparator to indicate that the target access request has been completed and no timeout monitoring is required. Among them, stopping the target comparator refers to resetting the target comparator and turning off the target comparator.

[0072] It is understandable that when the target AXI slave sends a response message, the access request responded by the target AXI slave can be obtained through the response message, so the response message can be used to search for the target register array from multiple register arrays and search for the target comparator from multiple comparators.

[0073] In one example, the information recorded by the register array includes an access ID, that is, the request information associated with the access request includes the access ID, and the access ID can be set by the host to generate the access request to uniquely identify the access request; the access ID is generated based on the unique identifier of the slave that the host wants to access (that is, the slave ID), that is, the access ID can both uniquely identify the access request and indicate the slave to be accessed; searching the target register array and the target comparator includes: extracting the response ID from the response information; retrieving the access ID recorded by each register array according to the response ID to obtain the target access ID that matches the response ID; using the register array that records the target access ID as the target register array, and determining the target comparator corresponding to the target register. The AXI host can extract the response ID from the response information. The response ID can be generated by the target AXI slave when generating a response message. The response ID can indicate the access ID to which the slave responds, and can also indicate the host itself. Therefore, the response ID can be consistent with the access ID, or the response ID can include the access ID. Each register array records the access ID of each access request. The extracted response ID can be compared one by one with the access ID recorded in each register array to determine the target access ID that matches the response ID, and then determine that the register array that records the target access ID is the target register array. The register array corresponds one by one to the comparator, so the target comparator corresponding to the target register can be determined.

[0074] In some embodiments of the present application, by clearing the corresponding register array and stopping the comparator when the slave responds, it can be ensured that only truly unresponded requests are marked as timed out, avoiding invalid timeout detection, improving the reliability and efficiency of the system, and ensuring that the timeout mechanism is only triggered when it is really needed.

[0075] See also Figure 5 , Figure 5 FIG. 1 is a flowchart of a bus timeout monitoring method based on the AXI protocol shown in another exemplary embodiment of the present application. Figure 5 As shown, Figure 5 Shows Figure 2 The flowchart of step S240 in the illustrated embodiment in an exemplary embodiment includes steps S510 to S520.

[0076] S510 , read request information from the register array.

[0077] S520: Determine the access type of the access request according to the type of the register array, and generate timeout information for reporting according to the request information and the access type of the access request.

[0078] In an embodiment of the present application, request information is read from the register array, such as the address of the target AXI slave, the unique identifier of the slave (ie, the slave ID), the access ID, etc., and the request information can be used to determine which slave has not responded.

[0079] As described above, the register arrays used for reading and writing are independent of each other. Therefore, the access type of the access request can be determined through the register array, whether it is a read access or a write access. The access type and request information are encapsulated to obtain the timeout information, such as concatenating the request information and the access type to obtain the timeout information, and the timeout information is reported. Subsequently, the specific circumstances of the timeout of the access request can be obtained based on the timeout information.

[0080] The bus timeout monitoring method provided in the embodiment of the present application not only supports a single host and a single slave, but also supports a single host and multiple slaves, and multiple hosts and multiple slaves. If the bus timeout monitoring system includes at least two AXI hosts and at least two AXI slaves, in order to facilitate the distinction between each host and slave, before recording the request information corresponding to the access request to the register array in the target communication channel, it also includes: obtaining the slave address of the target AXI slave; obtaining the host number and host unique identifier of the AXI host itself, and splicing the host number and the host unique identifier to obtain the host information; generating request information according to the host information and the slave address.

[0081] Among them, the host stores the slave address of each AXI slave, so the slave address of the target AXI slave can be extracted. Since the address and the slave are one-to-one corresponding, the slave information can be obtained from the address, and then determine which slave is not responding, so as to help quickly locate the problem device.

[0082] Since there are multiple hosts, the system can assign a unique number to each host. For example, host 0 is numbered 0, host 1 is numbered 1, host 2 is numbered 2, and host 3 is numbered 3. When initiating access, the host number and host ID can be concatenated to obtain the host information, and then the host information and slave address can be used as request information. The host information, slave address, slave ID and access ID can also be used as request information.

[0083] In case of timeout or response, the system can parse the request information to determine the specific host, thereby quickly locating which host initiated the timeout access and which slave did not respond.

[0084] See also Figure 6 , Figure 6 FIG. 1 is a schematic diagram of timeout monitoring of an AXI master and a slave according to an exemplary embodiment of the present application. Figure 6As shown, it can include multiple hosts and slaves, and also include an interrupt controller (INTC). There are read channels and write channels between the host and the slave, and each channel includes multiple groups of register arrays entry0~N, and multiple comparators with the same number of register arrays; each channel also includes an adder, and the above-mentioned timeout register is the timer value + adder warning value when the host sends a request; in order to deal with the timeout problem in AXI transmission, a watchdog mechanism is introduced. The following are two watchdog design solutions.

[0085] a) Alarm solution: A watchdog can be assigned to each AXI channel. The countdown starts after the host initiates access. If no response is received from the slave at the end of the countdown, it is considered a timeout.

[0086] b) Watchdog solution: Only one shared watchdog is needed. After the host initiates an access, the current time + timeout threshold is recorded as the timeout point of this access. If the watchdog counter reaches the timeout point and still has not received a response from the slave, it is considered a timeout.

[0087] Since the main source of power consumption of the chip is the frequently flipped signals and logic, the watch-watching solution is finally used. Figure 6 In the MCU, the read channel and the write channel share a watchdog (TIMER), which can save power consumption and area resources.

[0088] Since the AXI protocol supports outstanding reading and writing, multiple sets of register arrays are required to record the address and ID of this access, and the register arrays used for reading and writing are independent of each other and cannot be shared.

[0089] When the host wants to read the slave, it initiates a read request (RD_REQ) and an activation signal for the read request (RD _ACTIVE), records the address and ID of the slave into the register array, such as entry0, records the timeout point of this access (current time + timeout threshold) in the register corresponding to the array, and turns on the corresponding comparator (register array, timeout register and comparator correspond one to one).

[0090] At the same time, the watchdog starts counting when it receives the activation signal of the read request. For example, 15 minutes is considered a timeout, and the value of the timeout register is the current timer + 15 minutes. The comparator compares the watchdog value to see if it has reached the corresponding timeout point. If the corresponding slave response is not received at the timeout point, it is considered that the read request access has timed out. The comparator triggers the read signal (RD) to take out the information recorded in entry0 and send it to the INTC module to cause the INTC module to generate an interrupt, read out the recorded information and forward it to the CPU and save it in the external debug register. As long as the power is not turned off, the CPU can determine which access has timed out by reading these registers. Since the read and write register arrays are separated, it is easy to determine whether the timed-out transmission is a read access or a write access.

[0091] It can be understood that the slave can send response information and response activation status (RSP_ACTIVE) to the host. If the slave response information is received before the timeout period is reached, the response activation status is used to indicate that the host can clear the information recorded in the corresponding register array, reset and turn off the comparator to avoid invalid timeout detection; the host can extract the response ID from the response message, because the ID initiated by the host and the ID responded by the slave are the same, so the ID can be used as a register array label to determine the register array that needs to be cleared and the comparator that needs to be stopped.

[0092] In an embodiment of the present application, an AXI bus timeout monitoring scheme (watchdog scheme) based on a single watchdog is proposed. The timeout monitoring scheme supports monitoring of AXI read and write outstanding transmissions, wherein the recorded timeout information includes ID, address, and read and write type, but is not limited thereto. The recorded information can be used by system debuggers to help the system develop reasonable software and hardware solutions to improve the flexibility of the debugging system.

[0093] It should be noted that the present application is not limited to the use of the AMBA bus protocol. The same technical solution as above can be used for all buses that do not consider the functional safety design of automotive-grade chips to improve the reliability of on-board on-chip bus transmission.

[0094] Figure 7 1 is a schematic diagram of the structure of a bus timeout monitoring device based on the AXI protocol, which is shown in an exemplary embodiment of the present application. The device is applied to a bus timeout monitoring system, which includes at least one AXI host and at least one AXI slave. Multiple communication channels are set between the AXI host and the AXI slave. The multiple communication channels share a watchdog counter. The device is deployed on the AXI host, such as Figure 7 As shown, in an exemplary embodiment, includes.

[0095] The sending module 710 is configured to initiate an access request to a target AXI slave through a target communication channel, and record request information associated with the access request into a register array in the target communication channel.

[0096] The acquisition module 720 is configured to acquire a timeout point corresponding to the access request.

[0097] The monitoring module 730 is configured to determine that the access request has timed out if no response information from the target AXI slave is received when the value of the watchdog counter reaches a timeout time point.

[0098] The reporting module 740 is configured to trigger an interrupt and report the request timeout according to the information recorded in the register array.

[0099] In one embodiment of the present application, based on the aforementioned scheme, the device also includes a recording module; the recording module is configured to obtain a timeout threshold corresponding to an access request, and obtain a timeout time point according to the initiation time of the access request and the timeout threshold; record the timeout time point to a timeout register corresponding to the register array; open a comparator corresponding to the timeout register, and the comparator is used to determine whether the value of the watchdog counter reaches the timeout time point.

[0100] In one embodiment of the present application, based on the aforementioned scheme, the recording module is further used to obtain an initial time threshold for the target AXI slave; obtain the access type of the access request, adjust the initial time threshold according to the access type, and obtain a timeout threshold corresponding to the access request.

[0101] In one embodiment of the present application, based on the aforementioned scheme, the number of access requests includes multiple, and one access request corresponds to one register array and one comparator; the device also includes a clearing module, which is used to, if a response message from the target AXI slave is received before the value of the watchdog counter reaches a timeout point, search for the target register array from multiple register arrays and search for the target comparator from multiple comparators according to the response information; clear the information recorded in the target register array, and stop the target comparator.

[0102] In one embodiment of the present application, based on the aforementioned scheme, the information recorded by the register array includes an access ID; the clearing module is further used to extract the response ID from the response information; the access ID recorded by each register array is retrieved according to the response ID to obtain a target access ID that matches the response ID; the register array that records the target access ID is used as the target register array, and the target comparator corresponding to the target register is determined.

[0103] In one embodiment of the present application, based on the aforementioned scheme, the reporting module is further used to read request information from the register array; determine the access type of the access request according to the type of the register array, and generate timeout information for reporting based on the request information and the access type of the access request.

[0104] In one embodiment of the present application, based on the aforementioned scheme, the bus timeout monitoring protocol system includes at least two AXI hosts and at least two AXI slaves; the device also includes a generation module, which is configured to obtain the slave address of the target AXI slave; obtain the host number and host unique identifier of the AXI host itself, and concatenate the host number and the host unique identifier to obtain the host information; generate request information based on the host information and the slave address.

[0105] It should be noted that the device provided in the above embodiment and the bus timeout monitoring method based on the AXI protocol provided in the above embodiment belong to the same concept, and the specific manner in which each module and unit performs operations has been described in detail in the method embodiment and will not be repeated here.

[0106] An embodiment of the present application also provides a bus timeout monitoring system, comprising at least one AXI host and at least one AXI slave, wherein multiple communication channels are arranged between the AXI host and the AXI slave, wherein the multiple communication channels share a watchdog counter, and the watchdog counter is used for counting; multiple groups of register arrays for recording information are arranged in the communication channel; and the AXI host is used to execute the above-mentioned bus timeout monitoring method based on the AXI protocol.

[0107] In one embodiment of the present application, based on the aforementioned scheme, the system also includes an interrupt controller for generating an interrupt based on the trigger of the AXI host; a plurality of comparators corresponding to the plurality of register arrays are also provided in the communication channel, and the comparators are used to determine whether the value of the watchdog counter reaches a timeout point.

[0108] An embodiment of the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by one or more processors, the electronic device implements the bus timeout monitoring method based on the AXI protocol provided in the above-mentioned embodiments.

[0109] Figure 8 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown.

[0110] It should be noted that Figure 8 The computer system 800 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0111] like Figure 8 As shown, the computer system 800 includes a central processing unit (CPU) 801, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 802 or the program loaded from the storage part 808 to the random access memory (RAM) 803, such as executing the method in the above embodiment. In the RAM 803, various programs and data required for system operation are also stored. The CPU 801, the ROM 802 and the RAM 803 are connected to each other through the bus 804. The input / output (I / O) interface 805 is also connected to the bus 804.

[0112] The following components are connected to the I / O interface 805: an input section 806 including a keyboard, a mouse, etc.; an output section 807 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the I / O interface 805 as needed. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 810 as needed so that a computer program read therefrom is installed into the storage section 808 as needed.

[0113] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 809, and / or installed from a removable medium 811. When the computer program is executed by a central processing unit (CPU) 801, various functions defined in the system of the present application are executed.

[0114] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable medium may be any tangible medium containing or storing a program, which may be used by an instruction execution system, device or device or used in combination with it. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier, in which a computer-readable computer program is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. A computer program contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0115] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0116] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0117] Another aspect of the present application also provides a computer readable medium having a computer program stored thereon, which implements the bus timeout monitoring method based on the AXI protocol as described above when the computer program is executed by a processor. The computer readable medium may be included in the electronic device described in the above embodiment, or may exist independently without being assembled into the electronic device.

[0118] Another aspect of the present application also provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable medium. A processor of a computer device reads the computer instruction from the computer-readable medium, and the processor executes the computer instruction, so that the computer device executes the bus timeout monitoring method based on the AXI protocol provided in each of the above embodiments.

[0119] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. A person skilled in the art can easily make corresponding changes or modifications based on the main concept and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

Claims

1. A bus timeout monitoring method based on AXI protocol, characterized in that: The method is applied to a bus timeout monitoring system, the bus timeout monitoring system includes at least one AXI host and at least one AXI slave, a plurality of communication channels are set between the AXI host and the AXI slave, the plurality of communication channels share a watchdog counter, and the method is executed by the AXI host, including: Initiate an access request to a target AXI slave through a target communication channel, and record request information associated with the access request into a register array in the target communication channel; Obtaining a timeout point corresponding to the access request; If no response information from the target AXI slave is received when the value of the watchdog counter reaches the timeout time point, determining that the access request has timed out; An interrupt is triggered, and a request timeout is reported according to the information recorded in the register array.

2. The method according to claim 1, characterized in that After initiating an access request to the target AXI slave through the target communication channel, the method further includes: Obtaining a timeout threshold corresponding to the access request, and obtaining the timeout time point according to the initiation time of the access request and the timeout threshold; Recording the timeout time point into the timeout register corresponding to the register array; A comparator corresponding to the timeout register is turned on, where the comparator is used to determine whether the value of the watchdog counter reaches the timeout time point.

3. The method according to claim 2, characterized in that The obtaining a timeout threshold corresponding to the access request includes: Obtaining an initial time threshold for the target AXI slave; An access type of the access request is obtained, and the initial time threshold is adjusted according to the access type to obtain a timeout threshold corresponding to the access request.

4. The method according to claim 2, characterized in that: The number of the access requests includes a plurality, and one access request corresponds to one register array and one comparator; the method further includes: If a response message from the target AXI slave is received before the value of the watchdog counter reaches the timeout time point, searching for a target register array from a plurality of register arrays and searching for a target comparator from a plurality of comparators according to the response message; The information recorded in the target register array is cleared, and the target comparator is stopped.

5. The method according to claim 4, characterized in that The information recorded in the register array includes an access ID; searching for a target register array from a plurality of register arrays and searching for a target comparator from a plurality of comparators according to the response information includes: Extracting a response ID from the response information; Retrieving the access IDs recorded in each register array according to the response ID to obtain a target access ID that matches the response ID; The register array recording the target access ID is used as a target register array, and a target comparator corresponding to the target register is determined.

6. The method according to claim 1, characterized in that The reporting of request timeout according to the information recorded in the register array includes: Reading the request information from the register array; The access type of the access request is determined according to the type of the register array, and timeout information is generated and reported according to the request information and the access type of the access request.

7. The method according to claim 1, characterized in that The bus timeout monitoring system includes at least two AXI hosts and at least two AXI slaves; before recording the request information corresponding to the access request into the register array in the target communication channel, it also includes: Obtaining the slave address of the target AXI slave; Obtain the host number and host unique identifier of the AXI host itself, and concatenate the host number and the host unique identifier to obtain host information; The request information is generated according to the master information and the slave address.

8. A bus timeout monitoring device based on AXI protocol, characterized in that: The invention is applied to a bus timeout monitoring system, the bus timeout monitoring system comprises at least one AXI host and at least one AXI slave, a plurality of communication channels are arranged between the AXI host and the AXI slave, the plurality of communication channels share a watchdog counter, and the device is deployed on the AXI host, comprising: a sending module configured to initiate an access request to a target AXI slave through a target communication channel, and record request information associated with the access request to a register array in the target communication channel; An acquisition module, configured to acquire a timeout time point corresponding to the access request; A monitoring module configured to determine that the access request has timed out if no response information from the target AXI slave is received when the value of the watchdog counter reaches the timeout time point; The reporting module is configured to trigger an interrupt and report the request timeout according to the information recorded in the register array.

9. A bus timeout monitoring system, comprising at least one AXI host and at least one AXI slave, wherein a plurality of communication channels are arranged between the AXI host and the AXI slave, wherein the plurality of communication channels share a watchdog counter, and the watchdog counter is used for counting; The communication channel is provided with a plurality of register arrays for recording information; The AXI host is used to execute the bus timeout monitoring method based on the AXI protocol as described in any one of claims 1 to 7.

10. The system according to claim 9, characterized in that The system also includes an interrupt controller for generating an interrupt based on the trigger of the AXI host; a plurality of comparators corresponding to the plurality of register arrays are also provided in the communication channel, and the comparators are used to determine whether the value of the watchdog counter reaches a timeout point.

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