Cholesky matrix decomposition inversion method based on FPGA
By dividing the matrix decomposition inversion process into three state machines, and using Cholesky decomposition and inverse matrix calculation, the problem of high consumption of FPGA hardware resources is solved, and efficient matrix inversion operation is realized.
Patent Information
- Application Number
- CN202411551152.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-02-18
AI Technical Summary
The existing Cholesky matrix decomposition inversion method based on FPGA has the problem of huge decomposition calculation operations and high hardware resource consumption.
The matrix decomposition inversion process is divided into three state machines, which perform LC matrix decomposition, find the inverse matrix Y of matrix C, and find the inverse matrix W of covariance matrix A. The matrix inverse operation is realized through Cholesky decomposition and inverse matrix calculation.
Through state machine division and element address indexing, the operation state flow is reduced, the consumption of FPGA hardware resources is reduced, and the calculation efficiency of matrix inversion is improved.
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Abstract
Description
Technical Field
[0001] The invention relates to the technical field of signal processing, and in particular to a Cholesky matrix decomposition inversion method based on FPGA. Background Art
[0002] In FPGA-based signal processing algorithms, it is often necessary to invert the covariance matrix in the calculation process. In order to use FPGA to implement the matrix inversion algorithm, the matrix inversion process needs to be decomposed into basic addition, subtraction, multiplication and division operations. General matrix inversion methods such as elementary transformation method, adjoint matrix method, Gaussian elimination method, etc. require a large number of determinant calculations, which are not suitable for FPGA due to the large amount of calculation, large storage space requirements and high resource consumption. The matrix decomposition method has a small amount of calculation and is easy to implement. Therefore, the matrix decomposition method is generally selected to implement matrix inversion in FPGA.
[0003] Matrix decomposition is to decompose a matrix into the product of some simple matrices, such as triangular matrices or unitary matrices. They all have certain characteristics and are easier to obtain inverse matrices. Common matrix decomposition methods include: singular value decomposition, LU decomposition, QR decomposition and Cholesky decomposition. Among them, the first three decomposition methods are to invert all reversible complex matrices. The algorithms are more complex and difficult to implement and use more resources. Cholesky decomposition is applicable to conjugate symmetric positive definite matrices. In signal processing algorithms, when the matrix to be inverted is the covariance matrix after autocorrelation, it has a conjugate symmetric characteristic, which meets the applicable scope of Cholesky decomposition.
[0004] However, the existing FPGA-based Cholesky matrix decomposition inversion method still has the problem of huge decomposition calculation volume and high hardware resource consumption. Summary of the invention
[0005] The purpose of the present invention is to solve at least one technical problem in the background technology and provide a Cholesky matrix decomposition inversion method based on FPGA.
[0006] To achieve the above object, the present invention provides a Cholesky matrix decomposition inversion method based on FPGA, comprising:
[0007] The matrix decomposition and inversion process is divided into three state machines, which respectively perform LC matrix decomposition, find the inverse matrix Y of matrix C, and find the inverse matrix W of covariance matrix A;
[0008] The first state machine performs Cholesky decomposition on the input covariance matrix A according to the address order of the elements in the matrix L and the matrix C, and obtains the lower triangular matrix C and the lower triangular matrix L. After the calculation is completed, the result is stored in the RAM corresponding to the matrix L and the matrix C, and the LC matrix decomposition is completed;
[0009] After completing the LC matrix decomposition, switch to the second state machine, the second state machine performs inverse calculation on the matrix C according to the address order of the elements in the matrix C and the matrix Y, and stores the calculation result in the matrix Y. After calculating and storing all the element data of the Y matrix, the inverse matrix Y of the matrix C is completed;
[0010] After completing the calculation of the inverse matrix Y of matrix C, switch to the third state machine. The third state machine performs inverse calculation on matrix L according to the address order of the elements in matrix L and matrix W, stores the calculation results in matrix W, calculates and stores the inverse matrix W element data of all covariance matrices A, and finally outputs matrix W.
[0011] According to one aspect of the present invention, the first state machine performs Cholesky decomposition on the input covariance matrix A to obtain a lower triangular matrix C and a lower triangular matrix L. The specific formula is:
[0012]
[0013] Among them, the covariance matrix A = R Y R after Cholesky decomposition Y =LDL H =CL H .
[0015] According to one aspect of the present invention, the second state machine completes the calculation of the inverse matrix Y of the matrix C according to the following calculation formula:
[0016]
[0017] According to one aspect of the present invention, AW=CL H W=E=CY, we can get L H W=Y, the third state machine calculates the covariance matrix R Y The inverse matrix The specific formula is:
[0018]
[0019] To achieve the above object, the present invention also provides a Cholesky matrix decomposition inversion system based on FPGA, comprising:
[0020] The state machine division module divides the matrix decomposition and inversion process into three state machines. The three state machines respectively perform LC matrix decomposition, find the inverse matrix Y of matrix C, and find the inverse matrix W of matrix A;
[0021] LC matrix decomposition module, the first state machine performs Cholesky decomposition on the input covariance matrix A according to the address order of the elements in the matrices L and C to obtain the lower triangular matrices C and L. After the calculation is completed, the results are stored in the RAM corresponding to the matrices L and C to complete the LC matrix decomposition;
[0022] The inverse matrix Y solving module switches to the second state machine after completing the LC matrix decomposition. The second state machine performs inverse calculation on the matrix C according to the address sequence of the elements in the matrix C and the matrix Y, and stores the calculation results in the matrix Y. After calculating and storing all the element data of the matrix Y, the inverse matrix Y of the matrix C is completed.
[0023] The inverse matrix W solving module, after completing the inverse matrix Y of matrix C, switches to the third state machine. The third state machine performs inverse calculation on matrix L according to the address order of the elements in matrix L and matrix W, stores the calculation results in matrix W, calculates and stores the inverse matrix W element data of all covariance matrices A, and finally outputs matrix W.
[0024] To achieve the above-mentioned purpose, the present invention also provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the FPGA-based Cholesky matrix decomposition inversion method as described above is implemented.
[0025] To achieve the above objectives, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the FPGA-based Cholesky matrix decomposition inversion method as described above is implemented.
[0026] According to the solution of the present invention, the present invention realizes the customization of matrix order and data bit width through parameterized design, which is convenient for future modification work; saves FPGA hardware resources through time-sharing multiplexing of RAM and multiplication, addition and division IP cores; and reduces the operation time by streamlining the operation state through element address indexing. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is a principle block diagram of the FPGA-based Cholesky matrix decomposition inversion method of Example 1;
[0028] Figure 2 is a state transition diagram of the first state machine of Example 1;
[0029] Figure 3 This is an element refresh sequence diagram of the first state machine of Example 1;
[0030] Figure 4 is a state transition diagram of the second state machine of Embodiment 1;
[0031] Figure 5 This is an element refresh sequence diagram of the second state machine of Example 1;
[0032] Figure 6 is a state transition diagram of the third state machine of Example 1;
[0033] Figure 7 This is an element refresh sequence diagram of the third state machine of Example 1;
[0034] Figure 8 and Fig. 9 This is the matrix inversion FPGA simulation timing diagram of Example 1;
[0035] Fig.10 This is a diagram of the theoretical simulation results of the matrix inversion module of Example 1 in Matlab;
[0036] Fig.11 This is a diagram of the matrix inversion FPGA calculation simulation results of Example 1. DETAILED DESCRIPTION
[0037] The present invention will now be discussed with reference to exemplary embodiments. It should be understood that the embodiments discussed are only to enable those skilled in the art to better understand and thus implement the present invention, rather than implying any limitation on the scope of the present invention.
[0038] As used herein, the term “including” and variations thereof are to be interpreted as open-ended terms meaning “including, but not limited to.” The term “based on” is to be interpreted as “based, at least in part, on.” The terms “one embodiment” and “an embodiment” are to be interpreted as “at least one embodiment.”
[0039] According to one embodiment of the present invention, a Cholesky matrix decomposition inversion method based on FPGA includes:
[0040] The matrix decomposition and inversion process is divided into three state machines, which respectively perform LC matrix decomposition, find the inverse matrix Y of matrix C, and find the inverse matrix W of matrix A;
[0041] The first state machine indexes the corresponding elements in the covariance matrix A that need to be multiplied, added, or divided at this time (i.e., performs Cholesky decomposition on the input covariance matrix A) according to the address order of the elements in the matrix L and the matrix C, and obtains the lower triangular matrix C and the lower triangular matrix L. After the calculation is completed, the result is stored in the RAM of the corresponding matrix L and the matrix C, and the LC matrix decomposition is completed;
[0042] After the LC matrix decomposition is completed, switch to the second state machine and repeat the above steps (i.e., the second state machine performs inverse calculation on matrix C according to the address order of the elements in matrix C and matrix Y, and stores the calculation results in matrix Y). After calculating and storing all the element data of matrix Y, the inverse matrix Y of matrix C is completed;
[0043] After completing the calculation of the inverse matrix Y of matrix C, switch to the third state machine. The third state machine performs inverse calculation on matrix L according to the address order of the elements in matrix L and matrix W, calculates and stores all the element data of the inverse matrix W of the covariance matrix A, calculates and stores the inverse matrix W of matrix A, and finally outputs matrix W.
[0044] Further, according to one embodiment of the present invention, the first state machine inputs a covariance matrix A=R Y Perform Cholesky decomposition (R Y =LDL H =CL H ), and obtain the lower triangular matrix C and the lower triangular matrix L. The specific formula is:
[0045]
[0046] Further, according to an embodiment of the present invention, the second state machine completes the calculation of the inverse matrix Y of the matrix C according to the following calculation formula:
[0047]
[0048] Further, according to one embodiment of the present invention, AW=CL H W=E=CY, we can get L H W=Y, the third state machine calculates the covariance matrix R Y The inverse matrix The specific formula is:
[0049]
[0050] According to the solution of the present invention, the present invention realizes the customization of matrix order and data bit width through parameterized design, which is convenient for future modification work; saves FPGA hardware resources through time-sharing multiplexing of RAM and multiplication, addition and division IP cores; and reduces the operation time by streamlining the operation state through element address indexing.
[0051] Furthermore, to achieve the above object, the present invention also provides a Cholesky matrix decomposition inversion system based on FPGA, comprising:
[0052] The state machine division module divides the matrix decomposition and inversion process into three state machines. The three state machines respectively perform LC matrix decomposition, find the inverse matrix Y of matrix C, and find the inverse matrix W of matrix A;
[0053] LC matrix decomposition module, the first state machine indexes the corresponding elements in the covariance matrix A that need to be multiplied, added or divided at this time according to the address order of the elements in the matrices L and C (i.e., performs Cholesky decomposition on the input covariance matrix A), obtains the lower triangular matrix C and the lower triangular matrix L, and after the calculation is completed, stores the results in the RAM of the corresponding matrices L and C to complete the LC matrix decomposition;
[0054] The inverse matrix Y solving module switches to the second state machine after completing the LC matrix decomposition. The second state machine performs inverse calculation on the matrix C according to the address sequence of the elements in the matrix C and the matrix Y, and stores the calculation results in the matrix Y. After calculating and storing all the element data of the matrix Y, the inverse matrix Y of the matrix C is completed.
[0055] The inverse matrix W solving module, after completing the inverse matrix Y of matrix C, switches to the third state machine. The third state machine performs inverse calculation on matrix L according to the address order of the elements in matrix L and matrix W, stores the calculation results in matrix W, calculates and stores the inverse matrix W element data of all covariance matrices A, and finally outputs matrix W.
[0056] Further, according to one embodiment of the present invention, the first state machine inputs a covariance matrix A=R Y Perform Cholesky decomposition (R Y =LDL H =CL H ), and obtain the lower triangular matrix C and the lower triangular matrix L. The specific formula is:
[0057]
[0058] Further, according to an embodiment of the present invention, the second state machine completes the calculation of the inverse matrix Y of the matrix C according to the following calculation formula:
[0059]
[0060] Further, according to one embodiment of the present invention, AW=CL H W=E=CY, we can get L H W=Y, the third state machine calculates the covariance matrix RY The inverse matrix The specific formula is:
[0061]
[0062] According to the solution of the present invention, the present invention realizes the customization of matrix order and data bit width through parameterized design, which is convenient for future modification work; saves FPGA hardware resources through time-sharing multiplexing of RAM and multiplication, addition and division IP cores; and reduces the operation time by streamlining the operation state through element address indexing.
[0063] Furthermore, to achieve the above-mentioned purpose, the present invention also provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the FPGA-based Cholesky matrix decomposition inversion method as described above is implemented.
[0064] Furthermore, to achieve the above-mentioned purpose, the present invention also provides a computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the FPGA-based Cholesky matrix decomposition inversion method as described in any one of claims 1-4 is implemented.
[0065] Furthermore, based on the above solution, the technical solution of the present invention is described in detail in the following in combination with the accompanying drawings in the form of a specific embodiment.
[0066] Example 1
[0067] like Figure 1 As shown, the FPGA-based Cholesky matrix decomposition inversion method includes:
[0068] The first state machine is used to index the corresponding elements that need to be multiplied or divided at this time according to the address order of the elements of the matrices L and C and perform Cholesky decomposition. After the calculation is completed, the results are stored in the RAM of the corresponding matrices L and C and switched to the second state machine;
[0069] The second state machine is used to find the inverse matrix of the lower triangular matrix. After repeating the above steps and calculating and storing all the element data of the Y matrix, it switches to the third state machine.
[0070] The third state machine is used to calculate and store the inverse matrix W of the original matrix A, and finally output the matrix W.
[0071] Furthermore, the state transition diagram of the first state machine is as follows: Figure 2 As shown, the operations completed in each state are as follows:
[0072] State 0: Idle state, waiting for data input.
[0073] State 1: According to the currently calculated element index value (i, j) (i, j = 0, 1, ... 7), the i-th row is taken out from the RAM of the storage matrix C, and the j-th row is taken out from the RAM of the storage matrix L. The taken out data and the current state are sent to the basic multiplication and addition operation module.
[0074] State 2: Waiting for the basic multiplication and addition module to output the operation result. Calculate c i j And store the result in RAM.
[0075] State 3: According to the currently calculated element index value (i, j) (i, j = 0, 1, ... 7), c i j With c jj Sent to the basic division operation module.
[0076] State 4: Waiting for the basic division operation to output the operation result. ij And store the result in RAM.
[0077] State 5: Refresh the index value of the next round of calculation elements according to the element calculation order. The element refresh order is as follows Figure 3 shown.
[0078] Furthermore, the state transition diagram of the second state machine is as follows: Figure 4 As shown, the operations completed in each state are as follows:
[0079] State 0: Idle state, waiting for data input.
[0080] State 1: According to the currently calculated element index value (i, j) (i, j = 0, 1, ... 7), fetch the i-th row from the RAM of the storage matrix C and fetch the j-th column from the RAM of the storage matrix Y. Send the fetched data and the current state to the basic multiplication and addition operation module.
[0081] State 2: Waiting for the basic multiplication and addition operation module to output the operation result.
[0082] State 3: According to the currently calculated element index value (i, j) (i, j = 0, 1, ... 7), the multiplication and addition operation result c is ii Sent to the basic division operation module.
[0083] State 4: Waiting for the basic division operation to output the result. Calculate y i j And store the result in RAM.
[0084] State 5: Refresh the index value of the next round of calculation elements according to the element calculation order. The element refresh order is as follows Figure 5 shown.
[0085] Furthermore, the state transition diagram of the third state machine is as follows Figure 6 As shown, the operations completed in each state are as follows:
[0086] State 0: Idle state, waiting for data input.
[0087] State 1: According to the currently calculated element index value (i, j) (i, j = 0, 1, ... 7), the i-th column is taken out from the RAM of the storage matrix L, and the j-th column is taken out from the RAM of the storage matrix W. The taken out data and the current state are sent to the basic multiplication and addition operation module.
[0088] State 2: Waiting for the basic multiplication and addition module to output the operation result. Calculate w i j And store the result in RAM.
[0089] State 3: Refresh the index value of the next round of element calculation according to the element calculation order. The element refresh order is as follows Figure 7 shown.
[0090] In this embodiment, when the covariance matrix is input, the timing simulation is run as follows: Figure 8 and Fig. 9 As shown,
[0091] I_A_*: Input covariance matrix data bus, where I_A_valid is the input covariance matrix data valid signal; signal group I_A_row is the input matrix data.
[0092] O_W_*: Output covariance matrix inverse matrix data bus, where O_W_valid is the output inverse matrix data valid signal; signal group O_W_row is the output matrix data.
[0093] R_stepx_addr: Matrix element index of the state machine x (x=1,2,3) running process. R_step1_addr_i is the combination value of the high 4 bits, corresponding to the row index value of the matrix; R_step1_addr_j is the combination value of the low 4 bits, corresponding to the column index value of the matrix.
[0094] R_work_mode_x: Enable the operation process of state machine x (x=1,2,3). Provide the current working state judgment for the multiplication and addition module and the division module.
[0095] From the simulation results, it can be concluded that state machine 1 (the first state machine) solves the elements of matrix C and matrix L by column cross; state machine 2 (the second state machine) solves the elements of matrix Y in order parallel to the diagonal starting from the diagonal; state machine 3 (the third state machine) solves the elements of matrix W from bottom to top. State machine 1 takes 19.157us (4708 clock cycles), state machine 2 takes 15.963us (3923 clock cycles), and state machine 3 takes 3.780us (929 clock cycles).
[0096] The theoretical value of the inverse matrix of the covariance matrix calculated using the inv() function in Matlab is Q_R_B_inv. Fig.10 The results of FPGA simulation calculation are shown in Fig.11 shown.
[0097] By comparing the theoretical value with the simulation value, it can be concluded that the FPGA algorithm implementation results are basically consistent with the Matlab calculation results. During the simulation process, the FPGA simulation calculation results are written into a text file, and the deviation of the simulation value relative to the theoretical value is read and analyzed in Matlab. The results meet the design requirements.
[0098] Those skilled in the art will appreciate that the modules and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.
[0099] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and equipment can refer to the corresponding processes in the aforementioned method implementation methods, and will not be repeated here.
[0100] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.
[0101] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.
[0102] In addition, each functional module in the embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
[0103] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the energy-saving signal sending / receiving method of each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical disks.
[0104] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.
[0105] It should be understood that the size of the serial numbers of each step in the content of the invention and the implementation methods of the present invention does not absolutely mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of the present invention.
Claims
1. The Cholesky matrix decomposition inversion method based on FPGA is characterized by: include: The matrix decomposition and inversion process is divided into three state machines, which respectively perform LC matrix decomposition, find the inverse matrix Y of matrix C, and find the inverse matrix W of covariance matrix A; The first state machine performs Cholesky decomposition on the input covariance matrix A according to the address order of the elements in the matrix L and the matrix C, and obtains the lower triangular matrix C and the lower triangular matrix L. After the calculation is completed, the result is stored in the RAM corresponding to the matrix L and the matrix C, and the LC matrix decomposition is completed; After completing the LC matrix decomposition, switch to the second state machine, which performs inverse calculation on matrix C according to the address order of the elements in matrix C and matrix Y, and stores the calculation results in matrix Y. After calculating and storing all the element data of matrix Y, the inverse matrix Y of matrix C is completed; After completing the calculation of the inverse matrix Y of matrix C, switch to the third state machine. The third state machine performs inverse calculation on matrix L according to the address order of the elements in matrix L and matrix W, stores the calculation results in matrix W, calculates and stores the inverse matrix W element data of all covariance matrices A, and finally outputs matrix W.
2. The FPGA-based Cholesky matrix decomposition inversion method according to claim 1, characterized in that: The first state machine performs Cholesky decomposition on the input covariance matrix A to obtain the lower triangular matrix C and the lower triangular matrix L. The specific formula is: Among them, the covariance matrix A = R Y , after Cholesky decomposition R Y =LDL H =CL H .
3. The FPGA-based Cholesky matrix decomposition inversion method according to claim 2, characterized in that: The second state machine completes the calculation of the inverse matrix Y of the matrix C according to the following calculation formula:
4. The FPGA-based Cholesky matrix decomposition inversion method according to claim 3, characterized in that: From AW = CL H W=E=CY, we can get L H W=Y, the third state machine calculates the covariance matrix R Y The inverse matrix The specific formula is:
5. FPGA-based Cholesky matrix decomposition inversion system, characterized by: include: The state machine division module divides the matrix decomposition and inversion process into three state machines. The three state machines respectively perform LC matrix decomposition, find the inverse matrix Y of matrix C, and find the inverse matrix W of matrix A; LC matrix decomposition module, the first state machine performs Cholesky decomposition on the input covariance matrix A according to the address order of the elements in the matrix L and the matrix C, and obtains the lower triangular matrix C and the triangular matrix L. After the calculation is completed, the result is stored in the RAM corresponding to the matrix L and the matrix C to complete the LC matrix decomposition; The inverse matrix Y solving module switches to the second state machine after completing the LC matrix decomposition. The second state machine performs inverse calculation on the matrix C according to the address sequence of the elements in the matrix C and the matrix Y, and stores the calculation results in the matrix Y. After calculating and storing all the element data of the matrix Y, the inverse matrix Y of the matrix C is completed. The inverse matrix W solving module, after completing the inverse matrix Y of matrix C, switches to the third state machine. The third state machine performs inverse calculation on matrix L according to the address order of the elements in matrix L and matrix W, stores the calculation results in matrix W, calculates and stores the inverse matrix W element data of all covariance matrices A, and finally outputs matrix W.
6. An electronic device, characterized in that The invention comprises a processor, a memory and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the FPGA-based Cholesky matrix decomposition inversion method as described in any one of claims 1 to 4 is implemented.
7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the FPGA-based Cholesky matrix decomposition inversion method according to any one of claims 1 to 4 is implemented.