Chip macro-cell layout compactness assessment method and system, electronic equipment and storage medium
By calculating the available area in four directions of each module in the chip macro unit layout and accumulating the evaluation value, the problem of difficulty in accurately evaluating the layout compactness in the prior art is solved, and a more reasonable macro unit placement and better layout are achieved. Improves the quality and efficiency of chip design.
Patent Information
- Application Number
- CN202411607496.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-02-18
AI Technical Summary
The prior art is difficult to accurately evaluate the overall compactness of the chip macrocell layout, resulting in difficult to directly reflect the layout density and space utilization.
By calculating the available area in four directions of each module, selecting the smallest available area as the evaluation value of the module, and accumulating the evaluation values of each module to obtain the layout compactness index value.
It provides a more comprehensive and accurate quantitative indicator to help engineers better understand the compactness and regularity of the current layout, reduce layout area waste, achieve better layout, and improve the quality and efficiency of chip design.
Smart Images
Figure CN119476177A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit layout planning, and in particular to a method, system, electronic device and storage medium for evaluating the compactness of a chip macro unit layout. Background Art
[0002] Layout planning is essentially a non-deterministic problem of polynomial complexity. One of the goals of layout planning is to obtain a layout solution with high area utilization. At this stage, macro cells will be compactly placed around the chip layout area, and a large amount of blank area in the middle will be left for standard cell layout to optimize the timing and routing congestion of subsequent standard cell layout. The layout density and space utilization of macro cells and standard cells in the chip layout area are called layout compactness. During the placement of macro cells, some blank areas that cannot be effectively utilized in subsequent layouts may be generated, also known as dead space. The existence of dead space will reduce layout compactness. In order to achieve high-quality layout and reduce unnecessary area waste, it is necessary to quickly and accurately evaluate layout compactness.
[0003] The layout compactness evaluation method in the prior art usually adopts the dead zone analysis method, which indirectly measures the layout compactness by identifying and quantifying the area of the unused area in the layout. Generally, if the proportion of the dead zone area to the total layout area is higher, the layout compactness is considered to be lower. Another method is to calculate the layout fill rate index, which measures the layout compactness by calculating the ratio of the area occupied by all modules in the layout to the total chip area. The higher the ratio, the higher the layout compactness.
[0004] However, the above two methods are both one-sided in reflecting the compactness of the layout, and it is difficult to directly and accurately reflect the compactness of the overall layout of the chip macro unit. Based on this, a new technical solution is needed. Summary of the invention
[0005] The present invention provides a method, system, electronic device and storage medium for evaluating the compactness of a chip macro unit layout. The compactness of an existing layout is measured by calculating indicators related to the available area, providing a more comprehensive and accurate quantitative indicator for evaluating the compactness, thereby ensuring the reliability of the evaluation result.
[0006] The first object of the present invention is to provide a method for evaluating the compactness of a chip macro unit layout, which specifically comprises the following steps:
[0007] Acquire a layout area where the macro units are placed; the layout area includes a plurality of modules;
[0008] Traversing each module in turn, and obtaining an evaluation value of the module by calculating the available area of the module;
[0009] The evaluation values of all the modules are accumulated to obtain a layout compactness index value.
[0010] Furthermore, obtaining the evaluation value of the module by calculating the available area of the module specifically includes:
[0011] Calculate the available areas of the module in four directions respectively; the four directions specifically include the lower left corner direction, the lower right corner direction, the upper right corner direction and the upper left corner direction;
[0012] The available areas in the four directions are compared, and the smallest available area is selected as the evaluation value of the module.
[0013] Further, the calculating the available areas of the module in four directions respectively specifically includes:
[0014] Taking the lower left corner as the vertex, respectively extending the left side and the lower side of the module to intersect with the layout area to obtain the area of the lower left corner;
[0015] The difference between the area of the lower left corner and the area of the module is the available area of the lower left corner.
[0016] Furthermore, the calculating the available areas of the modules in four directions respectively also includes:
[0017] Taking the lower right corner as the vertex, respectively extending the right side and the lower side of the module to intersect with the layout area to obtain the area of the lower right corner;
[0018] The difference between the area of the lower right corner and the area of the module is the available area of the lower right corner;
[0019] Taking the upper right corner as the vertex, respectively extending the right side and the upper side of the module to intersect with the layout area to obtain the area of the upper right corner;
[0020] The difference between the upper right corner area and the module area is the upper right corner available area;
[0021] Taking the upper left corner as the vertex, respectively extending the left side and the upper side of the module to intersect with the layout area to obtain the area of the upper left corner;
[0022] The difference between the upper left corner area and the module area is the upper left corner available area.
[0023] A second object of the present invention is to provide a chip macro unit layout compactness evaluation system, comprising a layout area acquisition unit, an evaluation value calculation unit and a compactness index value acquisition unit;
[0024] The layout area acquisition unit is used to determine the range of evaluating compactness, specifically including:
[0025] Acquire a layout area where the macro units are placed; the layout area includes a plurality of modules;
[0026] The evaluation value calculation unit is used to calculate the evaluation value of a single module, specifically including:
[0027] Traversing each module in turn, and obtaining an evaluation value of the module according to the available area of the module;
[0028] The compactness index value acquisition unit is used to accumulate and obtain a final layout compactness index value, specifically including:
[0029] The evaluation values of all the modules are accumulated to obtain a layout compactness index value.
[0030] Furthermore, the evaluation value calculation unit also includes:
[0031] Calculate the available areas of the module in four directions respectively; the four directions specifically include the lower left corner direction, the lower right corner direction, the upper right corner direction and the upper left corner direction;
[0032] The available areas in the four directions are compared, and the smallest available area is selected as the evaluation value of the module.
[0033] Furthermore, the evaluation value calculation unit also includes:
[0034] Taking the lower left corner as the vertex, respectively extending the left side and the lower side of the module to intersect with the layout area to obtain the area of the lower left corner;
[0035] The difference between the area of the lower left corner and the area of the module is the available area of the lower left corner;
[0036] Taking the lower right corner as the vertex, respectively extending the right side and the lower side of the module to intersect with the layout area to obtain the area of the lower right corner;
[0037] The difference between the area of the lower right corner and the area of the module is the available area of the lower right corner;
[0038] Taking the upper right corner as the vertex, respectively extending the right side and the upper side of the module to intersect with the layout area to obtain the area of the upper right corner;
[0039] The difference between the upper right corner area and the module area is the upper right corner available area;
[0040] Taking the upper left corner as the vertex, respectively extending the left side and the upper side of the module to intersect with the layout area to obtain the area of the upper left corner;
[0041] The difference between the upper left corner area and the module area is the upper left corner available area.
[0042] The third object of the present invention is to provide an electronic device, comprising: a memory on which a program code is stored; a processor, which is connected to the memory and when the program code is executed by the processor, implements the chip macro unit layout compactness evaluation method described in any embodiment of the present invention.
[0043] A fourth object of the present invention is to provide a computer-readable storage medium having program instructions stored thereon, wherein the program instructions, when executed, implement the method for evaluating the compactness of the chip macro unit layout described in any embodiment.
[0044] Compared with the prior art, the present invention has the following beneficial effects:
[0045] (1) For a given layout area, the present invention accumulates the evaluation values of the compactness of each module around it as the index value of the final overall layout compactness. This method comprehensively considers the layout efficiency of each module, provides a more comprehensive and accurate quantitative index for evaluating compactness, and ensures the reliability of the evaluation results.
[0046] (2) This method quantitatively evaluates the compactness of the overall layout by summarizing and analyzing the available area in four directions of each module, helping engineers to better understand the compactness and regularity of the current layout, and based on this, make more reasonable macro unit placement, reduce layout area waste, achieve a better layout, and improve the quality and efficiency of chip design. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0048] Figure 1 This is a flow chart of a method for evaluating the compactness of a chip macro unit layout provided in the first embodiment of the present invention;
[0049] Figure 2 This is a flow chart of a method for obtaining an evaluation value in a method for evaluating the compactness of a chip macro unit layout provided in the first embodiment of the present invention;
[0050] Figure 3 This is a schematic diagram of the layout area and initial module sizes and placement positions of a chip macro unit layout compactness provided in the first embodiment of the present invention;
[0051] Figure 4 It is a schematic diagram of calculating the evaluation value of a single module in a method for evaluating the compactness of a chip macro unit layout provided in the first embodiment of the present invention;
[0052] Figure 5 It is a structural schematic diagram of a chip macro unit layout compactness evaluation system provided by the second embodiment of the present invention;
[0053] Figure 6 is a schematic diagram of an electronic device provided by a fourth embodiment of the present invention;
[0054] Figure 7 It is a schematic diagram of a storage medium provided in Embodiment 5 of the present invention. DETAILED DESCRIPTION
[0055] The embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0056] The following describes the implementation methods of the present application through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.
[0057] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.
[0058] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0059] Embodiment 1
[0060] Figure 1This is a flow chart of a method for evaluating the compactness of a chip macro cell layout provided in a first embodiment of the present invention. The embodiment of the present invention is suitable for evaluating the compactness of a macro cell layout in a chip layout area after macro cells are placed in the layout area.
[0061] like Figure 1 , a method for evaluating the compactness of chip macro cell layout, specifically comprising the following steps:
[0062] S101: Acquire a layout area where macro units are placed; the layout area includes a number of modules;
[0063] In the embodiments of the present application, Figure 3 As shown, the layout area 1 is set to be a rectangle; the layout area 1 may also be other shapes.
[0064] Module refers to the modules arranged in the chip layout plan. It can be understood as a chip logic unit, and each module has separate functional attributes. A chip can include multiple modules. Figure 3 As shown, there are several modules 2 in the layout area 1. The modules 2 are compactly placed around the layout area, leaving a large amount of blank area in the middle for the layout of standard cells, so as to optimize the timing and layout congestion of the subsequent standard cell layout.
[0065] S102: traverse each module in turn, and obtain the evaluation value of the module by calculating the available area of the module;
[0066] It should be noted that the evaluation value of the module obtained by calculating the available area of the module specifically includes:
[0067] S1021: Calculate the available areas of the module in four directions respectively; the four directions specifically include the lower left corner direction, the lower right corner direction, the upper right corner direction and the upper left corner direction;
[0068] It should be noted that the calculation of the available area of the module in four directions specifically includes:
[0069] Taking the lower left corner as the vertex, extend the left and bottom sides of the module and intersect them in the layout area to obtain the lower left corner area;
[0070] The difference between the area of the lower left corner and the module area is the available area of the lower left corner.
[0071] Taking the lower right corner as the vertex, extend the right side and the bottom side of the module to intersect with the layout area to obtain the lower right corner area;
[0072] The difference between the area of the lower right corner and the module area is the available area of the lower right corner;
[0073] Taking the upper right corner as the vertex, extend the right side and the top side of the module to intersect with the layout area to obtain the upper right corner area;
[0074] The difference between the area of the upper right corner and the module area is the available area of the upper right corner;
[0075] Taking the upper left corner as the vertex, extend the left and top sides of the module and intersect them in the layout area to obtain the upper left corner area;
[0076] The difference between the area of the upper left corner and the module area is the available area of the upper left corner.
[0077] In this embodiment, it is assumed that the current traversal reaches the i-th module, such as Figure 4 , module A is the i-th module currently traversed. With the lower left corner of the layout area as the origin O, a plane rectangular coordinate system 0-xy is established, and the coordinates of the lower left corner of the module are recorded as (x i1 ,y i1 ), the coordinates of the lower right corner, upper right corner and upper left corner of the module are (x i2 ,y i1 )、(x i2 ,y i2 )、(x i1 ,y i2 ).
[0078] Calculate the available areas in the lower left, lower right, upper right, and upper left directions in turn:
[0079] like Figure 4 , take the lower left corner Q of module A as the vertex, extend the left side of the module to intersect the layout area at point M, extend the bottom side of the module to intersect the layout area at point N, and the rectangle QNGM is the required lower left corner area.
[0080] Let the lower left corner area QNGM be The area of the lower left corner is for:
[0081]
[0082] in, and Represents the width and height of the lower left corner area. The specific calculation formula is as follows:
[0083]
[0084] in, is the horizontal coordinate of point G in the upper right corner of the layout area, The vertical coordinate of the upper right corner point G of the layout area.
[0085] Calculate the difference between the area of the lower left corner and the module area, which is the available area of the lower left corner. for:
[0086]
[0087] Among them, S macro is the total area of the modules contained in this region.
[0088] Similarly, the available areas in the lower right, upper right, and upper left directions can be obtained in turn and recorded as
[0089]
[0090] S1022: Compare the available areas in the four directions, and select the smallest available area as the evaluation value of the module.
[0091] Specifically, the module evaluation value S i for:
[0092]
[0093] The present invention quantifies the evaluation value of each module by individually evaluating the available area in four directions of each module, thereby obtaining a more comprehensive and accurate evaluation value and ensuring the reliability of the evaluation result.
[0094] S103: Accumulate the evaluation values of all the modules to obtain a layout compactness index value.
[0095] Specifically, the layout compactness index value S is:
[0096]
[0097] Where n is the number of modules in the layout area.
[0098] The present embodiment provides a method for evaluating the compactness of a chip macro-unit layout, which provides a more comprehensive and accurate quantitative index for evaluating the compactness by accumulating the evaluation values of the compactness around each module as the index value of the final overall layout compactness, and comprehensively considers the layout efficiency of each module to ensure the reliability of the evaluation result; the present invention quantitatively evaluates the compactness of the overall layout by summarizing and analyzing the available area in four directions of each module, helping engineers to better understand the compactness and regularity of the current layout, and accordingly perform more reasonable macro-unit placement, reduce layout area waste, achieve a better layout, and improve the quality and efficiency of chip design.
[0099] Embodiment 2
[0100] A chip macro cell layout compactness evaluation system 200 includes a layout area acquisition unit 201, an evaluation value calculation unit 202, and a compactness index value acquisition unit 203;
[0101] The layout area acquisition unit 201 is used to determine the range of compactness evaluation, specifically including:
[0102] Obtaining a layout area where the macro units are placed; the layout area includes several modules;
[0103] The evaluation value calculation unit 202 is used to calculate the evaluation value of a single module, specifically including:
[0104] Traversing each module in turn, and obtaining an evaluation value of the module by calculating the available area of the module;
[0105] It should be noted that the evaluation value of the module obtained by calculating the available area of the module specifically includes:
[0106] Calculate the available areas of the module in four directions respectively; the four directions specifically include the lower left corner direction, the lower right corner direction, the upper right corner direction and the upper left corner direction;
[0107] Taking the lower left corner as the vertex, extend the left and bottom sides of the module and intersect them in the layout area to obtain the area of the lower left corner;
[0108] The difference between the area of the lower left corner and the area of the module is the available area of the lower left corner;
[0109] Taking the lower right corner as the vertex, extend the right side and the bottom side of the module and intersect them in the layout area to obtain the area of the lower right corner;
[0110] The difference between the area of the lower right corner and the module area is the available area of the lower right corner;
[0111] Take the upper right corner as the vertex, extend the right side and the top side of the module and intersect them in the layout area to obtain the area of the upper right corner;
[0112] The difference between the upper right corner area and the module area is the upper right corner available area;
[0113] Take the upper left corner as the vertex, extend the left and top sides of the module and intersect them in the layout area to obtain the area of the upper left corner;
[0114] The difference between the upper left corner area and the module area is the upper left corner available area.
[0115] The available areas in the four directions are compared, and the smallest available area is selected as the evaluation value of the module.
[0116] The compactness index value acquisition unit 203 is used to accumulate and obtain the final layout compactness index value, which specifically includes:
[0117] The evaluation values of all modules are accumulated to obtain the layout compactness index value.
[0118] The present embodiment provides a chip macro unit layout compactness evaluation system 200, which provides a more comprehensive and accurate quantitative index for evaluating compactness by accumulating the evaluation values of the compactness around each module as the index value of the final overall layout compactness, and comprehensively considers the layout efficiency of each module to ensure the reliability of the evaluation result; the present invention quantitatively evaluates the compactness of the overall layout by summarizing and analyzing the available area in four directions of each module, helping engineers to better understand the compactness and regularity of the current layout, and accordingly perform more reasonable macro unit placement, reduce layout area waste, achieve better layout, and improve the quality and efficiency of chip design.
[0119] Embodiment 3
[0120] An electronic device 300, such as Figure 6 As shown, it includes: a memory 301 on which program codes are stored; a processor 302, which is connected to the memory, and when the program codes are executed by the processor, a method for evaluating the compactness of the chip macro unit layout is implemented. For a detailed description of the method, reference can be made to the corresponding description in the above method embodiment, which will not be repeated here.
[0121] Embodiment 4
[0122] A computer readable storage medium 400, such as Figure 7 As shown, a program instruction 401 is stored thereon, and when the program instruction is executed, a method for evaluating the compactness of a chip macrocell layout is implemented. For a detailed description of the method, reference may be made to the corresponding description in the above method embodiment, and no further description is given here.
[0123] The number of devices and processing scales described here are used to simplify the description of the present invention. Applications, modifications and variations of the present invention will be obvious to those skilled in the art.
[0124] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and implementation modes. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.
[0125] The apparatus, electronic device, non-volatile computer storage medium and method provided in the embodiments of this specification correspond to each other, and therefore, the apparatus, electronic device and non-volatile computer storage medium also have similar beneficial technical effects as the corresponding method. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the corresponding apparatus, electronic device and non-volatile computer storage medium will not be repeated here.
[0126] Those skilled in the art also know that, in addition to implementing the controller in a purely computer-readable program code, the controller can be made to implement the same function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, such a controller can be considered as a hardware component, and the devices for implementing various functions included therein can also be considered as structures within the hardware component. Or even, the devices for implementing various functions can be considered as both software units for implementing the method and structures within the hardware component.
[0127] The systems, devices or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. For the convenience of description, the above devices are described separately by functions in various units. Of course, when implementing one or more embodiments of this specification, the functions of each unit can be implemented in the same or more software and / or hardware.
[0128] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification may be in the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the embodiments of this specification may be in the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.
[0129] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0130] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0131] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0132] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.
[0133] The specification may be described in the general context of computer-executable instructions executed by a computer, such as program units. Generally, program units include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communications network. In a distributed computing environment, program units may be located in local and remote computer storage media, including storage devices.
[0134] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0135] The above description is only an embodiment of this specification and is not intended to limit one or more embodiments of this specification. For those skilled in the art, one or more embodiments of this specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included in the scope of the claims of one or more embodiments of this specification.
Claims
1. A method for evaluating the compactness of chip macro cell layout, characterized in that: The specific steps include: Acquire a layout area where the macro units are placed; the layout area includes a plurality of modules; Traversing each module in turn, and obtaining an evaluation value of the module by calculating the available area of the module; The evaluation values of all the modules are accumulated to obtain a layout compactness index value.
2. The chip macro cell layout compactness evaluation method according to claim 1, characterized in that: The step of obtaining the evaluation value of the module by calculating the available area of the module specifically includes: Calculate the available areas of the module in four directions respectively; the four directions specifically include the lower left corner direction, the lower right corner direction, the upper right corner direction and the upper left corner direction; The available areas in the four directions are compared, and the smallest available area is selected as the evaluation value of the module.
3. The chip macro unit layout compactness evaluation method according to claim 2, characterized in that: The calculating the available areas of the modules in four directions respectively specifically includes: Taking the lower left corner as the vertex, respectively extending the left side and the lower side of the module to intersect with the layout area to obtain the area of the lower left corner; The difference between the area of the lower left corner and the area of the module is the available area of the lower left corner.
4. The chip macro unit layout compactness evaluation method according to claim 3, characterized in that: The calculating the available areas of the modules in four directions respectively also includes: Taking the lower right corner as the vertex, respectively extending the right side and the lower side of the module to intersect with the layout area to obtain the area of the lower right corner; The difference between the area of the lower right corner and the area of the module is the available area of the lower right corner; Taking the upper right corner as the vertex, respectively extending the right side and the upper side of the module to intersect with the layout area to obtain the area of the upper right corner; The difference between the upper right corner area and the module area is the upper right corner available area; Taking the upper left corner as the vertex, respectively extending the left side and the upper side of the module to intersect with the layout area to obtain the area of the upper left corner; The difference between the upper left corner area and the module area is the upper left corner available area.
5. A chip macro cell layout compactness evaluation system, characterized in that: It includes a layout area acquisition unit, an evaluation value calculation unit and a compactness index value acquisition unit; The layout area acquisition unit is used to determine the range of evaluating compactness, specifically including: Acquire a layout area where the macro units are placed; the layout area includes a plurality of modules; The evaluation value calculation unit is used to calculate the evaluation value of a single module, specifically including: Traversing each module in turn, and obtaining an evaluation value of the module according to the available area of the module; The compactness index value acquisition unit is used to accumulate and obtain a final layout compactness index value, specifically including: The evaluation values of all the modules are accumulated to obtain a layout compactness index value.
6. The chip macro cell layout compactness evaluation system according to claim 5, characterized in that: The evaluation value calculation unit also includes: Calculate the available areas of the module in four directions respectively; the four directions specifically include the lower left corner direction, the lower right corner direction, the upper right corner direction and the upper left corner direction; The available areas in the four directions are compared, and the smallest available area is selected as the evaluation value of the module.
7. The chip macro unit layout compactness evaluation system according to claim 6, characterized in that: The evaluation value calculation unit also includes: Taking the lower left corner as the vertex, respectively extending the left side and the lower side of the module to intersect with the layout area to obtain the area of the lower left corner; The difference between the area of the lower left corner and the area of the module is the available area of the lower left corner; Taking the lower right corner as the vertex, respectively extending the right side and the lower side of the module to intersect with the layout area to obtain the area of the lower right corner; The difference between the area of the lower right corner and the area of the module is the available area of the lower right corner; Taking the upper right corner as the vertex, respectively extending the right side and the upper side of the module to intersect with the layout area to obtain the area of the upper right corner; The difference between the upper right corner area and the module area is the upper right corner available area; Taking the upper left corner as the vertex, respectively extending the left side and the upper side of the module to intersect with the layout area to obtain the area of the upper left corner; The difference between the upper left corner area and the module area is the upper left corner available area.
8. An electronic device, characterized in that: include: A memory having program code stored therein; A processor is connected to the memory, and when the program code is executed by the processor, the method according to any one of claims 1 to 7 is implemented.
9. A computer-readable storage medium, characterized in that: Program instructions are stored thereon, and when the program instructions are executed, the method according to any one of claims 1 to 7 is implemented.