Sensitive amplifier and control method thereof, ferroelectric memory and electronic equipment

Abstract

The invention discloses a sensitive amplifier and a control method thereof, a ferroelectric memory and electronic equipment. The sensitive amplifier comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a first capacitor, a first switch tube, a second capacitor and a second switch tube. According to the sensitive amplifier, the capacitive load which can be flexibly accessed is added, wrong reading caused by imbalance is reduced, and the reliability of a ferroelectric memory and the integrity of data are improved. Moreover, the sensitive amplifier is simple in circuit, low in cost, capable of adapting to sensitive amplifier imbalance changes caused by process changes, temperature changes and other environmental factors, and better in practicability. The invention can be widely applied to the technical field of electronic devices.

Description

Technical Field

[0001] The present application relates to the technical field of electronic devices, and in particular to a sensitive amplifier and a control method thereof, a ferroelectric memory, and an electronic device. Background Art

[0002] With the development of electronic technology, related devices have been gradually applied and promoted. Among them, ferroelectric memory is a non-volatile memory device that can continue to save data after power failure and has a fast access speed. It is widely used in fields such as smart cards, medical equipment, and automotive electronic systems. When the ferroelectric memory works under the positive voltage pulse of the plate line (PL), the voltage generated on its bit line is a small value, which cannot correctly express the logic "1" or "0" and cannot be directly output to the external port as a valid data signal. Therefore, a sensitive amplifier is required to amplify the tiny voltage difference generated when it is read to achieve full swing, so that it can correctly identify the valid logic value "1" or "0". Therefore, the sensitive amplifier is an indispensable part of the design of ferroelectric memory.

[0003] In the related art, the parameters of the transistors of the sense amplifier are matched, so as long as there is a slight voltage difference on the two bit lines (Bit Line, BL) of the ferroelectric memory, it will be correctly amplified by the sense amplifier. In the case of process fluctuations, the parameters of the transistors cannot be completely matched, and some deviations will occur, so the problem of device mismatch occurs. As the feature size continues to shrink, the mismatch problem between transistors becomes more and more obvious, resulting in an increase in the offset voltage of the sense amplifier, which in turn causes the sense amplifier to fail to work properly. When the input differential voltage is constant, its yield will decrease. When there is an offset voltage, if you want to correctly amplify the signal of the storage unit, you must increase the voltage difference on the bit line. If you want to get a larger differential voltage, you need to increase the bit line charging time, which will increase power consumption and worsen the delay. If the offset voltage value is reduced by adjusting the transistor size to increase it, the area of ​​the zero-sensitive amplifier will also increase accordingly, the cost is high and the practicality is not good.

[0004] In summary, the problems existing in related technologies need to be solved urgently. Summary of the invention

[0005] The purpose of this application is to solve one of the technical problems existing in the related art to at least a certain extent.

[0006] To this end, an object of the embodiments of the present application is to provide a sensitive amplifier and a control method thereof, a ferroelectric memory, and an electronic device.

[0007] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present application include:

[0008] On the one hand, an embodiment of the present application provides a sensitive amplifier, comprising:

[0009] A first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a first capacitor, a first switch tube, a second capacitor and a second switch tube;

[0010] The gate of the first MOS tube, the gate of the third MOS tube, the drain of the second MOS tube, and the drain of the fourth MOS tube are used to connect to the second bit line of the ferroelectric memory, the gate of the second MOS tube, the gate of the fourth MOS tube, the drain of the first MOS tube, and the drain of the third MOS tube are used to connect to the first bit line of the ferroelectric memory, the source of the first MOS tube and the source of the second MOS tube are connected to the drain of the fifth MOS tube, the gate of the fifth MOS tube is connected to the first signal port, the source of the fifth MOS tube is connected to the power supply, the source of the third MOS tube and the source of the fourth MOS tube are connected to the drain of the sixth MOS tube, the gate of the sixth MOS tube is connected to the second signal port, and the source of the sixth MOS tube is grounded;

[0011] The first end of the first capacitor is used to connect to the first bit line, and the second end of the first capacitor is grounded through the first switch tube; the first end of the second capacitor is used to connect to the second bit line, and the second end of the second capacitor is grounded through the second switch tube;

[0012] Among them, the first MOS tube, the second MOS tube, and the fifth MOS tube are NMOS tubes, and the third MOS tube, the fourth MOS tube, and the sixth MOS tube are PMOS tubes.

[0013] In addition, the sense amplifier according to the above embodiment of the present application may also have the following additional technical features:

[0014] Further, in one embodiment of the present application, the sense amplifier further includes a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a tenth MOS tube;

[0015] The gate of the seventh MOS tube and the gate of the eighth MOS tube are connected to the third signal port, the source of the seventh MOS tube and the source of the eighth MOS tube are connected to the power supply, the drain of the seventh MOS tube is used to connect to the first bit line, and the drain of the eighth MOS tube is used to connect to the second bit line;

[0016] The gate of the ninth MOS tube and the gate of the tenth MOS tube are connected to the fourth signal port, the source of the ninth MOS tube and the source of the tenth MOS tube are grounded, the drain of the ninth MOS tube is used to connect to the first bit line, and the drain of the tenth MOS tube is used to connect to the second bit line;

[0017] Wherein, the seventh MOS tube and the eighth MOS tube are NMOS tubes, and the ninth MOS tube and the tenth MOS tube are PMOS tubes.

[0018] Further, in one embodiment of the present application, the sense amplifier further includes at least one group of first auxiliary capacitor units;

[0019] The first auxiliary capacitor unit includes a third capacitor and a third switch tube;

[0020] The first end of the third capacitor is used to connect to the first bit line, and the second end of the third capacitor is grounded through the third switch tube.

[0021] Further, in one embodiment of the present application, the sense amplifier further includes at least one group of second auxiliary capacitor units;

[0022] The second auxiliary capacitor unit includes a fourth capacitor and a fourth switch tube;

[0023] The first end of the fourth capacitor is used to connect to the second bit line, and the second end of the fourth capacitor is grounded through the fourth switch tube.

[0024] Furthermore, in one embodiment of the present application, the first switch tube includes at least one of a gate turn-off thyristor, a power transistor, a metal oxide semiconductor field effect transistor, and an insulated gate bipolar transistor.

[0025] On the other hand, an embodiment of the present application provides a control method of a sense amplifier, which is used to control the aforementioned sense amplifier. The control method includes:

[0026] Detecting a first voltage offset on the first bit line;

[0027] If the first voltage offset is greater than or equal to a first preset threshold, the first switch tube is controlled to be turned on so that the first capacitor is grounded.

[0028] In some embodiments, the method further comprises:

[0029] If the first voltage offset is greater than or equal to a second preset threshold, determining the target number of enabled first auxiliary capacitor units according to the magnitude of the first voltage offset; wherein the second preset threshold is greater than the first preset threshold;

[0030] The target number of third switch tubes are controlled to be turned on so that the corresponding third capacitors are grounded.

[0031] In some embodiments, the method further comprises:

[0032] Detecting a second voltage offset on the second bit line;

[0033] If the second voltage offset is greater than or equal to a first preset threshold, the second switch tube is controlled to be turned on so that the second capacitor is grounded.

[0034] On the other hand, an embodiment of the present application provides a ferroelectric memory, comprising the aforementioned sensitive amplifier.

[0035] On the other hand, an embodiment of the present application further provides an electronic device, comprising the aforementioned ferroelectric memory.

[0036] The advantages and benefits of the present application will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application:

[0037] The sensitive amplifier and control method thereof, ferroelectric memory, and electronic device disclosed in the embodiments of the present application include a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a first capacitor, a first switch tube, a second capacitor, and a second switch tube; the gate of the first MOS tube, the gate of the third MOS tube, the drain of the second MOS tube, and the drain of the fourth MOS tube are used to connect to the second bit line of the ferroelectric memory, the gate of the second MOS tube, the gate of the fourth MOS tube, the drain of the first MOS tube, and the drain of the third MOS tube are used to connect to the first bit line of the ferroelectric memory, the source of the first MOS tube and the source of the second MOS tube are connected to the drain of the fifth MOS tube, and the drain of the fourth MOS tube is connected to the drain of the fifth MOS tube. The gate of the fifth MOS tube is connected to the first signal port, the source of the fifth MOS tube is connected to the power supply, the source of the third MOS tube and the source of the fourth MOS tube are connected to the drain of the sixth MOS tube, the gate of the sixth MOS tube is connected to the second signal port, and the source of the sixth MOS tube is grounded; the first end of the first capacitor is used to connect the first bit line, the second end of the first capacitor is grounded through the first switch tube, the first end of the second capacitor is used to connect the second bit line, and the second end of the second capacitor is grounded through the second switch tube; wherein the first MOS tube, the second MOS tube, and the fifth MOS tube are NMOS tubes, and the third MOS tube, the fourth MOS tube, and the sixth MOS tube are PMOS tubes. The sensitive amplifier can adjust the voltage offset through the capacitive load to achieve accurate compensation for the offset of the sensitive amplifier, and can improve the accuracy and reliability of the sensitive amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following introduction is made to the drawings of the embodiments of the present application or the related technical solutions in the prior art. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A schematic diagram of the circuit structure of a latch-type sense amplifier in the related art is shown;

[0040] Figure 2 A circuit structure diagram of a sensitive amplifier provided in an embodiment of the present application is shown;

[0041] Figure 3 A circuit structure schematic diagram of another sensitive amplifier provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0042] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. The described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0043] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] In the description of the present application, it should be understood that the terms "length", "up", "down", "front", "back", "left", "right", "top", "inside", "outside", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more.

[0045] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0046] Before introducing the technical solution of the present application, some technical terms involved in the present application are first explained and illustrated as follows.

[0047] 1) Ferroelectric Random Access Memory (FeRAM) is a non-volatile memory device that combines the high speed of static random access memory (SRAM) and the data retention capability of read-only memory (ROM). Unlike traditional RAM, ferroelectric memory can retain its data even after power is turned off.

[0048] With the development of electronic technology, related devices have been gradually applied and promoted. Among them, ferroelectric memory is a non-volatile memory device that can continue to save data after power failure and has a fast access speed. It is widely used in fields such as smart cards, medical equipment, and automotive electronic systems.

[0049] When the ferroelectric memory works under the positive voltage pulse of the plate line (PL), the voltage generated on its bit line is a small value, which cannot correctly express the logic "1" or "0" and cannot be directly output to the external port as a valid data signal. Therefore, a sensitive amplifier is needed to amplify the tiny voltage difference generated when it is read to achieve full swing, so that the valid logic value "1" or "0" can be correctly identified. Therefore, the sensitive amplifier is an indispensable part of the design of ferroelectric memory. The performance of ferroelectric memory is mainly reflected in the fast reading and writing speed and long service life. For a high-performance memory, the reading and writing speed is the key. Since the ferroelectric memory can achieve non-delayed writing, the key to determining the reading and writing speed of the ferroelectric memory is the reading speed. The data reading time of FeRAM refers to the total time consumed from the effective input of the address signal to the effective output of the data. This time is jointly determined by the address buffer delay, the row and column decoder delay, the ferroelectric memory cell delay, the sense amplifier delay and the output buffer delay. If you want to improve the reading speed of FeRAM, you should try to reduce the above delays. Since the structure of the row and column decoder is basically fixed, it is difficult and unprofitable to shorten the delay by changing its circuit structure. Therefore, the most effective way to increase the reading speed of FeRAM is to improve the design of the sense amplifier to improve the signal amplification efficiency. Moreover, the time consumed by the ferroelectric memory cell to form the minimum voltage difference required for the normal operation of the sense amplifier during reading and the time consumed by the sense amplifier to amplify the signal account for a large proportion of the total delay, so the main factor affecting the reading time is the performance of the sense amplifier.

[0050] In the related art, the parameters of the transistors of the sense amplifier are matched, so as long as there is a small voltage difference between the two bit lines (BL) of the ferroelectric memory, it will be correctly amplified by the sense amplifier. Figure 1 , Figure 1The circuit structure diagram of a latch-type sense amplifier in the related art is shown. It is composed of six MOS tubes, the four MOS tubes in the middle are connected to form a pair of interlocked inverters, which have the property of positive feedback and are the main working part of the amplification function; the MOS tubes on both sides are two switch tubes, and the gates are connected to SAEN and SAEP respectively to control the working state of the sense amplifier. In the off state, SAEP is high and SAEN is low. When the step difference information read by the 2T2C unit is generated on the complementary bit line, SAEP is pulled low and SAEN is pulled high at the same time, and the sense amplifier is turned on, and the bit line potential is quickly amplified to logic 0 and 1 through positive feedback. The circuit has the advantages of simple circuit, low power consumption, and high speed.

[0051] However, in the case of process fluctuations, the parameters of the transistors cannot be completely matched, and some deviations will occur, thus causing the problem of device mismatch. As the feature size continues to shrink, the mismatch problem between transistors becomes more and more obvious, causing the offset voltage of the sense amplifier to continue to increase, which in turn causes the sense amplifier to fail to work properly. When the input differential voltage is constant, its yield will decrease. When there is an offset voltage, in order to correctly amplify the signal of the storage cell, the voltage difference on the bit line must be increased. In order to obtain a larger differential voltage, the bit line charging time must be increased, which will lead to increased power consumption and worsening of delay. If the offset voltage value is reduced by adjusting the transistor size to increase it, the area of ​​the zero-sensitivity amplifier will also increase accordingly, the cost is high and the practicality is poor.

[0052] In view of this, an embodiment of the present application provides a sensitive amplifier and a control method thereof, a ferroelectric memory, and an electronic device. The sensitive amplifier includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a first capacitor, a first switch tube, a second capacitor, and a second switch tube; the gate of the first MOS tube, the gate of the third MOS tube, the drain of the second MOS tube, and the drain of the fourth MOS tube are used to connect to the second bit line of the ferroelectric memory, the gate of the second MOS tube, the gate of the fourth MOS tube, the drain of the first MOS tube, and the drain of the third MOS tube are used to connect to the first bit line of the ferroelectric memory, and the source of the first MOS tube and the source of the second MOS tube are connected to the fifth MOS tube. The drain of the S tube, the gate of the fifth MOS tube is connected to the first signal port, the source of the fifth MOS tube is connected to the power supply, the source of the third MOS tube and the source of the fourth MOS tube are connected to the drain of the sixth MOS tube, the gate of the sixth MOS tube is connected to the second signal port, and the source of the sixth MOS tube is grounded; the first end of the first capacitor is used to connect the first bit line, the second end of the first capacitor is grounded through the first switch tube, the first end of the second capacitor is used to connect the second bit line, and the second end of the second capacitor is grounded through the second switch tube; wherein the first MOS tube, the second MOS tube, and the fifth MOS tube are NMOS tubes, and the third MOS tube, the fourth MOS tube, and the sixth MOS tube are PMOS tubes. The sensitive amplifier can adjust the voltage offset through the capacitive load to achieve accurate compensation for the offset of the sensitive amplifier, which can improve the accuracy and reliability of the sensitive amplifier.

[0053] Below, in conjunction with specific drawings, a sensitive amplifier and a control method thereof, a ferroelectric memory, and an electronic device provided in the embodiments of the present application are described in detail.

[0054] The embodiments of the present application provide a sensitive amplifier and a control method thereof, a ferroelectric memory, and an electronic device, which can be applied to the technical field of electronic devices. Figure 2 , a sensitive amplifier provided in an embodiment of the present application mainly includes:

[0055] A first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a first capacitor C1, a first switch tube, a second capacitor C2 and a second switch tube;

[0056] The gate of the first MOS transistor M1, the gate of the third MOS transistor M3, the drain of the second MOS transistor M2, and the drain of the fourth MOS transistor M4 are used to connect to the second bit line BLN of the ferroelectric memory, the gate of the second MOS transistor M2, the gate of the fourth MOS transistor M4, the drain of the first MOS transistor M1, and the drain of the third MOS transistor M3 are used to connect to the first bit line BL of the ferroelectric memory, the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are connected to the drain of the fifth MOS transistor M5, the gate of the fifth MOS transistor M5 is connected to the first signal port, the source of the fifth MOS transistor M5 is connected to the power supply, the source of the third MOS transistor M3 and the source of the fourth MOS transistor M4 are connected to the drain of the sixth MOS transistor M6, the gate of the sixth MOS transistor M6 is connected to the second signal port, and the source of the sixth MOS transistor M6 is grounded;

[0057] The first end of the first capacitor C1 is used to connect the first bit line BL, and the second end of the first capacitor C1 is grounded through the first switch tube; the first end of the second capacitor C2 is used to connect the second bit line BLN, and the second end of the second capacitor C2 is grounded through the second switch tube;

[0058] The first MOS transistor M1 , the second MOS transistor M2 , and the fifth MOS transistor M5 are NMOS transistors, and the third MOS transistor M3 , the fourth MOS transistor M4 , and the sixth MOS transistor M6 are PMOS transistors.

[0059] In an embodiment of the present application, a sensitive amplifier is provided, which improves the traditional sensitive amplifier circuit design and introduces an asymmetric capacitive load on the state definition node, which can reduce the impact of the sensitive amplifier offset and facilitate the adjustment of the internal state of the sensitive amplifier.

[0060] For details, please refer to Figure 2 The sensitive amplifier in the embodiment of the present application still includes six MOS tubes in the main body, namely the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, and the sixth MOS tube M6, wherein the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are connected to form a pair of interlocked inverters, and positive feedback is provided by cross-coupled inverters. In the embodiment of the present application, the first signal port and the second signal port can be used for input signals, and the first bit line BL and the second bit line BLN can be used for output signals.

[0061] At the beginning of the circuit's operating cycle, the first bit line BL and the second bit line BLN of the ferroelectric memory are precharged to ground, and then a read operation is performed. After an appropriate time, in order to obtain a stable state at the node of the first bit line BL, the sense amplifier is enabled and internally interpreted as a logic state "1" or "0". The internal state preference of the sense amplifier depends on ΔV BL The sense amplifier offset is a direct result of random variations in transistor parameters and system imbalances in net parasitic loading. The random nature of the sense amplifier offset comes from mismatches between adjacent devices, especially the transistors that make up the positive feedback loop and any decoupling devices in the charge sharing path. Non-uniform conditions cause variations in process parameters and thus variations in device parameters. System offsets are due to unbalanced and asymmetric coupling of parasitic charges, primarily a result of the unbalanced physical implementation. The input offset affects the minimum ΔV required for the sense amplifier to flip correctly. BL_min .

[0062] Therefore, in the embodiment of the present application, a first capacitor C1 and a second capacitor C2 are added to the sense amplifier, wherein the first capacitor C1 is connected to the first bit line BL, and the second capacitor C2 is connected to the second bit line BLN. When there is a large voltage offset on the first bit line BL, it will cause ΔV BL_min Reduced, which in turn causes the sensitive amplifier to flip abnormally and the accuracy decreases. The first capacitor C1 in the embodiment of the present application can be connected to the circuit in this case to improve the voltage offset of the first bit line BL. Specifically, in the embodiment of the present application, one end of the first capacitor C1 is connected to the first bit line BL, and the other end can be grounded through the first switch tube. When the first switch tube is turned on, the first capacitor C1 can be connected to the circuit. Similarly, in the embodiment of the present application, the second capacitor C2 can also be used to improve the voltage offset of the second bit line BLN, one end of which is connected to the second bit line BLN, and the other end can be grounded through the second switch tube. When the second switch tube is turned on, the second capacitor C2 can be connected to the circuit.

[0063] It can be understood that in the embodiment of the present application, by reducing the offset of the sense amplifier, the yield of the ferroelectric memory can be improved, and the low signal edge can be resolved more accurately, thereby reducing the scrap rate in the production process. The improved sense amplifier design reduces the erroneous reading caused by the offset, and improves the reliability of the ferroelectric memory and the integrity of the data. Moreover, the improved sense amplifier circuit is simple, low in cost, can adapt to the offset changes of the sense amplifier caused by process changes, temperature changes and other environmental factors, and has better practicality.

[0064] Specifically, in some embodiments, the sense amplifier further includes a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9 and a tenth MOS tube M10;

[0065] The gate of the seventh MOS tube M7 and the gate of the eighth MOS tube M8 are connected to the third signal port, the source of the seventh MOS tube M7 and the source of the eighth MOS tube M8 are connected to the power supply, the drain of the seventh MOS tube M7 is used to connect to the first bit line BL, and the drain of the eighth MOS tube M8 is used to connect to the second bit line BLN;

[0066] The gate of the ninth MOS tube M9 and the gate of the tenth MOS tube M10 are connected to the fourth signal port, the source of the ninth MOS tube M9 and the source of the tenth MOS tube M10 are grounded, the drain of the ninth MOS tube M9 is used to connect to the first bit line BL, and the drain of the tenth MOS tube M10 is used to connect to the second bit line BLN;

[0067] The seventh MOS tube M7 and the eighth MOS tube M8 are NMOS tubes, and the ninth MOS tube M9 and the tenth MOS tube M10 are PMOS tubes.

[0068] In the embodiment of the present application, the sensitive amplifier may further include a third signal port and a fourth signal port, which may be used to control the on and off of the seventh MOS tube M7, the eighth MOS tube M8, the ninth MOS tube M9, and the tenth MOS tube M10. Their function is to pull the output signal (BL and BLN) to GND or VDD when the input signal (SAEN and SAEP) is suspended, so as to avoid the output signal being in an unknown state. Specifically, when the third signal port inputs a high level signal and the fourth signal port inputs a low level signal, the output signal (BL and BLN) is pulled to VDD; when the third signal port inputs a low level signal and the fourth signal port inputs a high level signal, the output signal (BL and BLN) is pulled to GND.

[0069] Specifically, in some embodiments, the sense amplifier further includes at least one group of first auxiliary capacitor units;

[0070] The first auxiliary capacitor unit includes a third capacitor C3 and a third switch tube;

[0071] The first end of the third capacitor C3 is used to connect to the first bit line BL, and the second end of the third capacitor C3 is grounded through the third switch tube.

[0072] It should be noted that, in the embodiment of the present application, multiple groups of capacitors can be set in the sense amplifier, so that the number of connected capacitors can be flexibly determined according to the voltage offset on the bit line. For example, for example, the sense amplifier in the embodiment of the present application also includes at least one group of first auxiliary capacitor units, where the first auxiliary capacitor unit includes a third capacitor C3 and a third switch tube. The third capacitor C3 and the first capacitor C1 have similar functions, and they can both be connected to the first bit line BL to achieve dynamic compensation for the first bit line BL. Please refer to Figure 3 , Figure 3 FIG. 2 shows a circuit structure diagram of another sensitive amplifier provided in an embodiment of the present application. Figure 3 Of course, it can be understood that the number of the actual first auxiliary capacitor units is not limited to Figure 3 The one group shown may also be multiple groups, and this application does not limit this.

[0073] Similarly, in the embodiment of the present application, on the second bit line BLN side, the sense amplifier further includes at least one group of second auxiliary capacitor units, each group of second auxiliary capacitor units includes a fourth capacitor C4 and a fourth switch tube. The first end of the fourth capacitor C4 is used to connect the second bit line BLN, and the second end is grounded through the fourth switch tube. The function of the fourth capacitor C4 is the same as that of the aforementioned second capacitor C2, which will not be described in detail here. Figure 3 The number of the second auxiliary capacitor units shown in FIG. 1 is one group, and it may also be multiple groups, which is not limited in the present application.

[0074] In the embodiment of the present application, for each of the aforementioned switching tubes, their models can be arbitrarily selected. For example, taking the first switching tube as an example, it can use any one of the gate turn-off thyristor, power transistor, metal oxide semiconductor field effect transistor, and insulated gate bipolar transistor, and the present application does not impose any restrictions on this.

[0075] In an embodiment of the present application, a control method of a sense amplifier is further provided, which is applied to the aforementioned sense amplifier. The control method includes:

[0076] Detecting a first voltage offset on the first bit line;

[0077] If the first voltage offset is greater than or equal to a first preset threshold, the first switch tube is controlled to be turned on so that the first capacitor is grounded.

[0078] In an embodiment of the present application, when using a ferroelectric memory including the above-mentioned sensitive amplifier, the voltage offset on the first bit line of the ferroelectric memory can be detected and recorded as the first voltage offset. Then, the first voltage offset can be compared with a pre-set first preset threshold value. If it is found that the first voltage offset is greater than or equal to the first preset threshold value, it means that the voltage offset on the current first bit line is large and there is an imbalance. At this time, the first switch tube can be controlled to be turned on so that the first capacitor is grounded, thereby connecting the first capacitor to the circuit to reduce the imbalance of the sensitive amplifier.

[0079] Similarly, in the embodiment of the present application, the voltage offset on the second bit line of the ferroelectric memory can also be detected and recorded as the second voltage offset. Then, the second voltage offset can be compared with the pre-set first preset threshold value. If it is found that the second voltage offset is greater than or equal to the first preset threshold value, it means that the voltage offset on the current second bit line is large and there is an imbalance. At this time, the second switch tube can be controlled to be turned on so that the second capacitor is grounded, thereby connecting the second capacitor to the circuit to reduce the imbalance of the sensitive amplifier.

[0080] It can be understood that in the embodiment of the present application, the size of the first preset threshold can be flexibly set according to actual needs, and the present application does not impose any limitation on this.

[0081] Specifically, in some embodiments, the method further includes:

[0082] If the first voltage offset is greater than or equal to a second preset threshold, determining the target number of enabled first auxiliary capacitor units according to the magnitude of the first voltage offset; wherein the second preset threshold is greater than the first preset threshold;

[0083] The target number of third switch tubes are controlled to be turned on so that the corresponding third capacitors are grounded.

[0084] In an embodiment of the present application, for the case where the sensitive amplifier includes multiple capacitors, the case where it includes at least one group of first auxiliary capacitor units is introduced and explained. At this time, the number of connected capacitors can be further determined according to the size of the first voltage offset. For example, if the first voltage offset exceeds the first preset threshold, but its value is small, you can choose to connect only the first capacitor. If the value of the first voltage offset is large, for example, it exceeds the second preset threshold that is greater than the first preset threshold, the target number of groups of enabled first auxiliary capacitor units can be determined according to the size of the first voltage offset. Then, the third switch tube of the target number of groups can be controlled to turn on so that the corresponding third capacitor is grounded, thereby connecting multiple capacitors to the circuit. In an embodiment of the present application, by setting multiple capacitors, the processing of offset compensation can be refined, reducing the complexity in the design.

[0085] In the embodiment of the present application, a ferroelectric memory and an electronic device are also provided. The ferroelectric memory includes the above-mentioned sensitive amplifier, and the electronic device includes the ferroelectric memory. In addition, the electronic device may also include a related processor, which can be used to execute the above-mentioned control method of the sensitive amplifier.

[0086] It can be understood that the contents of the above-mentioned sensitive amplifier embodiments are applicable to the present ferroelectric memory and electronic device embodiments, and the beneficial effects achieved by the present ferroelectric memory and electronic device embodiments are the same as the beneficial effects achieved by the above-mentioned sensitive amplifier embodiments.

[0087] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present application. More specifically, in view of the properties, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional techniques of the engineer. Therefore, those skilled in the art can implement the present application set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the attached claims and their equivalents.

[0088] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0089] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0090] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

[0091] In the description of this specification, the description with reference to the terms "one embodiment", "another embodiment" or "certain embodiments" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0092] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A sensitive amplifier, characterized in that: include: A first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a first capacitor, a first switch tube, a second capacitor and a second switch tube; The gate of the first MOS tube, the gate of the third MOS tube, the drain of the second MOS tube, and the drain of the fourth MOS tube are used to connect to the second bit line of the ferroelectric memory, the gate of the second MOS tube, the gate of the fourth MOS tube, the drain of the first MOS tube, and the drain of the third MOS tube are used to connect to the first bit line of the ferroelectric memory, the source of the first MOS tube and the source of the second MOS tube are connected to the drain of the fifth MOS tube, the gate of the fifth MOS tube is connected to the first signal port, the source of the fifth MOS tube is connected to the power supply, the source of the third MOS tube and the source of the fourth MOS tube are connected to the drain of the sixth MOS tube, the gate of the sixth MOS tube is connected to the second signal port, and the source of the sixth MOS tube is grounded; The first end of the first capacitor is used to connect to the first bit line, and the second end of the first capacitor is grounded through the first switch tube; the first end of the second capacitor is used to connect to the second bit line, and the second end of the second capacitor is grounded through the second switch tube; Among them, the first MOS tube, the second MOS tube, and the fifth MOS tube are NMOS tubes, and the third MOS tube, the fourth MOS tube, and the sixth MOS tube are PMOS tubes.

2. A sensitive amplifier according to claim 1, characterized in that: The sensitive amplifier further includes a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a tenth MOS tube; The gate of the seventh MOS tube and the gate of the eighth MOS tube are connected to the third signal port, the source of the seventh MOS tube and the source of the eighth MOS tube are connected to the power supply, the drain of the seventh MOS tube is used to connect to the first bit line, and the drain of the eighth MOS tube is used to connect to the second bit line; The gate of the ninth MOS tube and the gate of the tenth MOS tube are connected to the fourth signal port, the source of the ninth MOS tube and the source of the tenth MOS tube are grounded, the drain of the ninth MOS tube is used to connect to the first bit line, and the drain of the tenth MOS tube is used to connect to the second bit line; Wherein, the seventh MOS tube and the eighth MOS tube are NMOS tubes, and the ninth MOS tube and the tenth MOS tube are PMOS tubes.

3. A sensitive amplifier according to claim 1, characterized in that: The sensitive amplifier further comprises at least one group of first auxiliary capacitor units; The first auxiliary capacitor unit includes a third capacitor and a third switch tube; The first end of the third capacitor is used to connect to the first bit line, and the second end of the third capacitor is grounded through the third switch tube.

4. A sensitive amplifier according to any one of claims 1 to 3, characterized in that: The sense amplifier further comprises at least one group of second auxiliary capacitor units; The second auxiliary capacitor unit includes a fourth capacitor and a fourth switch tube; The first end of the fourth capacitor is used to connect to the second bit line, and the second end of the fourth capacitor is grounded through the fourth switch tube.

5. A sensitive amplifier according to claim 1, characterized in that: The first switch tube includes at least one of a gate turn-off thyristor, a power transistor, a metal oxide semiconductor field effect transistor, and an insulated gate bipolar transistor.

6. A control method for a sensitive amplifier, characterized in that: Used to control the sense amplifier as claimed in claim 3, the control method comprising: Detecting a first voltage offset on the first bit line; If the first voltage offset is greater than or equal to a first preset threshold, the first switch tube is controlled to be turned on so that the first capacitor is grounded.

7. The control method of a sensitive amplifier according to claim 6, characterized in that: The method further comprises: If the first voltage offset is greater than or equal to a second preset threshold, determining the target number of enabled first auxiliary capacitor units according to the magnitude of the first voltage offset; wherein the second preset threshold is greater than the first preset threshold; The target number of third switch tubes are controlled to be turned on so that the corresponding third capacitors are grounded.

8. The control method of a sensitive amplifier according to claim 6, characterized in that: The method further comprises: Detecting a second voltage offset on the second bit line; If the second voltage offset is greater than or equal to a first preset threshold, the second switch tube is controlled to be turned on so that the second capacitor is grounded.

9. A ferroelectric memory, characterized in that: A sensitive amplifier comprising any one of claims 1-8.

10. An electronic device, characterized in that: Includes the ferroelectric memory as claimed in claim 9.

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