High-heat-dissipation embedded packaging substrate and manufacturing method thereof

Abstract

The invention discloses a high-heat-dissipation embedded packaging substrate and a manufacturing method thereof, and relates to the technical field of packaging heat dissipation. The method comprises the following steps: preparing a framework; fixing materials are arranged at the bottom of the frame; placing a chip in the cavity, placing the chip on the fixing material, and fixing the chip through the dielectric material; arranging heat dissipation metal in the cavity, and enabling the heat dissipation metal to cover the chip; arranging a second dielectric layer on the surface of the frame, and removing the fixing material to form a first substrate; the second dielectric layer covers the heat dissipation metal; manufacturing a first blind hole communicated with the heat dissipation metal in the second dielectric layer; first circuit layers are manufactured on the upper surface and the lower surface of the first substrate, and the first circuit layers are communicated with the first blind holes and the connecting terminals. According to the manufacturing method of the high-heat-dissipation embedded packaging substrate, the chip is directly packaged by the heat dissipation metal, heat generated during operation of the chip can be rapidly taken away, and the heat dissipation performance of the embedded packaging substrate is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of packaging heat dissipation, and in particular to a high heat dissipation embedded packaging substrate and a manufacturing method thereof. Background Art

[0002] With the development and progress of electronic technology, electronic products are evolving towards being short, light and thin, and the functional requirements of electronic products are becoming increasingly powerful, which has promoted the packaging structure of electronic products to develop towards a highly integrated and miniaturized direction, and embedded packaging of components such as chips has emerged; at the same time, the application of electronic components is also developing towards high frequency, high speed and high power, resulting in a rapid increase in heat flux density per unit area. As we all know, with the increase in the operating environment temperature, the operating speed of electronic components decreases, and the loss increases. At the same time, the reliability of electronic products is relatively reduced when they are operated in a high temperature environment for a long time. Therefore, if the heat generated by high-frequency, high-speed and high-power electronic components cannot be dissipated in time, the performance and reliability of electronic products will be seriously affected. Therefore, under the general trend of high frequency, high speed and high power, how to reasonably optimize the heat dissipation performance of the packaging structure is an important topic at present. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a high heat dissipation embedded packaging substrate and a manufacturing method thereof, which can optimize the heat dissipation performance of the packaging structure.

[0004] On the one hand, a method for manufacturing a high heat dissipation embedded package substrate according to an embodiment of the present invention comprises the following steps:

[0005] Prepare a frame, the frame comprising a first dielectric layer, the first dielectric layer being provided with a cavity penetrating the first dielectric layer;

[0006] Disposing a fixing material at the bottom of the frame;

[0007] Placing a chip in the cavity so that the chip is placed on the fixing material, and fixing the chip by a dielectric material;

[0008] Disposing a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip;

[0009] A second dielectric layer is arranged on the surface of the frame, and the fixing material is removed to form a first substrate; the second dielectric layer covers the heat dissipation metal;

[0010] Making a first blind hole in the second dielectric layer that is in conduction with the heat dissipation metal;

[0011] A first circuit layer is manufactured on the upper and lower surfaces of the first substrate, and the first circuit layer is conductively connected to the first blind hole and the connecting terminal.

[0012] According to some embodiments of the present invention, the step of placing a chip in the cavity, placing the chip on the fixing material, and fixing the chip by a dielectric material includes:

[0013] placing a chip in the cavity so that the chip is placed on the fixing material;

[0014] Injecting liquid dielectric material into the cavity by dispensing so that the liquid dielectric material covers the connection terminals of the chip;

[0015] The liquid medium material is solidified.

[0016] According to some embodiments of the present invention, before the step of providing a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip, the step further includes:

[0017] Chemical copper deposition or metal sputtering is performed on the frame to form a metal seed layer on the upper surface of the frame, the inner wall of the cavity, and the surface and side wall of the chip.

[0018] According to some embodiments of the present invention, the step of providing a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip includes:

[0019] attaching a photosensitive dry film to the upper surface of the frame;

[0020] exposing and developing the photosensitive dry film to form an opening, and exposing the cavity and the chip through the opening;

[0021] The frame is electroplated according to the opening to form a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip, and the photosensitive dry film is removed.

[0022] According to some embodiments of the present invention, the method further comprises the following steps:

[0023] Disposing a third dielectric layer on the upper and lower surfaces of the first substrate;

[0024] Making a second blind hole in the third dielectric layer that is in communication with the first circuit layer;

[0025] A second circuit layer is manufactured on the surface of the third dielectric layer, and the second circuit layer is connected to the first circuit layer through the second blind hole.

[0026] On the other hand, a method for manufacturing a high heat dissipation embedded package substrate according to an embodiment of the present invention comprises the following steps:

[0027] Prepare a frame, the frame comprising a first dielectric layer, the first dielectric layer being provided with a cavity penetrating the first dielectric layer;

[0028] Disposing a dielectric material at the bottom of the frame;

[0029] Placing a chip in the cavity, and pressing the connecting terminals of the chip into the dielectric material by vacuum pressing;

[0030] Disposing a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip;

[0031] A second dielectric layer is provided on the surface of the frame to form a first substrate; the second dielectric layer covers the heat dissipation metal;

[0032] Making a first blind hole in the second dielectric layer that is in electrical communication with the heat dissipation metal and the connection terminal;

[0033] A first circuit layer is manufactured on the upper and lower surfaces of the first substrate, and the first circuit layer is electrically connected to the heat dissipation metal and the connection terminal through the first blind hole.

[0034] According to some embodiments of the present invention, before the step of providing a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip, the step further includes:

[0035] Chemical copper deposition or metal sputtering is performed on the frame to form a metal seed layer on the upper surface of the frame, the inner wall of the cavity, and the surface and side wall of the chip.

[0036] According to some embodiments of the present invention, the step of providing a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip includes:

[0037] attaching a photosensitive dry film to the upper surface of the frame;

[0038] exposing and developing the photosensitive dry film to form an opening, and exposing the cavity and the chip through the opening;

[0039] The frame is electroplated according to the opening to form a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip, and the photosensitive dry film is removed.

[0040] According to some embodiments of the present invention, the method further comprises the following steps:

[0041] Disposing a third dielectric layer on the upper and lower surfaces of the first substrate;

[0042] Making a second blind hole in the third dielectric layer that is in communication with the first circuit layer;

[0043] A second circuit layer is manufactured on the surface of the third dielectric layer, and the second circuit layer is connected to the first circuit layer through the second blind hole.

[0044] On the other hand, the high heat dissipation embedded package substrate according to an embodiment of the present invention is manufactured by the manufacturing method of the high heat dissipation embedded package substrate described in any one of the above embodiments.

[0045] The high heat dissipation embedded packaging substrate and its manufacturing method according to the embodiments of the present invention have at least the following beneficial effects: by mounting components such as chips on a frame with a preset cavity, and then sealing and fixing the connection terminals of the chip with a dielectric material, and then encapsulating the chip by electroplating heat dissipation metal, the chip is directly encapsulated by the heat dissipation metal, which can quickly take away the heat generated by the chip during operation, thereby greatly improving the heat dissipation performance of the embedded packaging substrate.

[0046] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0048] Figure 1 A flowchart of the steps of a method for manufacturing a high heat dissipation embedded packaging substrate according to a first embodiment of the present invention;

[0049] Figure 2 It is a schematic structural diagram of a framework of a first embodiment of the present invention;

[0050] Figure 3 It is a schematic diagram of the structure after placing a chip in the cavity in the first embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of the structure after a metal seed layer is provided on the frame in the first embodiment of the present invention;

[0052] Figure 5 It is a schematic diagram of the structure after the photosensitive dry film is attached to the frame and exposed and developed in the first embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of the structure after heat dissipation metal is provided in the first embodiment of the present invention;

[0054] Figure 7 It is a schematic diagram of the structure after the second dielectric layer is provided in the first embodiment of the present invention;

[0055] Figure 8It is a schematic diagram of the structure after the first blind hole and the first circuit layer are provided in the first embodiment of the present invention;

[0056] Fig. 9 It is a schematic diagram of the structure after the second blind hole and the second circuit layer are provided in the first embodiment of the present invention;

[0057] Fig.10 A flowchart of the steps of a method for manufacturing a high heat dissipation embedded packaging substrate according to a second embodiment of the present invention;

[0058] Fig.11 It is a structural schematic diagram of a framework of a second embodiment of the present invention;

[0059] Fig.12 It is a schematic diagram of the structure after placing a chip in the cavity in the second embodiment of the present invention;

[0060] Fig.13 This is a schematic diagram of the structure after a metal seed layer is provided on the frame in the second embodiment of the present invention;

[0061] Fig.14 It is a schematic diagram of the structure after the photosensitive dry film is attached to the frame and exposed and developed in the second embodiment of the present invention;

[0062] Fig.15 This is a schematic diagram of the structure after heat dissipation metal is provided in the second embodiment of the present invention;

[0063] Fig.16 This is a schematic diagram of the structure after the second dielectric layer is provided in the second embodiment of the present invention;

[0064] Fig.17 It is a schematic diagram of the structure after the first blind hole and the first circuit layer are provided in the second embodiment of the present invention;

[0065] Reference numerals:

[0066] Frame 100, first dielectric layer 110, cavity 120, fixing material 200, chip 300, connecting terminal 310, dielectric material 400, heat dissipation metal 500, second dielectric layer 600, first substrate 700, first blind hole 710, first circuit layer 720, metal seed layer 800, photosensitive dry film 900, opening 910, third dielectric layer 1000, second blind hole 1100, second circuit layer 1200. DETAILED DESCRIPTION

[0067] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limitations on the present application. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0068] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0069] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0070] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0071] With the development and progress of electronic technology, electronic products are evolving towards being short, light and thin, and the functional requirements of electronic products are becoming increasingly powerful, which has promoted the packaging structure of electronic products to develop towards a highly integrated and miniaturized direction, and embedded packaging of components such as chips has emerged; at the same time, the application of electronic components is also developing towards high frequency, high speed and high power, resulting in a rapid increase in heat flux density per unit area. As we all know, with the increase in the operating environment temperature, the operating speed of electronic components decreases, and the loss increases. At the same time, the reliability of electronic products is relatively reduced when they are operated in a high temperature environment for a long time. Therefore, if the heat generated by high-frequency, high-speed and high-power electronic components cannot be dissipated in time, the performance and reliability of electronic products will be seriously affected. Therefore, under the general trend of high frequency, high speed and high power, how to reasonably optimize the heat dissipation performance of the packaging structure is an important topic at present.

[0072] To this end, an embodiment of the present invention proposes a high heat dissipation embedded packaging substrate and a manufacturing method thereof, which is performed by mounting components such as chips on a frame with a preset cavity, and then sealing and fixing the connection terminals of the chip with a dielectric material, and then encapsulating the chip by electroplating heat dissipation metal. In this way, the chip is directly encapsulated by the heat dissipation metal, which can quickly take away the heat generated by the chip during operation, thereby greatly improving the heat dissipation performance of the embedded packaging substrate.

[0073] The following is combined with Figure 1 To Attachment Fig.17 , a high heat dissipation embedded packaging substrate and a manufacturing method thereof according to an embodiment of the present invention are described in detail.

[0074] On the one hand, if Figure 1 As shown, the method for manufacturing a high heat dissipation embedded package substrate according to an embodiment of the present invention comprises the following steps:

[0075] Step S100: preparing a frame 100, wherein the frame 100 includes a first dielectric layer 110, and the first dielectric layer 110 is provided with a cavity 120 penetrating the first dielectric layer 110;

[0076] Step S200: placing a fixing material 200 at the bottom of the frame 100;

[0077] Step S300: placing the chip 300 in the cavity 120, placing the chip 300 on the fixing material 200, and fixing the chip 300 through the dielectric material 400;

[0078] Step S400: disposing a heat dissipation metal 500 in the cavity 120 so that the heat dissipation metal 500 covers the chip 300;

[0079] Step S500: a second dielectric layer 600 is disposed on the surface of the frame 100, and the fixing material 200 is removed to form a first substrate 700; the second dielectric layer 600 covers the heat dissipation metal 500;

[0080] Step S600: making a first blind hole 710 in the second dielectric layer 600 and connected to the heat dissipation metal 500;

[0081] Step S700 : manufacturing a first circuit layer 720 on the upper and lower surfaces of the first substrate 700 , wherein the first circuit layer 720 is electrically connected to the first blind vias 710 and the connection terminals 310 of the chip 300 .

[0082] Specifically, in this example, the frame 100 is a polymer frame, and the number of cavities 120 provided therein can be set according to the number of chips to be embedded and packaged, which is not limited here. The cavity 120 penetrates the first dielectric layer 110 from top to bottom; the first dielectric layer 110 can be made of epoxy resin or BT (bismaleimide) containing glass fiber and having good strength and rigidity, or a mixture thereof.

[0083] like Figure 2 and Figure 3 As shown, in some embodiments of the present invention, after the frame 100 is prepared, a fixing material 200 is disposed at the bottom of the frame 100, so that the chip 300 can be placed in the cavity 120 of the frame 100, and the fixing material 200 plays a preliminary supporting and fixing role. It should be noted that the fixing material 200 can be a material with a certain viscosity such as tape.

[0084] like Figure 3 As shown, in some embodiments of the present invention, after the chip 300 is placed in the cavity 120 and supported by the fixing material 200 , a dielectric material 400 is disposed in the cavity 120 and the chip 300 is fixed by the dielectric material 400 .

[0085] Specifically, in this example, the above step S300: placing the chip 300 in the cavity 120, placing the chip 300 on the fixing material 200, and fixing the chip 300 by the dielectric material 400, includes the following three steps:

[0086] (1) placing the chip 300 in the cavity 120 so that the chip 300 is placed on the fixing material 200;

[0087] (2) Injecting liquid dielectric material into the cavity 120 by dispensing, so that the liquid dielectric material covers the connection terminal 310 of the chip 300;

[0088] (3) Solidifying the liquid medium material.

[0089] It should be noted that in this example, the dielectric material 400 is a liquid dielectric material. Therefore, the liquid dielectric material (such as epoxy resin or bismaleimide dielectric material, etc.) is injected into the cavity 120 by dispensing, and the dispensing amount is controlled so that the liquid dielectric material completely wraps the connecting terminal 310 of the chip 300. The liquid dielectric material is then solidified, and the chip 300 can be fixed by the dielectric material 400.

[0090] like Figure 4 As shown, in some embodiments of the present invention, in order to facilitate the subsequent electroplating to form the heat dissipation metal 500, it is also necessary to perform chemical copper deposition or metal sputtering on the frame 100 to form a metal seed layer 800 on the upper surface of the frame 100, the inner wall of the cavity 120, and the surface and sidewall of the chip 300. The metal seed layer 800 is conducive to the subsequent electroplating operation.

[0091] like Figure 5 and Figure 6 As shown, in some embodiments of the present invention, the above step S400: disposing the heat dissipation metal 500 in the cavity 120 so that the heat dissipation metal 500 covers the chip 300, specifically includes the following three steps:

[0092] (1) attaching a photosensitive dry film 900 to the upper surface of the frame 100;

[0093] (2) exposing and developing the photosensitive dry film 900 to form an opening 910, and exposing the cavity 120 and the chip 300 through the opening 910;

[0094] (3) Electroplating is performed on the frame 100 according to the opening 910 to form a heat dissipation metal 500 in the cavity 120 so that the heat dissipation metal 500 covers the chip 300 and the photosensitive dry film 900 is removed.

[0095] Specifically, in order to form the heat dissipation metal 500 by electroplating on the peripheral side of the chip 300, it is necessary to use the photosensitive dry film 900 to protect the rest of the frame 100, and then the photosensitive dry film 900 is exposed and developed, so as to open the photosensitive dry film 900 and expose the cavity 120 and the chip 300; then electroplating is performed to form the heat dissipation metal 500 in the cavity 120, and the heat dissipation metal 500 covers the periphery of the chip 300 to dissipate heat for the chip 300. Finally, the photosensitive dry film 900 is removed, and the excess metal seed layer 800 on the frame 100 is etched away. It should be noted that the heat dissipation metal 500 can be copper or other metals, and the heat generated during the operation of the chip 300 is dissipated by the heat conduction of the metal; since the heat dissipation metal 500 directly encapsulates the chip 300 and has a large contact area with the chip 300, it has better heat dissipation performance.

[0096] like Figure 7 As shown, in some embodiments of the present invention, after the heat dissipation metal 500 is set, the second dielectric layer 600 is pressed on the surface of the frame 100, and the fixing material 200 at the bottom of the frame 100 is removed to form a first substrate 700; the second dielectric layer 600 covers the upper surface of the frame 100 and covers the heat dissipation metal 500.

[0097] like Figure 8 As shown, in some embodiments of the present invention, after the second dielectric layer 600 is pressed, a first blind hole 710 is made in the second dielectric layer 600 to be connected to the heat dissipation metal 500, and then a first circuit layer 720 is made on the upper and lower surfaces of the first substrate 700, and the first circuit layer 720 is connected to the first blind hole 710 and the connection terminal 310 of the chip 300. The first circuit layer 720 on the upper surface of the first substrate 700 is connected to the heat dissipation metal 500 through the first blind hole 710, and the first circuit layer 720 on the lower surface of the first substrate 700 is directly connected to the connection terminal 310 of the chip 300. It should be noted that when making the first blind hole 710, the second dielectric layer 600 can be opened by laser or other methods, and then the hole is filled and electroplated at the window to form the first blind hole 710.

[0098] Further, as shown in 9, it is also possible to Figure 8 Based on the package substrate shown in the figure, the package substrate is further designed with additional layers. During the additional layer process:

[0099] A third dielectric layer 1000 is disposed on the upper and lower surfaces of the first substrate 700;

[0100] A second blind hole 1100 is formed in the third dielectric layer 1000 and is connected to the first circuit layer 720;

[0101] A second circuit layer 1200 is fabricated on the surface of the third dielectric layer 1000 , and the second circuit layer 1200 is electrically connected to the first circuit layer 720 via a second blind hole 1100 .

[0102] It should be noted that, on this basis, further layer-adding design can be performed to ultimately form a packaging substrate with the required number of layers.

[0103] According to the method for manufacturing a high heat dissipation embedded packaging substrate in an embodiment of the present invention, components such as a chip 300 are mounted on a frame 100 with a preset cavity 120, and then the connection terminals 310 of the chip 300 are sealed and fixed using a dielectric material 400, and then the chip 300 is packaged by electroplating a heat dissipation metal 500. In this way, the chip 300 is directly packaged by the heat dissipation metal 500, which can quickly take away the heat generated by the chip 300 during operation, thereby greatly improving the heat dissipation performance of the embedded packaging substrate.

[0104] On the other hand, Fig.10 As shown, the present invention also proposes another method for manufacturing a high heat dissipation embedded packaging substrate, the method comprising the following steps:

[0105] Step S110: preparing a frame 100, wherein the frame 100 includes a first dielectric layer 110, and the first dielectric layer 110 is provided with a cavity 120 penetrating the first dielectric layer 110;

[0106] Step S210: placing a dielectric material 400 at the bottom of the frame 100;

[0107] Step S310: placing the chip 300 in the cavity 120, and pressing the connecting terminals 310 of the chip 300 into the dielectric material 400 by vacuum pressing;

[0108] Step S410: disposing a heat dissipation metal 500 in the cavity 120 so that the heat dissipation metal 500 covers the chip 300;

[0109] Step S510: a second dielectric layer 600 is disposed on the surface of the frame 100 to form a first substrate 700; the second dielectric layer 600 covers the heat dissipation metal 500;

[0110] Step S610: making a first blind hole 710 in the second dielectric layer 600, which is conductive with the heat dissipation metal 500 and the connection terminal 310;

[0111] Step S710 : manufacturing a first circuit layer 720 on the upper and lower surfaces of the first substrate 700 , and the first circuit layer 720 is electrically connected to the heat dissipation metal 500 and the connection terminal 310 through the first blind hole 710 .

[0112] Specifically, in this example, the frame 100 is a polymer frame, and the number of cavities 120 provided therein can be set according to the number of chips to be embedded and packaged, which is not limited here. The cavity 120 penetrates the first dielectric layer 110 from top to bottom; the first dielectric layer 110 can be made of epoxy resin or BT (bismaleimide) containing glass fiber and having good strength and rigidity, or a mixture thereof.

[0113] like Fig.11 and Fig.12As shown, in some embodiments of the present invention, after the frame 100 is prepared, a dielectric material 400 is set at the bottom of the frame 100, so that the chip 300 can be placed in the cavity 120 of the frame 100, and the dielectric material 400 plays a preliminary supporting and fixing role. The dielectric material 400 can be made of an insulating material with a certain viscosity such as NBF-EOS. Then, the chip 300 is placed in the cavity 120, and the connecting terminal 310 of the chip 300 is completely pressed into the dielectric material 400 by vacuum pressing, so that the bottom of the chip 300 is directly encapsulated by the dielectric material 400.

[0114] like Fig.13 As shown, in some embodiments of the present invention, in order to facilitate the subsequent electroplating to form the heat dissipation metal 500, it is also necessary to perform chemical copper deposition or metal sputtering on the frame 100 to form a metal seed layer 800 on the upper surface of the frame 100, the inner wall of the cavity 120, and the surface and sidewall of the chip 300. The metal seed layer 800 is conducive to the subsequent electroplating operation.

[0115] like Fig.14 and Fig.15 As shown, in some embodiments of the present invention, the above step S410: disposing the heat dissipation metal 500 in the cavity 120 so that the heat dissipation metal 500 covers the chip 300, specifically includes the following three steps:

[0116] (1) attaching a photosensitive dry film 900 to the upper surface of the frame 100;

[0117] (2) exposing and developing the photosensitive dry film 900 to form an opening 910, and exposing the cavity 120 and the chip 300 through the opening 910;

[0118] (3) Electroplating is performed on the frame 100 according to the opening 910 to form a heat dissipation metal 500 in the cavity 120 so that the heat dissipation metal 500 covers the chip 300 and the photosensitive dry film 900 is removed.

[0119] Specifically, in order to form the heat dissipation metal 500 by electroplating on the peripheral side of the chip 300, it is necessary to use the photosensitive dry film 900 to protect the rest of the frame 100, and then the photosensitive dry film 900 is exposed and developed, so as to open the photosensitive dry film 900 and expose the cavity 120 and the chip 300; then electroplating is performed to form the heat dissipation metal 500 in the cavity 120, and the heat dissipation metal 500 covers the periphery of the chip 300 to dissipate heat for the chip 300. Finally, the photosensitive dry film 900 is removed, and the excess metal seed layer 800 on the frame 100 is etched away. It should be noted that the heat dissipation metal 500 can be copper or other metals, and the heat generated during the operation of the chip 300 is dissipated by the heat conduction of the metal; since the heat dissipation metal 500 directly encapsulates the chip 300 and has a large contact area with the chip 300, it has better heat dissipation performance.

[0120] like Fig.16 As shown, in some embodiments of the present invention, after the heat dissipation metal 500 is set, the second dielectric layer 600 is pressed on the surface of the frame 100 to form a first substrate 700; the second dielectric layer 600 covers the upper surface of the frame 100 and covers the heat dissipation metal 500.

[0121] like Fig.17 As shown, in some embodiments of the present invention, after the second dielectric layer 600 is pressed, a first blind hole 710 is made in the second dielectric layer 600 to be connected to the heat dissipation metal 500, and then a first circuit layer 720 is made on the upper and lower surfaces of the first substrate 700, and the first circuit layer 720 is connected to the first blind hole 710. The first circuit layer 720 on the upper surface of the first substrate 700 is connected to the heat dissipation metal 500 through the first blind hole 710, and the first circuit layer 720 on the lower surface of the first substrate 700 is connected to the connection terminal 310 of the chip 300 through the first blind hole 710. It should be noted that when making the first blind hole 710, the second dielectric layer 600 can be opened by laser or other methods, and then the opening can be filled with holes by electroplating to form the first blind hole 710.

[0122] Furthermore, you can Fig.17 Based on the package substrate shown in FIG. 1 , the package substrate is further designed with additional layers. The process of adding layers is similar to Fig. 9 similar:

[0123] A third dielectric layer 1000 is disposed on the upper and lower surfaces of the first substrate 700;

[0124] A second blind hole 1100 is formed in the third dielectric layer 1000 and is connected to the first circuit layer 720;

[0125] A second circuit layer 1200 is fabricated on the surface of the third dielectric layer 1000 , and the second circuit layer 1200 is electrically connected to the first circuit layer 720 via a second blind hole 1100 .

[0126] It should be noted that, on this basis, further layer-adding design can be performed to ultimately form a packaging substrate with the required number of layers.

[0127] According to the method for manufacturing a high heat dissipation embedded packaging substrate in an embodiment of the present invention, components such as a chip 300 are mounted on a frame 100 with a preset cavity 120, and then the connection terminals 310 of the chip 300 are sealed and fixed using a dielectric material 400, and then the chip 300 is packaged by electroplating a heat dissipation metal 500. In this way, the chip 300 is directly packaged by the heat dissipation metal 500, which can quickly take away the heat generated by the chip 300 during operation, thereby greatly improving the heat dissipation performance of the embedded packaging substrate.

[0128] On the other hand, the embodiment of the present invention also provides a high heat dissipation embedded packaging substrate, the structure of which is as follows: Figure 8 or Fig. 9 or Fig.17 As shown, the high heat dissipation embedded packaging substrate is manufactured by the manufacturing method of the high heat dissipation embedded packaging substrate described in any one of the above embodiments.

[0129] It should be noted that the contents of the above method embodiments are all applicable to this embodiment, the functions specifically implemented by this embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0130] Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described according to embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0131] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A method for manufacturing a high heat dissipation embedded packaging substrate, characterized in that: The following steps are involved: Prepare a frame, the frame comprising a first dielectric layer, the first dielectric layer being provided with a cavity penetrating the first dielectric layer; Disposing a fixing material at the bottom of the frame; Placing a chip in the cavity so that the chip is placed on the fixing material, and fixing the chip by a dielectric material; Disposing a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip; A second dielectric layer is disposed on the surface of the frame, and the fixing material is removed to form a first substrate; The second dielectric layer covers the heat dissipation metal; Making a first blind hole in the second dielectric layer that is in conduction with the heat dissipation metal; A first circuit layer is manufactured on the upper and lower surfaces of the first substrate, and the first circuit layer is conductively connected to the first blind hole and the connecting terminal.

2. The method for manufacturing a high heat dissipation embedded package substrate according to claim 1, characterized in that: The step of placing a chip in the cavity, placing the chip on the fixing material, and fixing the chip by a dielectric material comprises: placing a chip in the cavity so that the chip is placed on the fixing material; Injecting liquid dielectric material into the cavity by dispensing so that the liquid dielectric material covers the connection terminals of the chip; The liquid medium material is solidified.

3. The method for manufacturing a high heat dissipation embedded package substrate according to claim 1, characterized in that: Before the step of disposing a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip, the step further includes: Chemical copper deposition or metal sputtering is performed on the frame to form a metal seed layer on the upper surface of the frame, the inner wall of the cavity, and the surface and side wall of the chip.

4. The method for manufacturing a high heat dissipation embedded package substrate according to claim 1, characterized in that: The step of arranging a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip comprises: attaching a photosensitive dry film to the upper surface of the frame; exposing and developing the photosensitive dry film to form an opening, and exposing the cavity and the chip through the opening; The frame is electroplated according to the opening to form a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip, and the photosensitive dry film is removed.

5. The method for manufacturing a high heat dissipation embedded package substrate according to claim 1, characterized in that: The method further comprises the following steps: Disposing a third dielectric layer on the upper and lower surfaces of the first substrate; Making a second blind hole in the third dielectric layer that is in communication with the first circuit layer; A second circuit layer is manufactured on the surface of the third dielectric layer, and the second circuit layer is connected to the first circuit layer through the second blind hole.

6. A method for manufacturing a high heat dissipation embedded packaging substrate, characterized in that: The following steps are involved: Prepare a frame, the frame comprising a first dielectric layer, the first dielectric layer being provided with a cavity penetrating the first dielectric layer; Disposing a dielectric material at the bottom of the frame; Placing a chip in the cavity, and pressing the connecting terminals of the chip into the dielectric material by vacuum pressing; Disposing a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip; A second dielectric layer is disposed on the surface of the frame to form a first substrate; The second dielectric layer covers the heat dissipation metal; Making a first blind hole in the second dielectric layer that is in electrical communication with the heat dissipation metal and the connection terminal; A first circuit layer is manufactured on the upper and lower surfaces of the first substrate, and the first circuit layer is electrically connected to the heat dissipation metal and the connection terminal through the first blind hole.

7. The method for manufacturing a high heat dissipation embedded package substrate according to claim 6, characterized in that: Before the step of disposing a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip, the step further includes: Chemical copper deposition or metal sputtering is performed on the frame to form a metal seed layer on the upper surface of the frame, the inner wall of the cavity, and the surface and side wall of the chip.

8. The method for manufacturing a high heat dissipation embedded package substrate according to claim 6, characterized in that: The step of arranging a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip comprises: attaching a photosensitive dry film to the upper surface of the frame; exposing and developing the photosensitive dry film to form an opening, and exposing the cavity and the chip through the opening; The frame is electroplated according to the opening to form a heat dissipation metal in the cavity so that the heat dissipation metal covers the chip, and the photosensitive dry film is removed.

9. The method for manufacturing a high heat dissipation embedded package substrate according to claim 6, characterized in that: The method further comprises the following steps: Disposing a third dielectric layer on the upper and lower surfaces of the first substrate; Making a second blind hole in the third dielectric layer that is in communication with the first circuit layer; A second circuit layer is manufactured on the surface of the third dielectric layer, and the second circuit layer is connected to the first circuit layer through the second blind hole.

10. A high heat dissipation embedded packaging substrate, characterized in that: The high heat dissipation embedded packaging substrate is manufactured by the manufacturing method of the high heat dissipation embedded packaging substrate according to any one of claims 1 to 5 or the manufacturing method of the high heat dissipation embedded packaging substrate according to any one of claims 6 to 9.

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