Stuffing correction screening method and system for wafer test results

Abstract

The invention provides a rigorous correction screening method and system for a wafer test result. The method comprises the following steps: identifying layout data of a chip layout layout on a wafer; performing potential singular point identification on the resource information to obtain singular point layout information of a chip layout in a chip placement unit domain, and determining transient response data for performing deviation correction response during a chip layout test on a wafer; generating continuous failure characteristics on adjacent bits of the chip in the chip layout layout, and determining dynamic response data for performing deviation correction response when the chip layout test is performed on the wafer; and according to the transient response data and the dynamic response data, determining a feedback correction index of the wafer during the chip layout test, and then tightly filtering a chip on the wafer for the design of the failed computer chip. According to the scheme, the wafer test results are screened based on the feedback correction indexes, and the accuracy of rigorous correction screening during wafer test can be improved under the influence of insufficient identification of performance deviation generated during rigorous correction screening.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor product manufacturing, and more specifically, to a method and system for stricter correction screening of wafer test results. Background Art

[0002] Conductor product manufacturing refers to the process of processing semiconductor materials (such as silicon, gallium arsenide, etc.) into electronic components and integrated circuits. This process includes multiple steps, such as wafer manufacturing, doping, oxidation, photolithography, etching, deposition and packaging. Its function is to convert basic materials into functional components that can be used in electronic devices (such as computers, mobile phones, sensors, etc.) to meet the needs of modern electronic technology.

[0003] The existing method of strict correction and screening of wafer test results usually includes three main stages: data collection, analysis and screening. First, in the data collection stage, each chip is fully tested using automated test equipment to collect key performance-related indicators such as voltage, power consumption, temperature and transient response. Then, statistical and data processing techniques are applied to conduct in-depth analysis of the collected data to identify performance indicators related to failure modes. By comparing current test results with historical data, manufacturers can set strict thresholds based on experience to ensure that only chips that meet high standards are screened out. Finally, the performance data of all chips are compared with the set standards, and any chips that do not meet the standards are All chips will be marked as failed, but in the existing wafer test results using tightened correction screening, due to the lack of an effective dynamic feedback control mechanism, it is impossible to monitor key operating parameters in real time. It relies on static thresholds and historical data for evaluation, which limits its ability to adapt to complex production environments. As a result, some failed chips are not accurately eliminated during the testing phase, resulting in insufficient recognition of performance deviations during tightened correction screening of wafers, reducing the accuracy of tightened correction screening during wafer testing. Therefore, how to improve the accuracy of tightened correction screening during wafer testing under the influence of insufficient recognition of performance deviations during tightened correction screening of wafers is a problem faced by the industry. Summary of the invention

[0004] The present application provides a method and system for tightened correction screening of wafer test results, which can improve the accuracy of tightened correction screening during wafer testing under the influence of insufficient recognition of performance deviations generated during tightened correction screening of wafers.

[0005] In a first aspect, the present application provides a method for screening wafer test results with stricter correction, comprising the following steps:

[0006] Perform chip layout testing on wafers used for computer chip design to identify layout data of chip layouts on the wafers;

[0007] Correcting and constraining the layout data to obtain a constraint distance of chip layout in a chip layout layout on a wafer, and determining a component offset between chips in a chip placement unit domain according to the constraint distance;

[0008] Obtaining resource information occupied by a wafer used for computer chip design when performing chip layout planning, identifying potential singular points on the resource information, obtaining singular point layout information of the chip layout in the chip placement unit domain, and determining transient response data for deviation correction response during chip layout testing on the wafer through the singular point layout information and the component offset;

[0009] Generate continuous failure characteristics on adjacent bits of the chip in the chip layout based on the netlist connection information of the chip functional connection after the chip layout of the wafer used for computer chip design, and determine the dynamic response data of the deviation correction response during the chip layout test on the wafer according to the continuous failure characteristics;

[0010] A feedback correction index of a wafer for computer chip design during chip layout testing is determined according to the transient response data and the dynamic response data, and chips on the wafer for computer chip design that fail are strictly filtered according to the feedback correction index.

[0011] In some embodiments, performing correction and constraint on the layout data to obtain the constraint distance of the chip layout in the chip layout layout on the wafer specifically includes:

[0012] Determine the layout trajectory of the chip in the chip layout layout on the wafer according to the layout data;

[0013] Determine layout constraint information in the chip layout on the wafer;

[0014] The layout trajectory is adjusted using the layout constraint information to obtain a constraint distance of the chip layout in the chip layout diagram on the wafer.

[0015] In some embodiments, determining the component offset between chips in the chip placement unit domain according to the constraint distance specifically includes:

[0016] Determining alignment information of the chip in the chip placement unit by using the constraint distance;

[0017] determining a matching position of a chip on a chip placement unit;

[0018] The component offset is determined based on the alignment information and the matching position.

[0019] In some embodiments, identifying potential singular points on the resource information to obtain singular point layout information of the chip layout in the chip placement unit domain specifically includes:

[0020] Determine singular point position parameters of chip layout in the chip placement unit domain according to the resource information;

[0021] Determining a layout confidence of a chip layout in a chip placement unit domain by using the singular point position parameters;

[0022] The layout confidence is used to check the chip placement unit domain to obtain singular point layout information of the chip layout in the chip placement unit domain.

[0023] In some embodiments, determining transient response data for performing deviation correction response during chip layout testing on a wafer by using the singular point layout information and the component offset specifically includes:

[0024] Determine reference position information for performing deviation correction response during chip layout testing on a wafer according to the singular point layout information;

[0025] Determining layout rules for performing deviation correction responses during chip layout testing on a wafer based on the component offset;

[0026] The transient response data for performing deviation correction response is determined by the reference position information and the layout rule.

[0027] In some embodiments, determining the feedback correction index of the wafer used for computer chip design during chip layout testing according to the transient response data and the dynamic response data specifically includes:

[0028] Determining layout feedback data of a wafer used for computer chip design during chip layout testing through the transient response data;

[0029] Determining the tightening correction characteristics of a wafer used for computer chip design during chip layout testing through the dynamic response data;

[0030] A feedback correction index of the wafer during chip layout testing is determined according to the layout feedback data and the tightened correction feature.

[0031] In some embodiments, the image information is converted into electronic layout data by using dedicated layout extraction software (such as CAD tools or EDA tools).

[0032] In a second aspect, the present application provides a system for screening wafer test results with stricter correction, comprising:

[0033] An identification module is used to perform chip layout testing on a wafer used for computer chip design and to identify layout data of a chip layout on the wafer;

[0034] A processing module, used for correcting and constraining the layout data, obtaining a constraint distance of a chip layout in a chip layout on a wafer, and determining a component offset between chips in a chip placement unit domain according to the constraint distance;

[0035] The processing module is further used to obtain resource information occupied by a wafer used for computer chip design when performing chip layout planning, identify potential singular points on the resource information, obtain singular point layout information of the chip layout in the chip placement unit domain, and determine transient response data for deviation correction response during chip layout testing on the wafer through the singular point layout information and the component offset;

[0036] The processing module is further used to generate continuous failure characteristics on adjacent bits of the chip in the chip layout based on the netlist connection information of the chip function connection after the chip layout of the wafer used for computer chip design, and determine the dynamic response data for deviation correction response during the chip layout test on the wafer according to the continuous failure characteristics;

[0037] The execution module is used to determine the feedback correction index of the wafer used for computer chip design during chip layout test according to the transient response data and the dynamic response data, and to strictly filter the failed chips on the wafer used for computer chip design according to the feedback correction index.

[0038] In a third aspect, the present application provides a computer device, comprising a memory and a processor, wherein the memory stores codes, and the processor is configured to obtain the codes and execute the above-mentioned method for tightened correction screening of wafer test results.

[0039] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned method for stricter correction screening of wafer test results is implemented.

[0040] The technical solution provided by the embodiments disclosed in this application has the following beneficial effects:

[0041] The present application provides a method and system for rigorous correction screening of wafer test results. First, a chip layout test is performed on a wafer used for computer chip design to identify the layout data of the chip layout on the wafer; then, the layout data is corrected and constrained to obtain the constraint distance of the chip layout in the chip layout on the wafer, and the component offset between chips in the chip placement unit domain is determined according to the constraint distance; secondly, resource information occupied by the wafer used for computer chip design during chip layout planning is obtained, potential singularities are identified for the resource information, singularity layout information of the chip layout in the chip placement unit domain is obtained, and the singularity layout information and the corresponding singularity layout information are used to determine the component offset between chips in the chip placement unit domain. The component offset is used to determine transient response data for deviation correction response during chip layout test on the wafer; then, based on the netlist connection information of chip functional connections after chip layout of the wafer for computer chip design, continuous failure characteristics on adjacent bits of the chip in the chip layout are generated, and dynamic response data for deviation correction response during chip layout test on the wafer is determined according to the continuous failure characteristics; finally, feedback correction indicators of the wafer for computer chip design during chip layout test are determined according to the transient response data and the dynamic response data, and chips on the wafer for computer chip design that fail are strictly filtered according to the feedback correction indicators.

[0042] It can be seen that the present application performs strict screening when performing chip layout testing on wafers used for computer chip design; first, by efficiently identifying and analyzing the layout data of the wafer, the information integrity and accuracy in the design process are ensured. Then, the implementation of correction constraints makes the chip layout more physically compatible, reduces interference between chips, improves the overall stability of the layout, reduces the risk of potential failure, and ensures the reliability of the chip. Thirdly, by identifying potential singularities of resource information, bottlenecks can be proactively identified and avoided in the layout planning stage, thereby optimizing resource allocation and improving the efficiency and controllability of the chip layout process. Then, the generated transient response data provides a dynamic perspective on the performance of the chip under different working conditions, so that the chip performance can be better understood, the adaptability of the design can be improved, and the stability and performance consistency in practical applications can be ensured. Among them, the analysis of dynamic response data makes it easier to analyze the continuous failure characteristics of adjacent bits of the chip. Finally, by formulating feedback correction indicators, more accurate failure screening can be achieved, the accuracy and effectiveness of screening can be improved, and only chips that meet strict standards can enter the production process, which makes up for the impact of insufficient recognition of performance deviations when performing strict correction screening on wafers, thereby improving the accuracy of strict correction screening during wafer testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is an exemplary flow chart of a method for screening wafer test results with stricter correction according to some embodiments of the present application;

[0044] Figure 2 is a schematic diagram of a chip failure bathtub curve according to some embodiments of the present application;

[0045] Figure 3 It is a schematic diagram of the basic process of chip design according to some embodiments of the present application;

[0046] Figure 4 is a schematic diagram of a structure of a system for screening wafer test results with tightened correction according to some embodiments of the present application;

[0047] Figure 5 It is a schematic diagram of the structure of a computer device for implementing a stricter correction screening method for wafer test results according to some embodiments of the present application. DETAILED DESCRIPTION

[0048] In order to better understand the technical solution of the present application, the technical solution of the present application will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0049] refer to Figure 1 , which is an exemplary flow chart of a method for screening wafer test results with stricter correction according to some embodiments of the present application. The method 100 for screening wafer test results with stricter correction mainly includes the following steps:

[0050] In step 101, a chip layout test is performed on a wafer used for computer chip design to identify layout data of the chip layout on the wafer.

[0051] In the specific implementation, first, use high-precision scanning equipment, such as optical microscopes, electron beam microscopes or laser scanners, to scan the entire wafer surface. These devices can capture detailed images of the wafer surface, especially geometric features such as the position, shape and size of the chip; then, after the scan is completed, the system will generate multiple high-resolution images. In order to ensure the accuracy of the data, image preprocessing is required, including denoising, contrast enhancement, and edge detection; finally, the image information can be converted into layout data through dedicated layout extraction software (such as CAD tools or EDA tools), that is, the layout data of the chip layout on the wafer is obtained.

[0052] It should be noted that the layout data of the chip layout on the wafer in this application represents the electronic data of the geometric information and spatial relationship of the chip layout on the wafer. These data usually include the physical position, shape, size, and distance and arrangement between chips, providing accurate spatial reference for chip manufacturing and testing, ensuring that in the actual manufacturing process, the chips are arranged according to the design specifications to avoid position deviation or interconnection problems.

[0053] In step 102, the layout data is constrained and modified to obtain a constraint distance of the chip layout in the chip layout layout on the wafer, and the component offset between the chips in the chip placement unit domain is determined according to the constraint distance.

[0054] In some embodiments, reference Figure 2 As shown in the figure, this is a schematic diagram of the basic process of chip design. First, a layer of photoresist is applied to the surface of the wafer (or substrate) and dried. The dried wafer is transferred to the photolithography machine. Light passes through a mask to project the pattern on the mask onto the photoresist on the surface of the wafer to achieve exposure and stimulate photochemical reaction. The exposed wafer is baked for the second time, which is the so-called post-exposure baking. Post-baking makes the photochemical reaction more complete. Finally, the developer is sprayed on the photoresist on the surface of the wafer to develop the exposure pattern. After development, the pattern on the mask is It is retained on the photoresist; coating, baking and development are all completed in the photoresist developer, and exposure is completed in the photolithography machine. The photoresist developer and the photolithography machine are generally operated online. The wafer is transferred between each unit and machine by a robot. The entire exposure and development system is closed, and the wafer is not directly exposed to the surrounding environment to reduce the impact of harmful components in the environment on the photoresist and photochemical reactions. After several processes, grid-like grains are formed on the wafer, and the electrical characteristics of each grain are tested by needle testing.

[0055] In some embodiments, reference Figure 3 As shown in the figure, this is a schematic diagram of the chip failure bathtub curve. With the rapid development of the electronic industry towards intelligence, the demand for chips is becoming more and more extensive. The special application scenarios of chips have extremely high requirements for safety and reliability. Therefore, strict screening is performed at the test end to screen out early failure chips; the early failure period is a stage with a relatively high failure rate. The cause of failure is usually design defects, manufacturing abnormalities or material defects in the chip. The purpose of strict testing and screening is to screen out defective chips before the chip is shipped, and these defective chips are likely to be early failure chips (such as Figure 3 As shown in the figure, the failure rates of chips on the timeline include early failure rate, accidental failure rate and loss failure rate; common tightened screening includes stacked wafer diagram, aging and other tightened screening items.

[0056] In some embodiments, the layout data is corrected and constrained to obtain the constraint distance of the chip layout in the chip layout layout on the wafer, which can be achieved by the following steps:

[0057] Determine the layout trajectory of the chip in the chip layout layout on the wafer according to the layout data;

[0058] Determine layout constraint information in the chip layout on the wafer;

[0059] The layout trajectory is adjusted using the layout constraint information to obtain a constraint distance of the chip layout in the chip layout diagram on the wafer.

[0060] In specific implementation, first, the geometric shape and position of the chip are extracted from the layout data using image processing technology, and the movement trajectory of the chip is calculated. This can be achieved by performing edge detection and tracking algorithms on the chip contour to generate the path of each chip in the layout process, that is, the layout trajectory; then, the design rules and manufacturing processes related to the chip layout are analyzed to identify the layout constraint information that needs to be followed, such as the minimum spacing, maximum spacing, and electrical isolation requirements, etc. This can be achieved through a systematic analysis of the design documents and process specifications. For example, the minimum spacing requirement is 5 microns, that is, the distance between any two chips cannot be less than this value; finally, the identified layout constraint information is applied to the layout trajectory of the chip, and the chip position is adjusted using an optimization algorithm (such as particle swarm optimization or simulated annealing) to ensure that the position of each chip meets the constraint requirements. The adjustment can be iteratively performed until the layout of all chips meets the constraint conditions, and the output result is used as the constraint distance of the chip layout in the chip layout diagram on the wafer. In other embodiments, other methods can also be used to determine the constraint distance of the chip layout in the chip layout diagram on the wafer, which is not limited here.

[0061] It should be noted that the layout trajectory in this application represents the path of the chip from the starting position to the final position during the chip layout process on the wafer; the layout constraint information represents various restrictions related to the chip layout specified in the chip design, such as spacing, angles, etc., which can ensure the reasonable layout of the chip and reduce the failure rate; the constraint distance represents the minimum or maximum distance between chips in the chip layout that meets the manufacturing and electrical design requirements, which helps to ensure the rationality of the chip layout and avoid electrical problems caused by improper distance.

[0062] In some embodiments, determining the component offset between chips in the chip placement unit domain according to the constraint distance can be implemented by the following steps:

[0063] Determining alignment information of the chip in the chip placement unit by using the constraint distance;

[0064] determining a matching position of a chip on a chip placement unit;

[0065] The component offset is determined based on the alignment information and the matching position.

[0066] In the specific implementation, first, the ideal placement position of each chip is identified, and the alignment information of the chip in the placement unit is determined. This can be achieved through geometric measurement and coordinate system comparison to ensure that each chip can be correctly placed within the specified constraint range. For example, the ideal position of chip A is (100, 200), and the error range allowed by the constraint distance is ±5 microns, then the alignment information of chip A will include all possible positions within this range; then, on the chip placement unit, by identifying the relationship between the current chip position and the ideal position, the matching position of the chip is determined, which can be performed through image recognition or sensor detection technology, and the placement status of the chip can be monitored in real time; finally, the alignment information is compared with the matching position, and the deviation between the actual position and the ideal position is calculated, which can be achieved through simple coordinate difference calculation to obtain the specific component offset of each chip. For example, the matching position of chip A is (100.2, 199.8), and the ideal position is (100, 200), then the component offset is (0.2, -0.2), which will not be repeated here.

[0067] It should be noted that in the present application, the alignment information indicates the ideal position and allowable deviation range specified during the chip placement process to ensure the correct alignment of the chip, which can improve the accuracy and reliability of chip placement; the matching position indicates the correspondence between the actual chip and the ideal chip position in the chip placement unit; the component offset is a numerical value that describes the difference between the actual chip position and the ideal design position, which can provide a basis for chip position correction and ensure the accuracy of the layout.

[0068] In step 103, resource information occupied by a wafer used for computer chip design during chip layout planning is obtained, potential singularities are identified for the resource information, singularity layout information of the chip layout in the chip placement unit domain is obtained, and transient response data for deviation correction response during chip layout testing on the wafer is determined by the singularity layout information and the component offset.

[0069] In specific implementation, obtaining the resource information occupied by the wafer used for computer chip design when performing chip layout planning can be achieved in the following manner, namely: first, clarifying the resource types that need to be paid attention to in chip layout, such as power requirements, heat distribution, material usage and space occupancy, and then using design tools (such as EDA software) to comprehensively analyze the chip design and extract the resource requirements of each chip unit; then, based on the collected data, constructing a resource model of the chip layout, the model includes the resource requirements and mutual relationships of each chip unit, and the resource occupancy in the layout can be displayed through a graphical interface; finally, using a simulation tool, analyzing the resource model, evaluating the resource utilization efficiency in the layout planning, for example, simulating the power requirements and heat distribution of the chip under different workloads, identifying potential resource bottlenecks, and then organizing the analysis results into a report, and obtaining the resource information occupied when performing chip layout planning by reading the analysis result report. In other embodiments, other methods can also be used to determine the resource information occupied when performing chip layout planning, which is not limited here.

[0070] It should be noted that in this application, resource information refers to relevant data such as power supply, thermal management, material usage, space occupancy and interconnection requirements required for each chip unit when planning chip layout, which is used to evaluate the feasibility and performance of the chip design to ensure the rational use of resources during the layout process, avoid potential performance bottlenecks and overheating, and thus optimize the overall performance and stability of the chip.

[0071] In some embodiments, the potential singularity identification of the resource information and obtaining the singularity layout information of the chip layout in the chip placement unit domain may be implemented by the following steps:

[0072] Determine singular point position parameters of chip layout in the chip placement unit domain according to the resource information;

[0073] Determining a layout confidence of a chip layout in a chip placement unit domain by using the singular point position parameters;

[0074] The layout confidence is used to check the chip placement unit domain to obtain singular point layout information of the chip layout in the chip placement unit domain.

[0075] In the specific implementation, first, based on the resource information, the resource requirements and usage of each chip unit in the layout are analyzed to identify the key positions that may cause performance degradation or failure. The singularity position usually refers to the area with excessive resource utilization, concentrated heat or excessive power demand, that is, the singularity position parameters are obtained. For example, if the power demand of a certain area exceeds the maximum carrying capacity of the design, the position is identified as a singularity; then, through data analysis and modeling, the layout confidence of each singularity is calculated. Statistical methods or machine learning techniques can be used to quantify the resource allocation and heat distribution at the singularity to obtain the confidence of the layout. For example, regression analysis is used to calculate the relationship between the resource utilization and the failure rate of a singularity, so as to determine its layout confidence; finally, the calculated layout confidence is applied to the chip placement unit domain, which is checked to identify the area that needs to be improved or adjusted, and the layout confidence of the singularity position is verified through simulation to ensure that each singularity can operate normally within the design specification. No further details are given here.

[0076] It should be noted that, in the present application, the singularity position parameter means identifying the key positions and their related features that cause performance bottlenecks or failures in the chip layout, which helps to reveal potential problems in the chip layout for subsequent optimization; the layout confidence value means an indicator used to quantify the performance stability and reliability in the chip layout area in the chip layout, which helps to evaluate the risk level of the singularity and provide a basis for subsequent decision-making; the singularity layout information is a data set that describes the resource usage and potential risks of key positions in the chip layout, which can provide a data basis for subsequent optimization and design adjustments to ensure the reliability of the layout.

[0077] In some embodiments, determining transient response data for deviation correction response during chip layout testing on a wafer by using the singular point layout information and the component offset can be implemented by the following steps:

[0078] Determine reference position information for performing deviation correction response during chip layout testing on a wafer according to the singular point layout information;

[0079] Determining layout rules for performing deviation correction responses during chip layout testing on a wafer based on the component offset;

[0080] The transient response data for performing deviation correction response is determined by the reference position information and the layout rule.

[0081] In the specific implementation, first, based on the singularity layout information, identify the chip positions that need to be focused on during the test process. These positions are usually areas with high resource utilization and may cause performance problems or failures. Use design tools to extract the coordinate information of these reference positions from the singularity layout information, that is, obtain the reference position information. For example, if the singularity layout information indicates that the distance between chip A and chip B is too close, then the center point coordinates of the two chips will be used as reference position information; then, use component offset to analyze the actual distance and ideal distance between each chip, and formulate corresponding layout rules. The rules should include the allowable deviation range, minimum spacing and other design Limitations ensure that the areas that need to be corrected can be effectively identified during the test process. For example, if the actual distance between component offset display chip C and chip D is less than the design requirement of 5 microns, corresponding layout rules need to be formulated to enforce this distance, which will not be repeated here. Finally, dynamic simulation and simulation are performed in combination with reference position information and layout rules to generate transient response data. Numerical calculation methods, such as finite element analysis (FEA) or time domain analysis, can be used to simulate the behavior of the chip under specific conditions and evaluate its response to deviation correction. For example, simulation software is used to simulate the transient current response of the chip under different load conditions to evaluate its performance changes.

[0082] It should be noted that in this application, the reference position information represents the key chip position and its coordinate data used for deviation correction in the chip layout test; the layout rules represent the design constraints and standards established in the chip layout to ensure performance and reliability; the transient response data is the dynamic behavior data that describes the chip's response to deviation correction under specific conditions, which helps to evaluate and optimize chip performance and improve the stability and reliability of the design.

[0083] In step 104, a continuous failure feature on adjacent bits of a chip in a chip layout is generated based on the netlist connection information of chip functional connections after chip layout of a wafer used for computer chip design, and dynamic response data for deviation correction response during chip layout testing on the wafer is determined based on the continuous failure feature.

[0084] In some embodiments, the following steps may be used to generate continuous failure features on adjacent bits of a chip in a chip layout based on the netlist connection information of chip functional connections after chip layout of a wafer used for computer chip design:

[0085] Determine the layout data of the chip adjacent bits in the chip layout layout after the chip layout is performed on the wafer used for computer chip design;

[0086] Determine the netlist connection information of chip functional connections after chip layout;

[0087] Determine the continuous failure features on adjacent bits of the chip in the chip layout according to the layout annotation data and the netlist connection information.

[0088] In the specific implementation, first, the layout annotation data is extracted from the chip layout, including the geometry, size and relationship between adjacent bits of each chip. By using graphics processing and CAD tools, the connection lines and annotation information between adjacent chips are identified to understand the spatial relationship of each chip in the layout, that is, the layout annotation data is obtained. For example, the location information of each chip and the annotations of their interconnections are extracted using design software. For example, chip A is located at (100, 200) and has the connection characteristics with chip B. Then, the netlist information of the chip functional connection is collected and analyzed. This information includes the electrical connection relationship between the functional units of the chip. By establishing and parsing the netlist, the interconnection between the chips and their functional associations are identified. For example, from the design The software extracts the netlist and identifies that the output of chip A is connected to the input of chip B, and these connections are functionally interdependent. Finally, the extracted layout annotation data is combined with the netlist connection information to analyze the failure mode between adjacent bits. This can be done through methods such as fault tree analysis or electrical simulation to identify features that may cause functional failure between adjacent chips under specific conditions, such as signal interference, overload, etc. In other embodiments, other methods can also be used to determine the continuous failure features on adjacent bits of the chip in the chip layout, which is not limited here. For example, chip A and chip B are placed adjacent to each other at high temperature, and a signal pin of chip A fails, which may cause chip B to fail. At this time, the adjacent relationship is analyzed and the failure features are extracted.

[0089] It should be noted that in the present application, the layout annotation data represents the electronic information describing the geometric features, position and adjacent relationships of the chip in the chip layout layout, which can provide the spatial structure and connection status of the chip layout; the netlist connection information is a data structure that describes the electrical connections and logical relationships between the various functional units of the chip, which can clarify the interactions and dependencies between the chip functional modules; the continuous failure feature represents the feature of functional failure caused by the electrical connections and logical relationships between adjacent chips in the chip layout.

[0090] In some embodiments, determining the dynamic response data for performing deviation correction response during chip layout testing on a wafer according to the continuous failure characteristics can be implemented by the following steps:

[0091] Determine the failure distribution nodes during the chip layout test on the wafer by using the continuous failure characteristics;

[0092] Determining an adjustment configuration amount for a deviation correction response during chip layout testing on a wafer;

[0093] Dynamic response data of a deviation correction response is determined according to the failure distribution nodes and the adjustment configuration amount.

[0094] In the specific implementation, first, based on the identified continuous failure characteristics, fault records related to the chip layout are collected from the test data, including overheating, signal interference, overload, etc., and the fault tree analysis (FTA) or failure mode and effect analysis (FMEA) method is used to identify the root cause of each failure characteristic. In the simulation environment, different working conditions (such as temperature, frequency, voltage, etc.) are set to simulate the working state of the chip, and the nodes where the failure characteristics appear under these conditions are recorded. According to the simulation results, the specific nodes with high failure probability are determined and marked as failure distribution nodes; then, for each failure distribution node, its electrical characteristics (such as voltage, current, power, etc.) under normal working conditions are evaluated and compared with the design specifications, and then the impact of different configuration changes on the failure distribution nodes is analyzed. For example, the power consumption under different voltage conditions is calculated through the voltage-power relationship to identify the possible causes. The configuration that causes thermal failure is then evaluated, and corresponding adjustment configurations are formulated for each failure distribution node, including increasing voltage, optimizing signal paths, adding heat dissipation measures, etc., which will not be elaborated here; finally, a dynamic test plan is designed to clarify the test parameter range and test conditions, such as different temperatures, frequencies, and load conditions. During the test, a data acquisition system (such as an oscilloscope and logic analyzer) is used to monitor the voltage, temperature, signal amplitude, frequency and other parameters of the failure distribution node in real time. The collected data is processed using time domain analysis and frequency domain analysis techniques, and the dynamic response characteristics of the node under different conditions are extracted to identify the difference between the failure and normal states. According to the analysis results, a dynamic response model is constructed to describe the response characteristics of the node to deviation correction under specific conditions, including reaction time, fluctuation range, etc. The dynamic response data of the deviation correction response is output from the model, which is not limited here.

[0095] It should be noted that the failure distribution node in the present application represents a specific location in the chip layout that shows a high risk of failure due to continuous failure characteristics, providing a reference point for subsequent corrections and optimizations; the adjustment configuration amount represents the specific adjustment parameters formulated in the chip layout test to ensure performance and reliability, which helps to optimize the chip operation state and reduce the possibility of failure; the dynamic response data is the real-time behavioral data that describes the chip's response to deviation correction during the test process.

[0096] In step 105, a feedback correction index of a wafer for computer chip design during chip layout testing is determined according to the transient response data and the dynamic response data, and chips on the wafer for computer chip design that fail are strictly filtered according to the feedback correction index.

[0097] In some embodiments, determining the feedback correction index of a wafer for computer chip design during chip layout testing according to the transient response data and the dynamic response data can be implemented by the following steps:

[0098] Determining layout feedback data of a wafer used for computer chip design during chip layout testing through the transient response data;

[0099] Determining the tightening correction characteristics of a wafer used for computer chip design during chip layout testing through the dynamic response data;

[0100] A feedback correction index of the wafer during chip layout testing is determined according to the layout feedback data and the tightened correction feature.

[0101] In the specific implementation, first, the transient response data is extracted from the test records, including the voltage and current fluctuations of each node. The data analysis tools can be used to integrate these data into a structured format, such as an Excel table or a database. Then, the changing trend of the transient response data is analyzed by statistical methods (such as standard deviation, mean, etc.), the mutual influence between chips and potential problem areas are identified, and key performance indicators (such as voltage deviation, transient response time) are selected for extraction to form comprehensive layout feedback data; then, relevant features are extracted from the dynamic response data, that is, the tightening correction features of the wafer during the chip layout test are obtained, such as signal stability, power consumption and temperature change, and then the extracted features are analyzed to identify abnormal behaviors under specific working conditions, such as overheating or signal distortion, and classified. According to the identified abnormal mode, the necessary correction threshold is formulated, such as setting the temperature of a certain node not to exceed a certain value; finally, the layout feedback data and the tightening correction features are comprehensively analyzed to find the correlation between the two. According to the data analysis results, the feedback correction indicators are calculated, such as the required voltage adjustment amount or signal enhancement measures, which can be quantified by establishing a mathematical model, and the calculated feedback correction indicators are compiled into a report, which will not be repeated here.

[0102] It should be noted that the layout feedback data in this application refers to the key performance data that reflects the actual performance of the chip and the mutual influence during the chip layout test; the tightened correction feature describes the corrective measures that need to be taken due to abnormal behavior during the dynamic test of the chip; the feedback correction index represents the quantitative index generated based on the feedback data and the correction feature during the chip layout test.

[0103] In specific implementation, the chips on the wafer used for computer chip design that are strictly filtered out according to the feedback correction index can be implemented in the following manner, namely: first, the collected failure records are analyzed to identify the failure mode and its associated feedback correction index, for example, determine which chips frequently fail under specific voltage, temperature or signal conditions, and then, based on the feedback correction index, set a stricter filtering standard, including setting a threshold, such as the maximum allowable voltage deviation, temperature variation range, etc., to ensure that only chips that meet the standards can pass the filtering; finally, apply the set filtering standard to each chip on the wafer, check the performance data of each chip one by one, if the feedback correction index of a chip exceeds the set threshold, it is marked as a failed chip, and then organize the filtering results to generate a detailed report, including the number of failed chips found in the filtering process, the cause of failure and the related feedback correction index, that is, the chips on the wafer used for computer chip design that are strictly filtered out according to the feedback correction index are completed, which will not be repeated here.

[0104] In addition, in another aspect of the present application, in some embodiments, the present application provides a system for screening wafer test results with stricter correction, referring to Figure 4 , which is a schematic diagram of the structure of a wafer test result tightening correction screening system according to some embodiments of the present application, the wafer test result tightening correction screening system 400 includes: an identification module 401, a processing module 402 and an execution module 403, which are respectively described as follows:

[0105] Identification module 401, in this application, identification module 401 is mainly used to perform chip layout testing on a wafer used for computer chip design, and to identify layout data of a chip layout on the wafer;

[0106] Processing module 402, in the present application, the processing module 402 is mainly used to correct the layout data, obtain the constraint distance of the chip layout in the chip layout layout on the wafer, and determine the component offset between the chips in the chip placement unit domain according to the constraint distance;

[0107] The processing module 402 is further used to obtain resource information occupied by a wafer used for computer chip design when performing chip layout planning, identify potential singular points on the resource information, obtain singular point layout information of the chip layout in the chip placement unit domain, and determine transient response data for deviation correction response during chip layout testing on the wafer through the singular point layout information and the component offset;

[0108] The processing module 402 is further used to generate continuous failure characteristics on adjacent bits of the chip in the chip layout based on the netlist connection information of the chip function connection after the chip layout of the wafer used for computer chip design, and determine the dynamic response data of the deviation correction response during the chip layout test on the wafer according to the continuous failure characteristics;

[0109] Execution module 403, in the present application, execution module 403 is mainly used to determine the feedback correction index of the wafer used for computer chip design during chip layout testing according to the transient response data and the dynamic response data, and to strictly filter the failed chips on the wafer used for computer chip design according to the feedback correction index.

[0110] In addition, the present application also provides a computer device, which includes a memory and a processor, wherein the memory stores codes, and the processor is configured to obtain the codes and execute the above-mentioned method for tightening correction screening of wafer test results.

[0111] In some embodiments, reference Figure 5 , which is a schematic diagram of the structure of a computer device for implementing a method for strictly correcting and screening wafer test results according to some embodiments of the present application. The method for strictly correcting and screening wafer test results in the above embodiments can be performed by Figure 5 The computer device 500 shown in the figure is implemented, and the computer device 500 includes at least one processor 501, a communication bus 502, a memory 503 and at least one communication interface 504.

[0112] Processor 501 may be a general-purpose central processing unit (CPU), or an application-specific integrated circuit (ASIC) or one or more processors for controlling the execution of the tightened correction screening method for wafer test results in the present application.

[0113] The communication bus 502 may be used to transmit information between the above-mentioned components.

[0114] The memory 503 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a disk or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 503 may exist independently and be connected to the processor 501 via the communication bus 502. The memory 503 may also be integrated with the processor 501.

[0115] Among them, the memory 503 is used to store the program code for executing the solution of the present application, and the execution is controlled by the processor 501. The processor 501 is used to execute the program code stored in the memory 503. The program code may include one or more software modules. The method for screening the wafer test results with strict correction in the above embodiment can be implemented by the processor 501 and one or more software modules in the program code in the memory 503.

[0116] The communication interface 504 uses any transceiver or other device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc.

[0117] In a specific implementation, as an embodiment, a computer device may include multiple processors, each of which may be a single-CPU processor or a multi-CPU processor. The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0118] The above-mentioned computer device can be a general-purpose computer device or a special-purpose computer device. In a specific implementation, the computer device can be a desktop computer, a portable computer, a network server, a personal digital assistant (PDA), a mobile phone, a tablet computer, a wireless terminal device, a communication device or an embedded device. The embodiment of the present application does not limit the type of computer device.

[0119] In addition, the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the above-mentioned method for stricter correction screening of wafer test results.

[0120] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0121] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for screening wafer test results with stricter correction, characterized in that: The steps include: Perform chip layout testing on wafers used for computer chip design to identify layout data of chip layouts on the wafers; Correcting and constraining the layout data to obtain a constraint distance of chip layout in a chip layout layout on a wafer, and determining a component offset between chips in a chip placement unit domain according to the constraint distance; Obtaining resource information occupied by a wafer used for computer chip design when performing chip layout planning, identifying potential singular points on the resource information, obtaining singular point layout information of the chip layout in the chip placement unit domain, and determining transient response data for deviation correction response during chip layout testing on the wafer through the singular point layout information and the component offset; Generate continuous failure characteristics on adjacent bits of the chip in the chip layout based on the netlist connection information of the chip functional connection after the chip layout of the wafer used for computer chip design, and determine the dynamic response data of the deviation correction response during the chip layout test on the wafer according to the continuous failure characteristics; A feedback correction index of a wafer for computer chip design during chip layout testing is determined according to the transient response data and the dynamic response data, and chips on the wafer for computer chip design that fail are strictly filtered according to the feedback correction index.

2. The method according to claim 1, characterized in that Correcting and constraining the layout data to obtain the constraint distance of the chip layout in the chip layout layout on the wafer specifically includes: Determine the layout trajectory of the chip in the chip layout layout on the wafer according to the layout data; Determine layout constraint information in the chip layout on the wafer; The layout trajectory is adjusted using the layout constraint information to obtain a constraint distance of the chip layout in the chip layout diagram on the wafer.

3. The method according to claim 1, characterized in that Determining the component offset between chips in the chip placement unit domain according to the constraint distance specifically includes: Determining alignment information of the chip in the chip placement unit by using the constraint distance; determining a matching position of a chip on a chip placement unit; The component offset is determined based on the alignment information and the matching position.

4. The method according to claim 1, characterized in that Identifying potential singular points of the resource information to obtain singular point layout information of the chip layout in the chip placement unit domain specifically includes: Determine singular point position parameters of chip layout in the chip placement unit domain according to the resource information; Determining a layout confidence of a chip layout in a chip placement unit domain by using the singular point position parameters; The layout confidence is used to check the chip placement unit domain to obtain singular point layout information of the chip layout in the chip placement unit domain.

5. The method according to claim 1, characterized in that The transient response data for performing deviation correction response during chip layout testing on a wafer determined by the singular point layout information and the component offset specifically includes: Determine reference position information for performing deviation correction response during chip layout testing on a wafer according to the singular point layout information; Determining layout rules for performing deviation correction responses during chip layout testing on a wafer based on the component offset; The transient response data for performing deviation correction response is determined by the reference position information and the layout rule.

6. The method according to claim 1, characterized in that Determining the feedback correction index of the wafer used for computer chip design during chip layout testing according to the transient response data and the dynamic response data specifically includes: Determining layout feedback data of a wafer used for computer chip design during chip layout testing through the transient response data; Determining the tightening correction characteristics of a wafer used for computer chip design during chip layout testing through the dynamic response data; A feedback correction index of the wafer during chip layout testing is determined according to the layout feedback data and the tightened correction feature.

7. The method according to claim 1, characterized in that The image information is converted into layout data through electronic design automation tools.

8. A system for screening wafer test results with tightened correction, characterized in that: include: An identification module is used to perform chip layout testing on a wafer used for computer chip design and to identify layout data of a chip layout on the wafer; A processing module, used for correcting and constraining the layout data, obtaining a constraint distance of a chip layout in a chip layout on a wafer, and determining a component offset between chips in a chip placement unit domain according to the constraint distance; The processing module is further used to obtain resource information occupied by a wafer used for computer chip design when performing chip layout planning, identify potential singular points on the resource information, obtain singular point layout information of the chip layout in the chip placement unit domain, and determine transient response data for deviation correction response during chip layout testing on the wafer through the singular point layout information and the component offset; The processing module is further used to generate continuous failure characteristics on adjacent bits of the chip in the chip layout based on the netlist connection information of the chip function connection after the chip layout of the wafer used for computer chip design, and determine the dynamic response data for deviation correction response during the chip layout test on the wafer according to the continuous failure characteristics; The execution module is used to determine the feedback correction index of the wafer used for computer chip design during chip layout test according to the transient response data and the dynamic response data, and to strictly filter the failed chips on the wafer used for computer chip design according to the feedback correction index.

9. A computer device, characterized in that: The computer device includes a memory and a processor, wherein the memory stores codes, and the processor is configured to obtain the codes and execute the wafer test result tightening correction screening method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for screening wafer test results with stricter correction according to any one of claims 1 to 7 is implemented.

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