Isolation amplification circuit

Abstract

The invention discloses an isolation amplifying circuit. The isolation amplification circuit comprises a modulation circuit, an isolation circuit and a demodulation circuit. The modulation circuit receives an input signal and a first clock signal and generates a first modulation signal and a second modulation signal according to the first clock signal and the input signal. The isolation amplification circuit receives a second clock signal, a first modulation signal and a second modulation signal, generates a first clock signal according to the second clock signal, generates a first demodulation signal according to the first modulation signal, and generates a second demodulation signal according to the second modulation signal. The demodulation circuit receives the first demodulation signal, the second demodulation signal and the second clock signal, and generates an output signal according to the second clock signal, the first demodulation signal and the second demodulation signal. The second demodulation signal generated according to the second modulation signal in the demodulation circuit and the demodulated first modulation signal are subjected to weighted summation to offset quantization noise generated by the first modulation circuit, and low noise of the isolation amplification circuit is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of isolation amplifier circuits, and in particular to an isolation amplifier circuit. Background Art

[0002] Isolation amplifier circuits are widely used in the field of current and voltage detection. For actual drive systems in the industrial and automotive fields, such as motor drive systems, they usually have two voltage domains - a "high voltage" domain and a "low voltage" domain. The microcontroller or digital signal processor, usually located in the low voltage domain, receives feedback signals (voltage, current, etc.) from the three-phase IGBT power stage and generates digital signals to control the power switch transistors and other high-voltage circuits. It requires reliable electrical isolation between the two voltage domains to isolate the high voltage circuit from the low voltage circuit, ensure that the motor drive system can operate reliably, and prevent damage to expensive circuits by breaking the ground loop between the high and low voltage circuits, and help protect operators from high voltage injuries.

[0003] An isolation amplifier circuit is needed to protect the numerical control circuit. However, when implementing the isolation amplifier function, the isolation amplifier circuit in the prior art often cannot achieve both high bandwidth and fast response and high precision. The precision of the isolation amplifier circuit is mainly affected by the system noise. If the measurement accuracy is to be improved, the response speed will be sacrificed. Summary of the invention

[0004] The present application provides an isolation amplifier circuit, aiming to solve the problems of low signal transmission accuracy and low signal-to-noise ratio of isolation amplifier circuits in the prior art. To achieve the above technical objectives, the present application adopts the following technical solutions:

[0005] According to a first aspect of the present application, an embodiment of the present application provides an isolation amplifier circuit, including: a modulation circuit 10, having an input end receiving an input signal VIN, a control end receiving a first clock signal CLK_rx, a first output end providing a first modulation signal D1_tx, and a second output end providing a second modulation signal D2_tx, wherein the modulation circuit 10 generates a first modulation signal D1_tx and a second modulation signal D2_tx according to the input signal VIN and the first clock signal CLK_rx; an isolation circuit 20, having a first input end receiving the first modulation signal D1_tx, a second input end receiving the second modulation signal D2_tx, a control end receiving the second clock signal, and generating a first clock signal CLK_rx according to the second clock signal CLK_tx, and generating a first demodulation signal D1_tx according to the first modulation signal D1_tx. _rx, generates a second demodulation signal D2_rx according to the second modulation signal D2_tx, wherein the first clock signal CLK_tx has the same frequency and amplitude as the second clock signal CLK_rx, the first demodulation signal D1_rx has the same frequency and amplitude as the first modulation signal D1_tx, and the second demodulation signal D2_rx has the same frequency and amplitude as the second modulation signal D2_tx; and a demodulation circuit 30, having a first input terminal receiving the first demodulation signal D1_rx, a second input terminal receiving the second demodulation signal D2_rx, and a control terminal receiving the second clock signal CLK_tx, the demodulation circuit 30 generates an output signal VOUT according to the second clock signal CLK_tx, the first demodulation signal D1_rx and the second demodulation signal D2_rx, wherein the amplitude of the output signal is greater than the amplitude of the input signal.

[0006] According to a second aspect of the present application, an embodiment of the present application provides an isolation amplifier circuit, including: a modulation circuit 10, having an input end receiving an input signal VIN, a control end receiving a first clock signal CLK_tx, a first output end providing a first modulation signal D1_tx, and a second output end providing a second modulation signal D2_tx, wherein the modulation circuit 10 samples the input signal VIN at the frequency of the first clock signal CLK_tx and modulates it into a first modulation signal D1_tx and a second modulation signal D2_tx; an isolation circuit 20, having a first input end receiving the first modulation signal D1_tx, a second input end receiving the second modulation signal D2_tx, a control end receiving the first clock signal CLK_tx, and generating a first demodulation signal D1_rx according to the first modulation signal D1_tx, and generating a first demodulation signal D1_rx according to the first modulation signal D1_tx. The second modulation signal D2_tx generates a second demodulation signal D2_rx, and the second clock signal is generated according to the first clock signal, wherein the frequency and amplitude of the first clock signal CLK_tx are the same as those of the second clock signal CLK_rx, the frequency and amplitude of the first demodulation signal D1_rx are the same as those of the first modulation signal D1_tx, and the frequency and amplitude of the second demodulation signal D2_rx are the same as those of the second modulation signal D2_tx; and a demodulation circuit 30, having a first input terminal for receiving the first demodulation signal D1_rx, a second input terminal for receiving the second demodulation signal D2_rx, and a control terminal for receiving the second clock signal CLK_tx, and the demodulation circuit 30 generates an output signal VOUT according to the second clock signal CLK_tx, the first demodulation signal D1_rx and the second demodulation signal D2_rx.

[0007] Through one or more of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0008] The present application obtains a second modulation signal through a modulation circuit, and transmits the second modulation signal together with the first modulation signal to a demodulation circuit through an isolation circuit. The isolation circuit generates a second demodulation signal according to the second modulation signal, and generates a first demodulation signal according to the first modulation signal. The demodulation circuit receives the first demodulation signal and the second demodulation signal, and performs weighted summation on the two to offset the quantization noise introduced by the modulation circuit during the modulation process, thereby improving the signal-to-noise ratio during the signal transmission process of the isolation circuit and ensuring the signal transmission accuracy during the high-bandwidth fast response process. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1A A circuit structure schematic diagram of an isolation amplifier circuit 100 according to an embodiment of the present application is provided;

[0011] Figure 1B A circuit structure schematic diagram of an isolation amplifier circuit 100 according to an embodiment of the present application is provided;

[0012] Figure 2 A circuit structure diagram of a modulation circuit 10 according to an embodiment of the present application is given;

[0013] Figure 3A A circuit structure diagram of a first modulation circuit 11 according to an embodiment of the present application is given;

[0014] Figure 3B A schematic diagram of signal waveforms of a first modulation circuit 11 according to an embodiment of the present application is given;

[0015] Figure 4A A circuit structure diagram of a second modulation circuit 12 according to an embodiment of the present application is given;

[0016] Figure 4B A schematic diagram of signal waveforms of the second modulation circuit 12 according to an embodiment of the present application is given;

[0017] Figure 5 A circuit structure diagram of a demodulation circuit 30 according to an embodiment of the present application is given;

[0018] Figure 6 A circuit structure schematic diagram of a demodulation circuit 30 according to another embodiment of the present application is provided;

[0019] Figure 7 A circuit structure diagram of a first demodulation circuit 31 according to an embodiment of the present application is provided;

[0020] Figure 8 A circuit structure diagram of a second demodulation circuit 32 according to an embodiment of the present application is given;

[0021] Fig. 9 A circuit structure schematic diagram of an isolation circuit 20 according to an embodiment of the present application is provided;

[0022] Fig.10 A circuit structure schematic diagram of an isolation amplifier circuit 100 according to another embodiment of the present application is provided;

[0023] Fig.11 A circuit structure schematic diagram of an isolation circuit 20 according to another embodiment of the present application is provided. DETAILED DESCRIPTION

[0024] In the description of the present invention, it should be noted that throughout the specification and claims, the "coupling" used is defined as being directly or indirectly connected in an electrical or non-electrical manner. When an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or one or more intermediate elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there is no intermediate element. Throughout the specification, reference to "one embodiment", "embodiment", "one example" or "example" means that the specific features, structures or characteristics described in conjunction with the embodiment or example are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "one example" or "example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, specific features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes, and the drawings are not necessarily drawn to scale. The same reference numerals indicate the same device. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0025] Figure 1A A circuit structure diagram of an isolated amplifier circuit 100 according to an embodiment of the present application is given. The isolated amplifier circuit 100 includes a modulation circuit 10, an isolation circuit 20 and a demodulation circuit 30. The modulation circuit 10 has an input end for receiving an input signal VIN, a control end for receiving a first clock signal CLK_rx, a first output end for providing a first modulation signal D1_tx, and a second output end for providing a second modulation signal D2_tx. The modulation circuit 10 generates a first modulation signal D1_tx and a second modulation signal D2_tx according to the input signal VIN and the first clock signal CLK_rx. In one embodiment, the first modulation signal D1_tx represents the input signal VIN, and the second modulation signal D2_tx represents the quantization noise generated when the input signal VIN generates the first modulation signal D1_tx. In one embodiment, the input signal VIN can be a square wave or a sine wave with a frequency between 100KHZ-2MHZ. In one embodiment, the frequency range of the first clock signal CLK_rx is between 10MHz-30MHz.

[0026] The isolation circuit 20 has a first input end for receiving a first modulation signal D1_tx, a second input end for receiving a second modulation signal D2_tx, a control end for receiving a second clock signal CLK_tx, and generates a first clock signal CLK_rx according to the second clock signal CLK_tx, generates a first demodulation signal D1_rx according to the first modulation signal D1_tx, and generates a second demodulation signal D2_rx according to the second modulation signal D2_tx, wherein the first clock signal CLK_tx has the same frequency and amplitude as the second clock signal CLK_rx, the first demodulation signal D1_rx has the same frequency and amplitude as the first modulation signal D1_tx, and the second demodulation signal D2_rx has the same frequency and amplitude as the second modulation signal D2_tx.

[0027] The demodulation circuit 30 has a first input terminal for receiving a first demodulation signal D1_rx, a second input terminal for receiving a second demodulation signal D2_rx, and a control terminal for receiving a second clock signal CLK_tx. The demodulation circuit 30 generates an output signal VOUT according to the second clock signal CLK_tx, the first demodulation signal D1_rx and the second demodulation signal D2_rx, wherein the amplitude of the output signal is greater than the amplitude of the input signal.

[0028] Figure 1B The circuit structure diagram of the isolation amplifier circuit according to an embodiment of the present application is given. The isolation circuit 20 includes a first isolation circuit, which has an input end receiving a second clock signal CLK_tx, and an output end providing a first clock signal CLK_rx. The first isolation circuit generates a first clock signal CLK_rx according to the second clock signal CLK_tx. Figure 1B In the illustrated embodiment, the first isolation circuit may include an isolated coupled first receiving circuit RX1 and a first transmitting circuit TX1, wherein the first transmitting circuit TX1 receives the second clock signal CLK_tx and generates differential signals P2 and N2, which are coupled and output to the first receiving circuit RX1, and the first receiving circuit RX1 receives the differential signals P2 and N2 and generates a first clock signal CLK_rx which is output to the modulation circuit 10. The isolation circuit 20 also includes a second isolation circuit having an input terminal for receiving the first modulation signal D1_tx and an output terminal for providing a first demodulation signal D1_rx. The second isolation circuit generates a first demodulation signal D1_rx according to the first modulation signal D1_tx, and outputs the first demodulation signal D1_rx to the first receiving circuit RX1. Figure 1BIn the illustrated embodiment, the second isolation circuit may include an isolated coupled second receiving circuit RX2 and a second transmitting circuit TX2, wherein the second transmitting circuit TX2 receives the first modulated signal D1_tx and generates differential signals P1 and N1, which are coupled and output to the second receiving circuit RX2, and the second receiving circuit RX2 receives the differential signals P1 and N1 and generates a first demodulated signal D1_rx which is output to the demodulation circuit 30. The isolation circuit 20 also includes a third isolation circuit having an input terminal for receiving the second modulated signal D2_tx and an output terminal for providing the second demodulated signal D2_rx. The third isolation circuit generates the second demodulated signal D2_rx according to the second modulated signal D2_tx, and outputs the second demodulated signal D2_rx to the demodulation circuit 30. Figure 1B In the illustrated embodiment, the third isolation circuit may include an isolated coupled third receiving circuit RX3 and a third transmitting circuit TX3, wherein the third transmitting circuit TX3 receives the second modulation signal D2_tx and generates differential signals P3 and N3, which are coupled and output to the third receiving circuit RX3, and the third receiving circuit RX3 receives the differential signals P3 and N3 and generates a second demodulation signal D2_rx which is output to the demodulation circuit 30.

[0029] The modulation circuit 10 generates a second modulation signal D2_tx according to the quantization noise signal Vqn_tx. The quantization noise is the noise generated in the process of the modulation circuit 10 converting the analog input signal VIN into the digital first modulation signal D1_tx. In one embodiment, the second modulation signal D2_tx is a pulse width modulation signal. The isolation circuit 20 generates a second demodulation signal D2_rx according to the second modulation signal D2_tx, and the second demodulation signal D2_rx is also a pulse width modulation signal. The demodulation circuit 30 receives the second demodulation signal D2_rx, and generates an output signal VOUT according to the second demodulation signal D2_rx and the first demodulation signal D1_rx to offset the influence of the quantization noise generated in the modulation circuit 10.

[0030] Figure 2A circuit structure diagram of a modulation circuit 10 according to an embodiment of the present application is given. The modulation circuit 10 includes a first modulation circuit 11 and a second modulation circuit 12. The first modulation circuit 11 has an input end for receiving an input signal VIN, a control end for receiving a first clock signal CLK_rx, a first output end for providing a first modulation signal D1_tx, and a second output end for providing a quantization noise signal Vqn_tx. The first modulation circuit 11 generates a first modulation signal D1_tx and a quantization noise signal Vqn_tx according to the input signal VIN under the control of the first clock signal CLK_rx. Among them, the quantization noise signal Vqn_tx represents the noise caused by the error introduced by the quantization process when the analog signal (input signal VIN) is converted into a discrete digital signal (first modulation signal D1_tx). The second modulation circuit 12 has an input end for receiving a quantization noise signal Vqn_tx, a control end for receiving a first clock signal CLK_rx, and a first output end for providing a second modulation signal D2_tx. The second modulation circuit 12 generates a second modulation signal D2_tx according to the quantization noise signal Vqn_tx under the control of the first clock signal CLK_rx. In one embodiment, the first modulation circuit 11 includes a delta-sigma modulation circuit (SDM, sigma-delta modulator), which can be a continuous delta-sigma modulation circuit or a discrete delta-sigma modulation circuit. In one embodiment, the first modulation circuit 11 can be a second-order 1-bit feedforward SDM. It should be noted that the SDM modulator is only an example, and any circuit structure that can generate a first modulation signal D1_tx and a quantization noise signal Vqn_tx according to the input signal VIN under the control of the first clock signal CLK_rx is included in the present application. In one embodiment, the second modulation circuit 12 may be a pulse width modulation circuit (PWM, Pulse Width Modulator), wherein the pulse width of the second modulation signal D2_tx represents the quantization noise signal Vqn_tx. It should be noted that the pulse width modulation circuit is only an example, and any circuit structure that can generate the second modulation signal D2_tx according to the quantization noise signal Vqn_tx under the control of the first clock signal CLK_rx is included in the present application.

[0031] Figure 3AA circuit structure diagram of a first modulation circuit 11 according to an embodiment of the present application is given. The first modulation circuit 11 includes a first integration circuit 111, a second integration circuit 112, a first addition circuit 113 and a first operation circuit 114. The first integration circuit 111 has a first input terminal for receiving an input signal VIN, a second input terminal for receiving a first modulation signal D1_tx, and performs a weighted integration calculation on the input signal VIN and the first modulation signal D1_tx to generate a first conversion signal TX1. The second integration circuit 112 has an input terminal for receiving the first conversion signal TX1, and performs an integration operation on the first conversion signal TX1 to generate a quantization noise signal Vqn_tx. The first addition circuit 113 has a first input terminal for receiving a quantization noise signal Vqn_tx, a second input terminal for receiving the first conversion signal TX1, and a third input terminal for receiving an input signal VIN, and performs a weighted sum operation on the quantization noise signal Vqn_tx, the first conversion signal TX1 and the input signal VIN to generate a second conversion signal TX2. The first operation circuit 114 has an input terminal for receiving the second conversion signal TX2 , and generates a first modulation signal D1_tx according to the second conversion signal TX2 .

[0032] exist Figure 3A In the embodiment shown, the first modulation circuit 11 is a second-order 1-bit feedforward Sigma-Delta modulator. The first integration circuit 111 samples the input voltage VIN at a sampling frequency F, and weighted sums the sampled voltage and the first modulation signal D1_tx. The weighted summation refers to multiplying the summation object by a corresponding weight coefficient and then adding the respective products to obtain the sum. In this embodiment, the sampled voltage is multiplied by a coefficient and the product is multiplied by a coefficient. The first modulation signal D1_tx is multiplied by a coefficient and then added to obtain the summation result. The summation result is delayed and integrated to generate the first conversion signal TX1. The second integration circuit 112 integrates the first conversion signal TX1 to generate a quantization noise signal Vqn_tx. The first addition circuit 113 performs a weighted summation operation on the quantization noise signal Vqn_tx, the first conversion signal TX1 and the input signal VIN to generate a second conversion signal TX2. The first operation circuit 114 generates the first modulation signal D1_tx according to the second conversion signal TX2.

[0033] exist Figure 3A In the illustrated embodiment, the transfer function of the first modulated signal D1_tx in the z-domain is as shown in the following equation (1):

[0034] D1_tx(z)=VIN(z)+E(z)·(1-z -1 ) 2 (1)

[0035] Where D1_tx(z) is the first modulated signal, and E(z) is the quantization noise contributed by a 1-bit quantizer. The working principle of a 1-bit quantizer is to use oversampling and noise shaping techniques to improve the conversion accuracy. Ideally, the bandwidth quantization noise power of a second-order 1-bit SDM is Where OSR is the oversampling rate, which is equal to half of the sampling frequency divided by the signal bandwidth. rms is the root mean square value of the quantization noise. When the oversampling rate is fixed, the theoretically obtained quantization noise limits the signal to interference plus noise ratio (SNR) performance of the structure. When the sampling frequency is fixed, as the frequency range of the input signal VIN increases, the oversampling rate decreases, and the signal to noise ratio gradually decreases. In the embodiment of FIG3 , the quantization noise is provided by the output end of the second integrator circuit 112, that is, the quantization noise signal Vqn_tx, and its z-domain transfer function is shown in the following formula (2):

[0036] V qn_tx (z)=-z -2 E(z) (2)

[0037] It can be seen from the above formula that the quantization noise signal Vqn_tx is the delay of two time units of the quantization noise E(z) (the exponential value of z represents the degree of delay, -1 power is one time unit delay, -2 power is two time unit delay), which can represent the quantization noise in the first modulation circuit 11 when the input signal VIN generates the first modulation signal D1_tx.

[0038] Figure 3B A schematic diagram of the signal waveform of the first modulation circuit 11 according to an embodiment of the present application is given. Figure 3A The structure of the first modulation circuit 11 shown in FIG. Figure 3B The waveforms of the signals in FIG. 1 are used to illustrate the waveforms of the signals in FIG. 1 . Under the control of the first clock signal CLK_tx, the input signal VIN is modulated into the first modulation signal D1_tx. During the modulation process, the influence of the quantization noise signal Vqn_tx is superimposed. It should be noted that: Figure 3B The waveform change of the quantization noise signal Vqn_tx shown in FIG. 1 is for illustration only and is only used to indicate that the quantization noise signal has a random distribution in different clock cycles and has no regularity.

[0039] exist Figure 3AIn the illustrated embodiment, the first operation circuit 114 is a dynamic zero-crossing comparator, which periodically compares the second conversion signal TX2 with the reference ground voltage GND according to the frequency of the first clock signal CLK_rx. When the second conversion signal TX2 is greater than the reference ground voltage GND, the first modulation signal D1_tx is output as a logic high level, otherwise the first modulation signal D1_tx is output as a logic low level.

[0040] Figure 4A A circuit structure diagram of a second modulation circuit 12 according to an embodiment of the present application is given. A differential pair of quantization noise signals Vqn_tx and -Vqn_tx are input into the second modulation circuit 12, and a differential pair of first clock signals CLK_rxP and CLK_rxN are input into the second modulation circuit 12. Taking a circuit in which a quantization noise signal Vqn_tx and a first clock signal CLK_rxP are input into one side as an example, the first switch S1 and the second switch S2 are turned on or off under the control of the second modulation signal D2_tx. When the first switch S1 is turned on, the second end of the resistor Rf1p receives the first reference voltage -Vref1, and when the second switch S2 is turned on, the second end of the resistor Rf1p receives the second reference voltage +Vref1. In one embodiment, when the second modulation signal D2_tx is at a logic high level, the first switch S1 is turned off and the second switch S2 is turned on. When the second modulation signal D2_tx is at a logic low level, the first switch S1 is turned on and the second switch S2 is turned off. In one embodiment, the first reference voltage -Vref1 and the second reference voltage +Vref1 have the same absolute value and opposite polarities.

[0041] exist Figure 4A In the embodiment shown, one side of the second modulation circuit 12 with differential input is used as an example for explanation. The integrator composed of the resistor Rcp, the capacitor C1P and the operational amplifier provides a triangular wave signal to the subsequent comparison circuit at the input end of the operational amplifier. The triangular wave is used as the carrier of the second modulation circuit 12 to realize pulse width modulation. When the operational amplifier is in a stable state, the output of the integrator must be bounded. Therefore, from the perspective of cycle balance, the average current on the capacitor C1P is zero. According to the Thevenin theorem, the output duty cycle of the second modulation signal D2_tx is derived, and its calculation formula is: The bandwidth of the second modulation signal D2_tx is determined by the resistors Rcp, Rf1p, the capacitor C1P and the carrier frequency, and exhibits a first-order low-pass characteristic. Since the quantization noise does not need to be completely transmitted to the demodulation side, the bandwidth of the second modulation signal D2_tx only needs to be greater than the signal bandwidth. In one embodiment, the bandwidth of the second modulation signal D2_tx is 1 MHz. In some other embodiments, the second modulation circuit 12 may also be a circuit with non-differential input, for example, it may only include Figure 4AOne side of the circuit shown in FIG. 1 only includes a resistor Rcp, a resistor Rs1p, a capacitor C1P, an operational amplifier, a comparator, and a first switch S1 and a second switch S2, and its working principle is the same as Figure 4A The working principle of the differential single-side in the second modulation circuit 12 shown is similar and will not be described in detail here.

[0042] Figure 4B A schematic diagram of the signal waveform of the second modulation circuit 12 according to an embodiment of the present application is given. Figure 4A The structure of the second modulation circuit 12 shown in FIG. Figure 4B The waveforms of the signals in are described. Under the control of the clock signal CLK_rx, the quantization noise signal VIN is modulated into the second modulation signal D2_tx, and the second modulation circuit 12 is a pulse width modulation circuit, wherein the pulse width of the second modulation signal D2_tx represents the quantization noise signal Vqn_tx. It should be noted that, Figure 4B The waveform change of the quantization noise signal Vqn_tx shown in FIG. 1 is only for illustration. In practical applications, the quantization noise signal has random value fluctuations.

[0043] In some embodiments, the second modulation circuit 12 may include a first-order 1-bit SDM modulator or a first-order pulse width modulator. A first-order pulse width modulator has better noise performance. In a first-order pulse width modulator, the information of the signal is encoded into the time domain. Ideally, PWM does not contribute to quantization noise, and using PWM to transfer quantization noise can obtain a better signal-to-noise ratio.

[0044] Figure 5 A circuit structure diagram of a demodulation circuit 30 according to an embodiment of the present application is given. The demodulation circuit 30 includes a first demodulation circuit 31 and a second demodulation circuit 32. The first demodulation circuit 31 has an input end for receiving a second demodulation signal D2_rx, and generates a demodulation quantization noise signal Vqn_rx according to the second demodulation signal D2_rx. The second demodulation circuit 32 has a first input end for receiving a first demodulation signal D1_rx, a second input end for receiving a demodulation quantization noise signal Vqn_rx, and a third input end for receiving a second clock signal CLK_tx. The second demodulation circuit 32 generates an output signal VOUT according to the second clock signal CLK_tx, the first demodulation signal D1_rx and the demodulation quantization noise signal Vqn_rx. In one embodiment, the first demodulation signal D1_rx and the demodulation quantization noise signal Vqn_rx are weightedly summed to generate an output signal VOUT. It should be noted that

[0045] Figure 5 The demodulation circuit 30 provided is only an example, and any circuit structure that can generate a demodulated quantization noise signal Vqn_rx according to the second demodulation signal D2_rx is included in the present application.

[0046] Figure 6 A circuit structure diagram of a demodulation circuit 30 according to another embodiment of the present application is given. Figure 5 In the illustrated embodiment, the first demodulation circuit 31 has an input terminal for receiving the second demodulation signal D2_rx, and generates a demodulation quantization noise signal Vqn_rx according to the second demodulation signal D2_rx. Figure 5 The first demodulation circuit 31 does not receive the second clock signal CLK_tx, and its timing control is only implemented according to the timing information of the second demodulation signal D2_rx. Figure 6 In the illustrated embodiment, the first demodulation circuit 31 has an input terminal for receiving the second demodulation signal D2_rx and the second clock signal CLK_tx, and generates a demodulated quantization noise signal Vqn_rx according to the second demodulation signal D2_rx and the second clock signal CLK_tx. The second demodulation circuit 32 has a first input terminal for receiving the first demodulation signal D1_rx, a second input terminal for receiving the demodulation quantization noise signal Vqn_rx, and a third input terminal for receiving the second clock signal CLK_tx. The second demodulation circuit 32 generates an output signal VOUT according to the second clock signal CLK_tx, the first demodulation signal D1_rx and the demodulation quantization noise signal Vqn_rx. It should be noted that any circuit structure that can generate a demodulated quantization noise signal Vqn_rx according to the second demodulation signal D2_rx under the control of the second clock signal CLK_tx is included in the present application.

[0047] Figure 7 A circuit structure diagram of a first demodulation circuit 31 according to an embodiment of the present application is given. The first demodulation circuit 31 includes a fifth switch S5, a sixth switch S6, a fourth resistor R4, a sixth operation circuit 311, a second capacitor C2, a sampling and holding circuit 312, a seventh operation circuit 313 and a fifth resistor R5.

[0048] The fifth switch S5 has a first end for receiving a fourth reference voltage -Vref2, and a third end for receiving a second demodulated signal D2_rx. The sixth switch S6 has a first end for receiving a third reference voltage +Vref2, and a third end for receiving a second demodulated signal D2_rx. The fourth resistor R4 has a first end coupled to the second end of the fifth switch S5 and the second end of the sixth switch S6. The sixth operation circuit 311 has a first input end coupled to the second end of the fourth resistor R4, a second input end coupled to the reference ground, and an output end for providing a sixth conversion signal TX6. The second capacitor C2 has a first end coupled to the first input end of the sixth operation circuit 311, and a second end coupled to the output end of the sixth operation circuit 311. The sampling and holding circuit 312 has a first input end for receiving the sixth conversion signal TX6, and a second input end for receiving the second demodulated signal D2_rx, and generates a seventh conversion signal TX7 according to the sixth conversion signal TX6 and the second demodulated signal D2_rx. The seventh operation circuit 313 has an input terminal for receiving the seventh conversion signal TX7, and generates a demodulated quantization noise signal Vqn_rx according to the seventh conversion signal TX7. The fifth resistor R5 has a first terminal for receiving the demodulated quantization noise signal Vqn_rx, and a second terminal coupled to the first input terminal of the sixth operation circuit 311. The fifth switch S5 and the sixth switch S6 are turned on or off under the control of the second demodulation signal D2_rx. When the fifth switch S5 is turned on, the first terminal of the fourth resistor R4 receives the fourth reference voltage -Vref2, and when the sixth switch S6 is turned on, the first terminal of the fourth resistor R4 receives the third reference voltage +Vref2. In one embodiment, when the second demodulation signal D2_rx is at a logic high level, the fifth switch S5 is turned off and the sixth switch S6 is turned on. When the second demodulation signal D2_rx is at a logic low level, the fifth switch S5 is turned on and the sixth switch S6 is turned off.

[0049] exist Figure 7 In the embodiment shown, the first demodulation circuit 31 is used for pulse width demodulation to restore the demodulated quantization noise signal Vqn_rx and output it to the second demodulation circuit 32. The voltage of the demodulated quantization noise signal Vqn_rx is And it presents a first-order low-pass characteristic. The sampling and holding circuit 312 can generate a notch at the carrier frequency to suppress the interference signal near the carrier frequency. According to the calculation formula of the second modulation circuit 12, Finally, it is derived It can be seen that when the resistance and reference voltage are equally matched, V qn_rx =V qn_tx .

[0050] In one embodiment, the first demodulation circuit 31 exhibits a low-pass characteristic of PWM, and the cancellation effect of the part higher than the PWM bandwidth is weakened. In order to suppress high-frequency noise, a low-pass filter can be added in the later stage to further filter out the high-frequency noise to obtain better noise performance.

[0051] Figure 8 A circuit structure diagram of a second demodulation circuit 32 according to an embodiment of the present application is given. The second demodulation circuit 32 includes a third switch S3, a fourth switch S4, a third integration circuit 321, a fourth operation circuit 323, a fourth integration circuit 322, a fifth operation circuit 324, and a second addition circuit 325.

[0052] The third switch S3 has a first end, a second end and a third end, the first end receives the third reference voltage +Vref2, the third end receives the first demodulation signal D1_rx, and the third switch is turned on or off under the control of the first demodulation signal D1_rx. The fourth switch S4 has a first end, a second end and a third end, the first end receives the fourth reference voltage -Vref2, the third end receives the first demodulation signal D1_rx, and the fourth switch S4 is turned on or off under the control of the first demodulation signal. The fourth operation circuit 323 has an input end to receive the output signal VOUT, and generates a third conversion signal TX3 according to the output signal VOUT. The third integration circuit 321 has a first input end, a second input end and an output end, the first input end is coupled to the second end of the third switch S3 and the second end of the fourth switch S4, and the second input end receives the third conversion signal TX3. The third switch S3 and the fourth switch S4 are turned on or off under the control of the first demodulation signal D1_rx. When the third switch S3 is turned on, the first input terminal of the third integration circuit 321 receives the third reference voltage +Vref2. When the fourth switch S4 is turned on, the first input terminal of the third integration circuit 321 receives the fourth reference voltage -Vref2. The third integration circuit 321 performs a weighted integration operation based on the third reference voltage and the third conversion signal TX3 to generate a fourth conversion signal TX4, or performs a weighted integration operation based on the third reference voltage and the third conversion signal TX3 to generate a fourth conversion signal TX4. The fourth integration circuit 322 has a first input terminal for receiving the fourth conversion signal TX4, a second input terminal for receiving the third conversion signal TX3, and performs a weighted integration operation based on the fourth conversion signal TX4 and the third conversion signal TX3 to generate a fifth conversion signal TX5. The fifth operation circuit 324 has an input terminal for receiving the demodulated quantization noise signal Vqn_rx, and generates a second noise signal Vqn2 based on the demodulated quantization noise signal Vqn_rx. The second adding circuit 325 has a first input terminal for receiving the fifth conversion signal TX5 and a second input terminal for receiving the second noise signal Vqn2 , and performs a weighted sum operation on the fifth conversion signal TX5 and the second noise signal Vqn2 to generate an output signal VOUT.

[0053] In one embodiment, when the first demodulation signal D1_rx is at a logic low level, the third switch S3 is turned off and the fourth switch S4 is turned on. When the first demodulation signal D1_rx is at a logic high level, the third switch S3 is turned on and the fourth switch S4 is turned off.

[0054] exist Figure 8 In the illustrated embodiment, the second demodulation circuit 32 converts the digital first demodulation signal D1_rx into an analog output signal VOUT, and simultaneously implements weighted cancellation of the quantization noise generated by the first modulation circuit 10. The output signal VOUT is expressed in the z domain as follows (3):

[0055]

[0056] Where D(z) = 10-15z -1 +6z -2

[0057] Each operation circuit, integration circuit and addition circuit in the first demodulation circuit 31 and the second demodulation circuit 32 needs to perform operations according to the frequency of the first clock signal. -1 " indicates a delay of one time period, "z -2 " indicates a delay of two time periods, and the setting of the time period is related to the frequency period of the clock signal.

[0058] In summary, combining formulas (1), (2), and (3), we can derive the expression of the output signal VOUT as:

[0059]

[0060] Fig. 9 A schematic diagram of the circuit structure of an isolation circuit 20 according to an embodiment of the present application is given. The isolation circuit 20 includes a first isolation circuit 21, a second isolation circuit 22 and a third isolation circuit 23.

[0061] The first isolation circuit 21 has an input end for receiving the second clock signal CLK_tx, and an output end for providing the first clock signal CLK_rx. The first isolation circuit 21 generates the first clock signal CLK_rx according to the second clock signal CLK_tx. The second isolation circuit 22 has an input end for receiving the first modulation signal D1_tx, and an output end for providing the first demodulation signal D1_rx. The second isolation circuit 22 generates the first demodulation signal D1_rx according to the first modulation signal D1_tx. The third isolation circuit 23 has an input end for receiving the second modulation signal D2_tx, and an output end for providing the second demodulation signal D2_rx. The third isolation circuit 23 generates the second demodulation signal D2_rx according to the second modulation signal D2_tx.

[0062] exist Fig. 9In the illustrated embodiment, the first isolation circuit 21 includes a first capacitor C1, the second isolation circuit 22 includes a second capacitor C2, and the third isolation circuit 23 includes a third capacitor C3. In some other embodiments, the first isolation circuit 21 may include N capacitors connected in series, where N is an integer greater than or equal to 2.

[0063] Fig.10 A circuit structure diagram of an isolation amplifier circuit 100 according to another embodiment of the present application is given. The modulation circuit 10 has an input end receiving an input signal VIN, a control end receiving a first clock signal CLK_tx, a first output end providing a first modulation signal D1_tx, and a second output end providing a second modulation signal D2_tx. The modulation circuit 10 samples the input signal VIN at the frequency of the first clock signal CLK_tx and modulates it into the first modulation signal D1_tx and the second modulation signal D2_tx. Fig.10 In the embodiment shown, the first clock signal CLK_tx is generated by an oscillator. The isolation circuit 20 has a first input terminal for receiving the first modulation signal D1_tx, a second input terminal for receiving the second modulation signal D2_tx, a control terminal for receiving the first clock signal CLK_tx, and generates a first demodulation signal D1_rx according to the first modulation signal D1_tx, generates a second demodulation signal D2_rx according to the second modulation signal D2_tx, and generates a second clock signal CLK_rx according to the first clock signal CLK_tx, wherein the first clock signal CLK_tx has the same frequency and amplitude as the second clock signal CLK_rx, the first demodulation signal D1_rx has the same frequency and amplitude as the first modulation signal D1_tx, and the second demodulation signal D2_rx has the same frequency and amplitude as the second modulation signal D2_tx. The demodulation circuit 30 has a first input terminal receiving the first demodulation signal D1_rx, a second input terminal receiving the second demodulation signal D2_rx, and a control terminal receiving the second clock signal CLK_rx. The demodulation circuit 30 generates an output signal VOUT according to the second clock signal CLK_rx, the first demodulation signal D1_rx and the second demodulation signal D2_rx.

[0064] Fig.11A circuit structure schematic diagram of an isolation circuit 20 according to another embodiment of the present application is given. The isolation circuit 20 includes a first isolation circuit 21, a second isolation circuit 22 and a third isolation circuit 23. The first isolation circuit 21 has an input end for receiving a first clock signal CLK_tx, and an output end for providing a second clock signal CLK_rx. The first isolation circuit 21 generates a second clock signal CLK_rx according to the first clock signal CLK_tx. The second isolation circuit 22 has an input end for receiving a first modulation signal D1_tx, and an output end for providing a first demodulation signal D1_rx. The second isolation circuit 22 generates a first demodulation signal D1_rx according to the first modulation signal D1_tx. The third isolation circuit 23 has an input end for receiving a second modulation signal D2_tx, and an output end for providing a second demodulation signal D2_rx. The third isolation circuit 23 generates a second demodulation signal D2_rx according to the second modulation signal D2_tx.

[0065] exist Fig.11 In the illustrated embodiment, the first isolation circuit 21 includes a first capacitor C1 , the second isolation circuit 22 includes a second capacitor C2 , and the third isolation circuit 23 includes a third capacitor C3 .

[0066] Although the present invention has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in a variety of forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. An isolation amplifier circuit, comprising: A modulation circuit, having an input end for receiving an input signal, a control end for receiving a first clock signal, a first output end for providing a first modulation signal, and a second output end for providing a second modulation signal, wherein the modulation circuit generates the first modulation signal and the second modulation signal according to the input signal and the first clock signal; An isolation circuit, wherein a first input terminal receives the first modulation signal, a second input terminal receives the second modulation signal, a control terminal receives a second clock signal, and generates a first clock signal according to the second clock signal, generates a first demodulation signal according to the first modulation signal, and generates a second demodulation signal according to the second modulation signal, wherein the first clock signal has the same frequency and amplitude as the second clock signal, the first demodulation signal has the same frequency and amplitude as the first modulation signal, and the second demodulation signal has the same frequency and amplitude as the second modulation signal; as well as A demodulation circuit has a first input terminal for receiving the first demodulation signal, a second input terminal for receiving the second demodulation signal, and a control terminal for receiving a second clock signal. The demodulation circuit generates an output signal according to the second clock signal, the first demodulation signal and the second demodulation signal, wherein the amplitude of the output signal is greater than the amplitude of the input signal. 2 . The isolation amplifier circuit according to claim 1 , wherein the first modulation signal represents the input signal, and the second modulation signal represents the quantization noise generated when the input signal generates the first modulation signal.

3. The isolation amplifier circuit according to claim 1, wherein the input signal is a square wave or a sine wave with a frequency between 100KHZ and 2MHZ. 4 . The isolation amplifier circuit according to claim 1 , wherein a frequency range of the first clock signal CLKtx is between 10 MHz and 30 MHz.

5. The isolation amplifier circuit according to claim 1, wherein the modulation circuit comprises: A first modulation circuit, having an input end for receiving an input signal, a control end for receiving a first clock signal, a first output end for providing a first modulation signal, and a second output end for providing a quantization noise signal, wherein the first modulation circuit generates a first modulation signal and a quantization noise signal according to the input signal under the control of the first clock signal; as well as The second modulation circuit has an input end for receiving a quantization noise signal, a control end for receiving a first clock signal, and an output end for providing a second modulation signal. The second modulation circuit generates the second modulation signal according to the quantization noise signal under the control of the first clock signal. 6 . The isolation amplifier circuit according to claim 5 , wherein the first modulation circuit 11 comprises a delta-sigma modulation circuit. 7 . The isolation amplifier circuit according to claim 5 , wherein the second modulation circuit 12 comprises a pulse width modulation circuit, wherein a pulse width of the second modulation signal represents a quantization noise signal.

8. The isolation amplifier circuit according to claim 1, wherein the demodulation circuit comprises: A first demodulation circuit has an input terminal for receiving the second demodulation signal and generating a demodulated quantization noise signal according to the second demodulation signal; as well as The second demodulation circuit has a first input terminal for receiving the first demodulation signal, a second input terminal for receiving a demodulation quantization noise signal, and a third input terminal for receiving a second clock signal. The second demodulation circuit generates the output signal according to the second clock signal, the first demodulation signal and the demodulation quantization noise signal.

9. The isolation amplifier circuit according to claim 1, wherein the demodulation circuit comprises: A first demodulation circuit has an input terminal for receiving the second demodulation signal and a second clock signal, and generates a demodulated quantization noise signal according to the second demodulation signal and the second clock signal; as well as The second demodulation circuit has a first input terminal for receiving the first demodulation signal, a second input terminal for receiving a demodulation quantization noise signal, and a third input terminal for receiving a second clock signal. The second demodulation circuit generates the output signal according to the second clock signal, the first demodulation signal and the demodulation quantization noise signal. 10 . The isolation amplifier circuit according to claim 8 , wherein the output signal is generated by weighted summing the first demodulated signal and the demodulated quantization noise signal.

11. The isolation amplifier circuit according to claim 1, wherein the isolation circuit comprises: A first isolation circuit has an input end for receiving a second clock signal and an output end for providing a first clock signal, wherein the first isolation circuit generates the first clock signal according to the second clock signal; a second isolation circuit, having an input end for receiving a first modulation signal and an output end for providing a first demodulation signal, wherein the second isolation circuit generates a first demodulation signal according to the first modulation signal; as well as The third isolation circuit has an input end for receiving the second modulation signal and an output end for providing the second demodulation signal. The third isolation circuit generates a second demodulation signal according to the second modulation signal.

12. An isolation amplifier circuit, comprising: A modulation circuit, having an input end for receiving an input signal, a control end for receiving a first clock signal, a first output end for providing a first modulation signal, and a second output end for providing a second modulation signal, wherein the modulation circuit samples the input signal at a frequency of the first clock signal and modulates the input signal into the first modulation signal and the second modulation signal; An isolation circuit, wherein the first input terminal receives the first modulation signal, the second input terminal receives the second modulation signal, the control terminal receives a first clock signal, and generates a first demodulation signal according to the first modulation signal, generates a second demodulation signal according to the second modulation signal, and generates a second clock signal according to the first clock signal, wherein the first clock signal has the same frequency and amplitude as the second clock signal, the first demodulation signal has the same frequency and amplitude as the first modulation signal, and the second demodulation signal has the same frequency and amplitude as the second modulation signal; as well as The demodulation circuit has a first input terminal for receiving the first demodulation signal, a second input terminal for receiving the second demodulation signal, and a control terminal for receiving a second clock signal. The demodulation circuit generates an output signal according to the second clock signal, the first demodulation signal and the second demodulation signal.

13. The isolation amplifier circuit according to claim 12, wherein the modulation circuit comprises: A first modulation circuit, having an input end for receiving an input signal, a control end for receiving a first clock signal, a first output end for providing a first modulation signal, and a second output end for providing a quantization noise signal, wherein the first modulation circuit generates a first modulation signal and a quantization noise signal according to the input signal under the control of the first clock signal; as well as The second modulation circuit has an input end for receiving a quantization noise signal, a control end for receiving a first clock signal, and an output end for providing a second modulation signal. The second modulation circuit generates the second modulation signal according to the quantization noise signal under the control of the first clock signal.

14. The isolation amplifier circuit according to claim 12, wherein the isolation circuit comprises: A first isolation circuit has an input end for receiving a first clock signal and an output end for providing a second clock signal, wherein the first isolation circuit generates the second clock signal according to the first clock signal; a second isolation circuit, having an input end for receiving a first modulation signal and an output end for providing a first demodulation signal, wherein the second isolation circuit generates a first demodulation signal according to the first modulation signal; as well as The third isolation circuit has an input end for receiving the second modulation signal and an output end for providing the second demodulation signal. The third isolation circuit generates a second demodulation signal according to the second modulation signal.

15. The isolation amplifier circuit according to claim 12, wherein the demodulation circuit comprises: A first demodulation circuit has an input terminal for receiving the second demodulation signal and generating a demodulated quantization noise signal according to the second demodulation signal; as well as The second demodulation circuit has a first input terminal for receiving the first demodulation signal, a second input terminal for receiving a demodulation quantization noise signal, and a third input terminal for receiving a second clock signal. The second demodulation circuit generates the output signal according to the second clock signal, the first demodulation signal and the demodulation quantization noise signal.

16. The isolation amplifier circuit according to claim 14, characterized in that: The first isolation circuit includes a first capacitor, the second isolation circuit includes a second capacitor, and the third isolation circuit includes a third capacitor.

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