Radio frequency switch

Abstract

According to the radio frequency switch, parallel inductors are added in a traditional circuit for matching, a low-Ron structure can be adopted, low insertion loss and high isolation degree of the radio frequency switch are achieved, the number of switch tubes is increased by additionally arranging the inductors compared with a traditional circuit, and the switch area is reduced.

Description

Technical Field

[0001] The invention relates to a radio frequency switch and belongs to the field of microwave monolithic integrated circuits. Background Art

[0002] RF switches are important components of transceiver modules in wireless communication systems. Their main function is to shut down and switch signals. They are widely used in phased array communication systems, digitally controlled attenuators, and phase shifters. GaAs PHEMT is a high electron mobility transistor and an important control element widely used in fields such as communication and measurement. By using multiple GaAs PHEMTs to design circuit topologies, RF switches with low loss, high isolation, small size, high reliability, and simple control can be manufactured. In traditional RF switch design, the isolation of the switch is usually improved by increasing the number of parallel switches, but this design method will lead to a deterioration in insertion loss and an increase in switch area. Summary of the invention

[0003] The present invention provides a radio frequency switch, which solves the problem disclosed in the background technology.

[0004] According to one aspect of the present disclosure, there is provided a radio frequency switch, comprising a first transistor, a second transistor, a third transistor, a fourth transistor and an inductor; The gate of the first transistor is connected to the first forward control signal, the drain of the first transistor is connected to the RF common port, and the source of the first transistor is respectively connected to the first RF output port, the drain of the second transistor and one end of the inductor; The gate of the second transistor is connected to the second forward control signal, and the source of the second transistor is connected to the power supply and the ground respectively; The gate of the third transistor is connected to the second forward control signal, the drain of the third transistor is connected to the RF common port, and the source of the third transistor is respectively connected to the second RF output port, the drain of the fourth transistor and the other end of the inductor; The gate of the fourth transistor is connected to the first forward control signal, and the source of the fourth transistor is connected to the power supply and the ground respectively.

[0005] In some embodiments of the present disclosure, a logic circuit is also included, which outputs a second forward control signal and a first forward control signal; the logic circuit includes a first inverter, a second inverter and a third inverter, the input ends of the first inverter and the second inverter are both externally connected to the initial control signal, the output end of the first inverter outputs the second forward control signal, the output end of the second inverter is connected to the input end of the third inverter, the output end of the third inverter outputs the first forward control signal, and the power supply ends of all inverters are connected to the power supply.

[0006] In some embodiments of the present disclosure, the inverter includes a first PHEMT tube, a second PHEMT tube, a third PHEMT tube, a first adjustment resistor and a second adjustment resistor, the drain of the first PHEMT tube serves as the input end of the inverter, the gate of the first PHEMT tube is connected to the gate of the second PHEMT tube, the source of the first PHEMT tube is connected to the gate of the second PHEMT tube through the first adjustment resistor, the source of the second PHEMT tube is grounded, the drain of the second PHEMT tube serves as the output end of the inverter, the drain of the third PHEMT tube serves as the power supply end of the inverter, the gate of the third PHEMT tube is connected to the drain of the second PHEMT tube, and the source of the third PHEMT tube is connected to the drain of the second PHEMT tube through the second adjustment resistor.

[0007] In some embodiments of the present disclosure, the second forward control signal and the first forward control signal are a pair of complementary forward control signals; In some embodiments of the present disclosure, the gate of the first transistor is connected to the first forward control signal through the first gate resistor, the gate of the second transistor is connected to the second forward control signal through the second gate resistor, the gate of the third transistor is connected to the second forward control signal through the third gate resistor, and the gate of the fourth transistor is connected to the first forward control signal through the fourth gate resistor.

[0008] In some embodiments of the present disclosure, the drain of the first transistor and the drain of the third transistor are both connected to the RF common port through the first DC blocking capacitor, the source of the first transistor is connected to the first RF output port through the second DC blocking capacitor, the source of the second transistor is connected to the ground through the third DC blocking capacitor, the source of the third transistor is connected to the second RF output port through the fourth DC blocking capacitor, and the source of the fourth transistor is connected to the ground through the fifth DC blocking capacitor.

[0009] In some embodiments of the present disclosure, the source of the second transistor is connected to the power supply through a first bias resistor, and the source of the fourth transistor is connected to the power supply through a second bias resistor.

[0010] In some embodiments of the present disclosure, the transistor is a PHEMT transistor.

[0011] The beneficial effects achieved by the present invention are as follows: the present invention adds parallel inductance to the traditional circuit for matching, and can adopt a low Ron structure, thereby achieving low insertion loss and high isolation of the RF switch, and the addition of the inductor reduces the switch area compared to the traditional method of increasing the number of switch tubes. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a first structural schematic diagram of a radio frequency switch; Figure 2 The second structural diagram of the radio frequency switch Figure 3is an echo curve diagram; in the figure, S11 is the input return loss, and S22 is the output return loss; Figure 4 It is a curve diagram of insertion loss simulation; S21 in the figure is the insertion loss; Figure 5 It is a simulation curve diagram of isolation degree; S31 and S32 in the figure are isolation degrees. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is obvious that the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present disclosure and its application or use. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0014] Unless otherwise specified, the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0015] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0016] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0017] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0018] It should be noted that similar symbols and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it does not require further discussion in subsequent figures.

[0019] In order to solve the problems existing in the traditional way of improving switch isolation, the present invention discloses a radio frequency switch, specifically, a parallel inductor is added to the traditional circuit for matching to achieve a radio frequency switch with low insertion loss, high isolation and small area.

[0020] Figure 1 Schematic diagram of an embodiment of the radio frequency switch disclosed in the present invention, which mainly includes a first transistor SW1, a second transistor SW2, a third transistor SW3, a fourth transistor SW4 and an inductor L.

[0021] The gate of the first transistor SW1 is connected to the first forward control signal V1, the drain of the first transistor SW1 is connected to the RF common port P0, and the source of the first transistor SW1 is respectively connected to the first RF output port P1, the drain of the second transistor SW2 and one end of the inductor L; the gate of the second transistor SW2 is connected to the second forward control signal V2, and the source of the second transistor SW2 is respectively connected to the power supply (+5V) and the ground; the gate of the third transistor SW3 is connected to the second forward control signal V2, the drain of the third transistor SW3 is connected to the RF common port P0, and the source of the third transistor SW3 is respectively connected to the second RF output port P2, the drain of the fourth transistor SW4 and the other end of the inductor L; the gate of the fourth transistor SW4 is connected to the first forward control signal V1, and the source of the fourth transistor SW4 is respectively connected to the power supply (+5V) and the ground.

[0022] It should be noted that the first forward control signal V1 and the second forward control signal V2 may be directly input from the outside, or may be controlled by a logic circuit, that is, the switch may be controlled by a logic circuit.

[0023] See Figure 2 The logic circuit includes a first inverter S1, a second inverter S2 and a third inverter S3. The input ends of the first inverter S1 and the second inverter S2 are both externally connected to the initial control signal VIN. The output end of the first inverter S1 outputs the second forward control signal V2. The output end of the second inverter S2 is connected to the input end of the third inverter S3. The output end of the third inverter S3 outputs the first forward control signal V1. The power supply ends of all inverters are connected to the power supply (+5V).

[0024] It should be noted that the results of all inverters are consistent. The inverter includes a first PHEMT tube P1, a second PHEMT tube P2, a third PHEMT tube P3, a first regulating resistor R7 and a second regulating resistor R8. The drain of the first PHEMT tube P1 serves as the input end of the inverter, the gate of the first PHEMT tube P1 is connected to the gate of the second PHEMT tube P2, the source of the first PHEMT tube P1 is connected to the gate of the second PHEMT tube P2 through the first regulating resistor R7, the source of the second PHEMT tube P2 is grounded, the drain of the second PHEMT tube P2 serves as the output end of the inverter, the drain of the third PHEMT tube P3 serves as the power supply end of the inverter, the gate of the third PHEMT tube P3 is connected to the drain of the second PHEMT tube P2, and the source of the third PHEMT tube P3 is connected to the drain of the second PHEMT tube P2 through the second regulating resistor R8; wherein the first regulating resistor R7 and the second regulating resistor R8 are both used to adjust the static operating point.

[0025] It should be noted that the second forward control signal and the first forward control signal are a pair of complementary forward control signals. When VIN is 0~1V, the first PHEMT tube P1 of the inverter is not turned on and the output voltage is a high level; when VIN is 3.3~5V, the transistor operates in the saturation region and the output voltage is a low level.

[0026] It should be noted that the voltage of the initial control signal VIN can fluctuate and can adapt to different input voltage requirements; for example: if the initial control signal is a voltage signal of 0~1V, then the first forward control signal V1 is a voltage signal of 0V, and the second forward control signal V2 is a voltage signal of 5V; if the initial control signal is a voltage signal of 3.3~5V, then the first forward control signal V1 is a voltage signal of 5V, and the second forward control signal V2 is a voltage signal of 0V.

[0027] It should be noted that, in some embodiments, the gate of the first transistor SW1 is connected to the first forward control signal V1 through the first gate resistor R1, the gate of the second transistor SW2 is connected to the second forward control signal V2 through the second gate resistor R2, the gate of the third transistor SW3 is connected to the second forward control signal V2 through the third gate resistor R3, and the gate of the fourth transistor SW4 is connected to the first forward control signal V1 through the fourth gate resistor R4; wherein the gate resistors can adjust the current and voltage in the circuit, protect the circuit, and suppress noise.

[0028] It should be noted that, in some embodiments, the drain of the first transistor SW1 and the drain of the third transistor SW3 are both connected to the RF common port P0 through the first DC blocking capacitor C1, the source of the first transistor SW1 is connected to the first RF output port P1 through the second DC blocking capacitor C2, the source of the second transistor SW2 is connected to the ground through the third DC blocking capacitor C3, the source of the third transistor SW3 is connected to the second RF output port P2 through the fourth DC blocking capacitor C4, and the source of the fourth transistor SW4 is connected to the ground through the fifth DC blocking capacitor C5; wherein, since the capacitor is a high impedance for the RF signal and a low impedance for the DC signal, the DC blocking capacitor can prevent the DC signal from passing through and only allow the RF signal to be transmitted. By isolating the DC, the stability and reliability of the RF circuit can be guaranteed.

[0029] It should be noted that the capacitance of the DC blocking capacitor is generally large, so other components in the circuit except the DC blocking capacitor can be integrated inside the chip, while the DC blocking capacitor is distributed separately outside.

[0030] It should be noted that, in some embodiments, the source of the second transistor SW2 is connected to the power supply (+5V) through the first bias resistor R5, and the source of the fourth transistor SW4 is connected to the power supply (+5V) through the second bias resistor R6; wherein the bias resistor can adjust the base bias current so that the transistor has a suitable operating point.

[0031] It should be noted that the above transistors may be PMOS, NMOS, PHEMT or LDMOS transistors, and all transistors herein are PHEMT transistors.

[0032] by Figure 2 For example, when the first forward control signal V1 is at a high potential and the second forward control signal V2 is at a low potential, the first transistor SW1 is in an on state and the second transistor SW2 is in an off state; similarly, the fourth transistor SW4 is in an on state and the third transistor SW3 is in an off state. Therefore, the microwave signal passes through the channel input to the first RF output port P1, and the microwave signal is cut off when input to the channel of the second RF output port P2, and the switch circuit completes the switching of the signal channel.

[0033] When the first forward control signal V1 is at a low potential and the second forward control signal V2 is at a high potential, the first transistor SW1 is in a cut-off state and the second transistor SW2 is in a conduction state; similarly, the fourth transistor SW4 is in a cut-off state and the third transistor SW3 is in a conduction state. Therefore, the microwave signal passes through the channel input to the second RF output port P2, and the microwave signal is cut off in the channel input to the first RF output port P1, and the switch circuit completes the switching of the signal channel.

[0034] It should be noted that in the above-mentioned RF switch, the off capacitance and on resistance of the transistor itself and the inductor form a switch-type resonant cavity, and the insertion loss of the switch is only related to the resonant network formed by the on resistance Ron and inductor L of the series transistor and the off capacitance. Selecting a large-sized transistor can effectively reduce the on impedance of the transistor and increase the off capacitance, which is not only conducive to reducing the insertion loss, but also reduces the isolation inductance value and thus reduces the chip area.

[0035] To verify the above switch, simulate it: like Figure 3 As shown in the figure, the return loss simulation curve of the switch is given. The horizontal axis in the figure is the frequency, and the vertical axis is the return loss value at the frequency. The magnitude of the return value reflects the reflection loss of the signal. The smaller the value, the lower the reflection loss. At 3-6GHz, the return loss of the RF switch is less than -15dB.

[0036] like Figure 4As shown in the figure, the insertion loss simulation curve of the switch circuit is given. The horizontal axis in the figure is the frequency, and the vertical axis is the insertion loss value at the frequency. The size of the insertion loss can reflect the transmission efficiency of the signal. The larger the value, the higher the signal transmission efficiency. The insertion loss of the switch circuit at 3-6GHz is greater than -0.48dB.

[0037] like Figure 5 As shown in FIG. 1 , a simulation curve of the isolation of the switch circuit is given, in which the horizontal axis is the frequency and the vertical axis is the isolation value at the frequency. The isolation of the switch circuit is less than -30dB.

[0038] From the above simulation, it can be seen that the RF switch adds parallel inductance for matching, and can adopt a low Ron structure, which achieves low insertion loss, high isolation and small area of ​​the RF switch. On the one hand, the RF switch meets the high-power working conditions of the communication system and ensures the normal operation of the system. On the other hand, it only uses positive voltage for power supply and is easy to use, that is, only a set of complementary positive control signals is needed to complete the switching of the signal path.

[0039] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A radio frequency switch, characterized in that: comprising a first transistor, a second transistor, a third transistor, a fourth transistor and an inductor; The gate of the first transistor is connected to the first forward control signal, the drain of the first transistor is connected to the RF common port, and the source of the first transistor is respectively connected to the first RF output port, the drain of the second transistor and one end of the inductor; The gate of the second transistor is connected to the second forward control signal, and the source of the second transistor is connected to the power supply and the ground respectively; The gate of the third transistor is connected to the second forward control signal, the drain of the third transistor is connected to the RF common port, and the source of the third transistor is respectively connected to the second RF output port, the drain of the fourth transistor and the other end of the inductor; The gate of the fourth transistor is connected to the first forward control signal, and the source of the fourth transistor is connected to the power supply and the ground respectively.

2. The radio frequency switch according to claim 1, characterized in that: It also includes a logic circuit, which outputs a second forward control signal and a first forward control signal; the logic circuit includes a first inverter, a second inverter and a third inverter, the input ends of the first inverter and the second inverter are both externally connected to the initial control signal, the output end of the first inverter outputs the second forward control signal, the output end of the second inverter is connected to the input end of the third inverter, the output end of the third inverter outputs the first forward control signal, and the power supply ends of all inverters are connected to the power supply.

3. The radio frequency switch according to claim 2, characterized in that: The inverter includes a first PHEMT tube, a second PHEMT tube, a third PHEMT tube, a first regulating resistor and a second regulating resistor. The drain of the first PHEMT tube serves as the input end of the inverter, the gate of the first PHEMT tube is connected to the gate of the second PHEMT tube, the source of the first PHEMT tube is connected to the gate of the second PHEMT tube through the first regulating resistor, the source of the second PHEMT tube is grounded, the drain of the second PHEMT tube serves as the output end of the inverter, the drain of the third PHEMT tube serves as the power supply end of the inverter, the gate of the third PHEMT tube is connected to the drain of the second PHEMT tube, and the source of the third PHEMT tube is connected to the drain of the second PHEMT tube through the second regulating resistor.

4. The radio frequency switch according to claim 1, characterized in that: The second forward control signal and the first forward control signal are a pair of complementary forward control signals.

5. The radio frequency switch according to claim 1, characterized in that: The gate of the first transistor is connected to the first forward control signal through the first gate resistor, the gate of the second transistor is connected to the second forward control signal through the second gate resistor, the gate of the third transistor is connected to the second forward control signal through the third gate resistor, and the gate of the fourth transistor is connected to the first forward control signal through the fourth gate resistor.

6. The radio frequency switch according to claim 1, characterized in that: The drain of the first transistor and the drain of the third transistor are both connected to the RF common port through the first DC blocking capacitor, the source of the first transistor is connected to the first RF output port through the second DC blocking capacitor, the source of the second transistor is connected to the ground through the third DC blocking capacitor, the source of the third transistor is connected to the second RF output port through the fourth DC blocking capacitor, and the source of the fourth transistor is connected to the ground through the fifth DC blocking capacitor.

7. The radio frequency switch according to claim 1, characterized in that: The source of the second transistor is connected to the power supply through a first bias resistor, and the source of the fourth transistor is connected to the power supply through a second bias resistor.

8. The radio frequency switch according to any one of claims 1 to 7, characterized in that: The transistor is a PHEMT tube.

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