Active loop filter for low-jitter phase-locked loop
By designing an active loop filter including pulse signal selection, signal transmission, resistance capacitor and operational amplifier circuit in the phase-locked loop circuit, the problem of low jitter and high integration in the phase-locked loop circuit is solved. Excellent jitter performance and high integration are achieved.
Patent Information
- Application Number
- CN202411530559.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-02-18
AI Technical Summary
The prior art is difficult to achieve low jitter and high integration in phase-locked loop circuits, and the design of loop filters is difficult to take into account both performance and layout area.
Design an active loop filter for low jitter phase-locked loop, including pulse signal selection circuit, signal transmission circuit, resistor capacitor circuit and operational amplifier circuit, through these circuits, signal conversion and filtering are implemented to optimize the phase-locked loop Jitter performance and integration.
It realizes low power consumption and high anti-interference capability of signal transmission circuits, high quality factors and low layout area of resistor and capacitor circuits, high gain and good isolation performance of operational amplifier circuits, significantly optimizes the jitter performance and integration of phase-locked loops .
Smart Images
Figure CN119483590A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of phase-locked loops and filters, and in particular relates to an active loop filter for a low-jitter phase-locked loop. Background Art
[0002] As a timing reference, the phase-locked loop can generate a stable clock, thereby coordinating the various modules in the circuit to work together. It is widely used in aerospace, industrial production, radar communications and other fields, and directly affects the performance of each system. Therefore, the requirements for phase-locked loop circuits are constantly increasing, and the development of phase-locked loops tends to be high performance and high integration.
[0003] The loop filter is an important module of the phase-locked loop, which converts the current generated by the charge pump into a relatively stable control voltage of the voltage-controlled oscillator. The phase-locked loop is a typical closed-loop negative feedback system. The system stability and dynamic characteristics are particularly important. The parameter design of the loop filter determines the stability and dynamic characteristics of the entire phase-locked loop system, and will affect the phase noise, jitter, spurious and other performance indicators of the phase-locked loop system.
[0004] Loop filters include passive loop filters and active loop filters. In order to meet the bandwidth requirements, the values of resistance and capacitance required by passive loop filters are usually large, which occupies a large layout area and is difficult to achieve on-chip integration. In order to achieve a phase-locked loop circuit with higher performance and integration, the design of the loop filter is very critical. Summary of the invention
[0005] The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art and provide an active loop filter for a low-jitter phase-locked loop, which can be applied to a phase-locked loop circuit to achieve signal conversion and filtering, thereby improving the performance and integration of the phase-locked loop.
[0006] In order to solve the above technical problems, the present invention provides an active loop filter for a low-jitter phase-locked loop, comprising:
[0007] A pulse signal selection circuit and a signal transmission circuit provide a stable input for an operational amplifier circuit; wherein the signal transmission circuit comprises: a NOR gate NOR1, a NAND gate NAND, inverters INV1 to INV5, and a transmission gate composed of a PMOS tube MP9 and an NMOS tube MN11; the two input ends of the NOR gate NOR1 are respectively input with a low level input PDN and a signal CP_MUX, the output end of the NOR gate NOR1 is sequentially connected to inverters INV1 and INV2, the output end of the inverter INV2 is connected to the gate of the PMOS tube MP9 of the transmission gate, the signal CP_MUX is connected to the input end of the inverter INV3, the output end of the inverter INV3 and a high level input PUP are respectively connected to the two input ends of the NAND gate NAND, the output end of the NAND gate NAND is sequentially connected to inverters INV4 and INV5, and the output end of the inverter INV5 is connected to the gate of the NMOS tube MN11 of the transmission gate;
[0008] The resistor and capacitor circuits work together with the operational amplifier circuit to achieve frequency selection and amplitude control of the input signal;
[0009] The operational amplifier circuit enhances the amplitude of the charge pump output signal and converts the current signal into a stable voltage signal.
[0010] Preferably, the pulse signal selection circuit includes: a NOR gate NOR and an inverter INV, the two input ends of the NOR gate NOR respectively input the pulse signals UP and DOWN generated by the frequency detector and phase detector, the output end of the NOR gate NOR is connected to the input end of the inverter INV, and the output end of the inverter INV outputs the selected signal CP_MUX.
[0011] Preferably, the connection circuit of the transmission gate includes: the drain of the PMOS tube MP9 is connected to the source of the NMOS tube MN11 and is connected to the current signal I CP , the source of the PMOS tube MP9 is connected to the drain of the NMOS tube MN11 and outputs a current signal I OUT After being processed by the logic gate, the signal transmitted to the gate of the PMOS tube MP9 is TG_EN, and the signal transmitted to the gate of the NMOS tube MN11 is TG_EN.
[0012] Preferably, when the signal TG_EN is at a high level, the charge pump is charging or discharging, and the transmission gate is turned on, and the current I CP Convert to I OUT Output; when the signal TG_EN is low, the transmission gate is closed.
[0013] Preferably, the resistor-capacitor circuit comprises: a capacitor C1 and resistors R1 to R3; one end of the resistor R1 is connected to the current signal IOUT The other end of the resistor R2 is connected to the output voltage signal VOUT and the resistor R3, and the other end of the resistor R3 is connected to the control voltage signal V TUNE .
[0014] Preferably, the operational amplifier circuit includes: PMOS tubes P1-P10, NMOS tubes N1-N3, transistors Q1-Q6, resistors R4-R8, resistor Rc and capacitor Cc; the gate of the PMOS tube P1 is connected to the bias current Ibias, the source of the PMOS tube P1 is connected to the power supply voltage VDD, the drain of the PMOS tube P1 is connected to the source of the PMOS tubes P2 and PMOS tubes P3, the gate of the PMOS tube P2 is connected to the input signal CP_OUT, the drain of the PMOS tube P2 is connected to the collector and base of the transistor Q1, the emitter of the transistor Q1 is connected to the grounded resistor R4, and the gate of the PMOS tube P3 is connected to the reference voltage V REF The drain of PMOS tube P3 is connected to the collector of transistor Q2 and transistor Q3, the base of transistor Q2 is connected to the base of transistor Q1, the base of transistor Q6 and the gate of PMOS tube P9, the emitter of transistor Q2 is connected to the grounded resistor R5, the emitter of transistor Q3 is connected to the grounded resistor R6, the base of transistor Q3 is connected to the base of transistor Q4, the emitter of transistor Q4 is connected to the grounded resistor R7, the collector of transistor Q4 is connected to the grounded resistor R8, and the emitter of transistor Q4 is connected to the grounded resistor R9. The gate of PMOS tube P4 and PMOS tube P5 are connected to each other and connected to the drain of PMOS tube P5 and the base of transistor Q5. The source of PMOS tube P4 and PMOS tube P5 are connected to the power supply voltage VDD. The collector of transistor Q5 is connected to the power supply voltage VDD. The emitter of transistor Q5 is connected to the collector of transistor Q6. The emitter of transistor Q6 is connected to the grounded resistor R8. PMOS tube P6, PM The sources of the OS transistor P7 and the PMOS transistor P8 are connected to the power supply voltage VDD, the gate of the PMOS transistor P6 is connected to the bias current Ibias, the drain of the PMOS transistor P6 is connected to the drain of the NMOS transistor N1, the source of the NMOS transistor N1 is connected to the source of the PMOS transistor P9, the drain of the PMOS transistor P9 is grounded, the gates of the NMOS transistors N1 and NMOS transistors N2 are interconnected, the drain of the NMOS transistor N2 is connected to the drain and gate of the PMOS transistor P7 and the gate of the PMOS transistor P8, the source of the NMOS transistor N2 is connected to the source of the PMOS transistor P10, the drain of the PMOS transistor P10 is grounded, the gates of the PMOS transistor P10 and the NMOS transistor N3 are interconnected and connected to one end of the capacitor Cc, the other end of the capacitor Cc is connected to one end of the resistor Rc, the other end of the resistor Rc is connected to the drain of the NMOS transistor N3, the drain of the PMOS transistor P8 and the output voltage signal VOUT, and the source of the NMOS transistor N3 is grounded.
[0015] Preferably, the PMOS transistors P1-P3 and the transistors Q1-Q2 form a first-stage differential amplifier structure, which can provide high gain and suppress common-mode signal interference.
[0016] Preferably, the PMOS tube P8 and the NMOS tube N3 form a second-stage common-source amplifier structure, which can provide a large swing for the circuit.
[0017] Preferably, the PMOS transistors P4 to P7, PMOS transistors P9 to P10, NMOS transistors N1 to N2 and transistors Q3 to Q6 form a bias circuit to provide a stable static operating point for the circuit.
[0018] Compared with the prior art, the present invention has the following beneficial effects:
[0019] 1. The signal transmission circuit of the present invention can reduce the burrs and overshoots of the signal, has good voltage transmission characteristics, high noise tolerance, strong anti-interference ability, and low power consumption, and can provide a stable signal as the input of the operational amplifier, thereby optimizing the jitter performance of the phase-locked loop.
[0020] 2. The active loop filter of the present invention adopts a proportional integral structure, which can reduce the layout area and achieve higher integration compared with the passive loop filter. The performance compromise is achieved by flexibly selecting the size of the resistor and the capacitor. It has a higher quality factor and can effectively suppress the high-frequency noise component and spurious of the charge pump output current, preventing the high-frequency signal from affecting the voltage-controlled oscillator, thereby optimizing the noise performance of the voltage-controlled oscillator and reducing jitter. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 Schematic diagram of the charge pump phase-locked loop structure.
[0022] Figure 2 It is a schematic diagram of the structure of the active loop filter of the present invention.
[0023] Figure 3 It is a schematic diagram of the structure of the pulse signal selection circuit of the active loop filter of the present invention.
[0024] Figure 4 The figure is a schematic diagram of the signal transmission circuit structure of the active loop filter of the present invention.
[0025] Figure 5 The figure is a signal transmission circuit principle and a signal transmission path diagram of the active loop filter of the present invention.
[0026] Figure 6 A timing diagram of key signals in an embodiment of the present invention when charging a charge pump.
[0027] Figure 7It is a timing diagram of key signals in an embodiment of the present invention when the charge pump is discharged.
[0028] Figure 8 The schematic diagram of the operational amplifier circuit of the active loop filter of the present invention is shown in FIG. DETAILED DESCRIPTION
[0029] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0030] like Figure 1 As shown in Figure 1, the charge pump phase-locked loop is a digital-analog hybrid phase-locked loop that theoretically has zero static phase, a wide frequency locking range, high system gain, low power consumption, and high robustness, so it is widely used. Figure 1 , including a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The frequency detector compares the input reference signal f REF And the divided signal f DIV The phase difference is generated to generate a pulse signal proportional to the phase difference, and this pulse signal is input into the charge pump to control the charge pump to charge and discharge the loop filter, generate the control voltage of the voltage-controlled oscillator, and make the voltage-controlled oscillator change the output signal f OUT The frequency of the high frequency f OUT Input the frequency divider to divide the frequency and get f DIV Input frequency detector and phase detector to form a negative feedback loop, and finally realize f OUT With f REF Same frequency and same phase.
[0031] When the phase-locked loop is locked and the loop bandwidth is less than 1 / 10 of the reference frequency, it can be approximated as a continuous linear system and analyzed using the s-domain model. In the s-domain, let θ ref (s) is the input reference signal, θ fb (s) is the feedback signal, I cp (s) is the charge pump output current, V tune (s) is the control voltage output by the loop filter, θ out (s) is the output signal.
[0032] When analyzing in a linear model, the phase frequency detector and the charge pump are usually combined, and the transfer function of the phase frequency detector and the charge pump is obtained as follows:
[0033] Assume the frequency tuning gain of the voltage controlled oscillator is K VCO , the self-oscillation frequency is ω0, and the output frequency is ω vco, the output voltage of the loop filter is V tune , then:ω vco =ω0+K vco V tune By integrating it, we can get the transfer function of the voltage-controlled oscillator:
[0034] The frequency divider can get different frequency outputs by setting different frequency division ratios N, so the transfer function is 1 / N. Combining the transfer functions of other modules, the open-loop transfer function of the phase-locked loop system can be obtained as:
[0035]
[0036] The closed-loop transfer function of the phase-locked loop system is:
[0037] For a schematic diagram of the structure of the active loop filter according to an embodiment of the present invention, see Figure 2 , the active proportional-integral filter transfer function is:
[0038] At this time, the open-loop transfer function of the charge pump phase-locked loop is:
[0039] By bringing the phase-locked loop parameters into calculation and analysis, it can be obtained that the loop filter adds a pole located at the origin and a zero point in the left half plane to the phase-locked loop system. The phase-locked loop system is stable and can attenuate the system's stray noise.
[0040] like Figures 2 to 8 As shown, the embodiment of the present invention specifically provides an active loop filter for a low-jitter phase-locked loop, and the loop filter adopts a proportional-integral structure, including:
[0041] A pulse signal selection circuit and a signal transmission circuit can reduce burrs in a signal, provide a stable input for an operational amplifier circuit, have low power consumption and strong anti-interference capability; wherein the signal transmission circuit comprises: a NOR gate NOR1, a NAND gate NAND, inverters INV1 to INV5 and a transmission gate composed of a PMOS tube MP9 and an NMOS tube MN11; the two input ends of the NOR gate NOR1 are respectively input with a low-level input PDN and a signal CP_MUX, the output end of the NOR gate NOR1 is sequentially connected to the inverter INV1 and the inverter INV2, the output end of the inverter INV2 is connected to the gate of the PMOS tube MP9 of the transmission gate, the signal CP_MUX is connected to the input end of the inverter INV3, the output end of the inverter INV3 and a high-level input PUP are respectively connected to the two input ends of the NAND gate NAND, the output end of the NAND gate NAND is sequentially connected to the inverter INV4 and the inverter INV5, and the output end of the inverter INV5 is connected to the gate of the NMOS tube MN11 of the transmission gate;
[0042] The resistor and capacitor circuits work together with the operational amplifier circuit to achieve frequency selection and amplitude control of the input signal;
[0043] The operational amplifier circuit enhances the amplitude of the charge pump output signal, converts the current signal into a stable voltage signal, and realizes inter-stage isolation to ensure the stability and reliability of the circuit.
[0044] like Figure 3 As shown, the pulse signal selection circuit includes: a NOR gate NOR and an inverter INV, the two input ends of the NOR gate NOR respectively input the pulse signals UP and DOWN generated by the frequency detector and phase detector, the output end of the NOR gate NOR is connected to the input end of the inverter INV, and the output end of the inverter INV outputs the selected signal CP_MUX.
[0045] like Figure 3 As shown, the connection circuit of the transmission gate includes: the drain of the PMOS tube MP9 is connected to the source of the NMOS tube MN11 and is connected to the current signal I CP , the source of the PMOS tube MP9 is connected to the drain of the NMOS tube MN11 and outputs a current signal I OUT After being processed by the logic gate, the signal transmitted to the gate of the PMOS tube MP9 is TG_EN, and the signal transmitted to the gate of the NMOS tube MN11 is TG_EN.
[0046] like Figure 2 As shown, the resistor-capacitor circuit includes: a capacitor C1 and resistors R1 to R3; one end of the resistor R1 is connected to the current signal I OUTThe other end of the capacitor C1 is connected to the output signal CP_OUT and the capacitor C1, the other end of the capacitor C1 is connected to the resistor R2, the other end of the resistor R2 is connected to the output voltage signal VOUT and the resistor R3, and the other end of the resistor R3 is connected to the control voltage signal V TUNE The above-mentioned resistor and capacitor circuit plays the role of filtering and adjusting circuit performance. By flexibly selecting the size of the resistor and capacitor to achieve a compromise in performance, the layout area can be reduced and the integration level can be improved.
[0047] like Figure 6 As shown, the operational amplifier circuit includes: PMOS tubes P1-P10, NMOS tubes N1-N3, transistors Q1-Q6, resistors R4-R8, resistor Rc and capacitor Cc; the gate of the PMOS tube P1 is connected to the bias current Ibias, the source of the PMOS tube P1 is connected to the power supply voltage VDD, the drain of the PMOS tube P1 is connected to the source of the PMOS tubes P2 and PMOS tubes P3, the gate of the PMOS tube P2 is connected to the input signal CP_OUT, the drain of the PMOS tube P2 is connected to the collector and base of the transistor Q1, the emitter of the transistor Q1 is connected to the grounded resistor R4, and the gate of the PMOS tube P3 is connected to the reference voltage V REFThe drain of PMOS tube P3 is connected to the collector of transistor Q2 and transistor Q3, the base of transistor Q2 is connected to the base of transistor Q1, the base of transistor Q6 and the gate of PMOS tube P9, the emitter of transistor Q2 is connected to the grounded resistor R5, the emitter of transistor Q3 is connected to the grounded resistor R6, the base of transistor Q3 is connected to the base of transistor Q4, the emitter of transistor Q4 is connected to the grounded resistor R7, the collector of transistor Q4 is connected to the grounded resistor R8, and the emitter of transistor Q4 is connected to the grounded resistor R9. The gate of PMOS tube P4 and PMOS tube P5 are connected to each other and connected to the drain of PMOS tube P5 and the base of transistor Q5. The source of PMOS tube P4 and PMOS tube P5 are connected to the power supply voltage VDD. The collector of transistor Q5 is connected to the power supply voltage VDD. The emitter of transistor Q5 is connected to the collector of transistor Q6. The emitter of transistor Q6 is connected to the grounded resistor R8. PMOS tube P6, PM The sources of the OS transistor P7 and the PMOS transistor P8 are connected to the power supply voltage VDD, the gate of the PMOS transistor P6 is connected to the bias current Ibias, the drain of the PMOS transistor P6 is connected to the drain of the NMOS transistor N1, the source of the NMOS transistor N1 is connected to the source of the PMOS transistor P9, the drain of the PMOS transistor P9 is grounded, the gates of the NMOS transistors N1 and NMOS transistors N2 are interconnected, the drain of the NMOS transistor N2 is connected to the drain and gate of the PMOS transistor P7 and the gate of the PMOS transistor P8, the source of the NMOS transistor N2 is connected to the source of the PMOS transistor P10, the drain of the PMOS transistor P10 is grounded, the gates of the PMOS transistor P10 and the NMOS transistor N3 are interconnected and connected to one end of the capacitor Cc, the other end of the capacitor Cc is connected to one end of the resistor Rc, the other end of the resistor Rc is connected to the drain of the NMOS transistor N3, the drain of the PMOS transistor P8 and the output voltage signal VOUT, and the source of the NMOS transistor N3 is grounded.
[0048] The signal transmission circuit, the circuit structure diagram is shown in Figure 4 , circuit schematics and signal transmission paths refer to Figure 5 , including NOR gate, NAND gate, inverters INV1~INV5 and transmission gate composed of PMOS tube MP1 and NMOS tube MN1, PDN is low level input, PUP is high level input. After the logic gate is processed to reduce the burr, the signal transmitted to the gate of NMOS tube MN1 is TG_EN, and the signal transmitted to the gate of PMOS tube MP1 is
[0049] The timing diagram of key signals when the charge pump is charging is as follows: Figure 6 As shown, at this time the reference signal f REF Leading the feedback signal f DIV The frequency detector generates UP and DOWN, which are passed through the pulse signal selection circuit to generate CP_MUX, and the burrs are reduced to generate TG_EN and The timing diagram of key signals when the charge pump is discharging is as follows: Figure 7 As shown, at this time the reference signal f REF Lagging behind the feedback signal f DIV Similarly, UP and DOWN are selected to generate CP_MUX, which reduces the burr and generates TG_EN and In summary, when the signal TG_EN is high, it means that the charge pump is charging or discharging. At this time, the transmission gate is turned on and the current I CP Convert to I OUT Output; when the signal TG_EN is low, the transmission gate is closed.
[0050] The operational amplifier circuit adopts a two-stage amplification structure with high input impedance and low output impedance, which can achieve good isolation performance and greater gain. Figure 8 , including 13 MOS tubes, 6 transistors, 6 resistors and 1 capacitor. Among them, PMOS tubes P1, P2, P3 and transistors Q1, Q2 constitute the first-stage differential amplifier structure, which can provide high gain and suppress common-mode signal interference. PMOS tube P8 and NMOS tube N3 constitute the second-stage common source amplifier structure, which can provide a large swing for the circuit. Resistor Rc and capacitor Cc realize Miller compensation. PMOS tubes P4, P5, P6, P7, P9, P10, NMOS tubes N1, N2, and transistors Q3, Q4, Q5, Q6 constitute a bias circuit to provide a stable static operating point for the circuit. The operational amplifier enables the output end of the charge pump to be stable at a fixed reference level, which can reduce the non-ideal effect of "charge sharing" of the charge pump and ensure that the current source tubes in the charge pump are all working in a saturated state.
[0051] The embodiment of the present invention uses the signal transmission circuit, the resistor and capacitor circuit and the amplifier circuit to convert the current signal I output by the charge pump into CP Converted into a relatively stable control voltage signal V of the voltage-controlled oscillator TUNE , which can optimize the jitter performance of the phase-locked loop circuit. The signal transmission circuit can reduce the burrs and overshoots of the signal, has good voltage transmission characteristics, high noise tolerance, and low power consumption, and can provide a stable signal as the input of the operational amplifier; the resistor and capacitor circuit plays the role of filtering and adjusting the circuit performance, and can achieve a compromise in performance by flexibly selecting the size of the resistor and capacitor, which can reduce the layout area and improve the integration; the operational amplifier circuit has a high input impedance and a low output impedance, which can achieve good isolation performance and greater gain, has a higher quality factor, and has better ripple suppression ability.
[0052] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. An active loop filter for a low jitter phase-locked loop, characterized in that: include: The pulse signal selection circuit and the signal transmission circuit provide a stable input for the operational amplifier circuit; The signal transmission circuit comprises: a NOR gate NOR1, a NAND gate NAND, inverters INV1 to INV5 and a transmission gate composed of a PMOS tube MP9 and an NMOS tube MN11; the two input ends of the NOR gate NOR1 are respectively input with a low level PDN and a signal CP_MUX, the output end of the NOR gate NOR1 is sequentially connected to the inverter INV1 and the inverter INV2, the output end of the inverter INV2 is connected to the gate of the PMOS tube MP9 in the transmission gate, the signal CP_MUX is connected to the input end of the inverter INV3, the output end of the inverter INV3 and the high level input PUP are respectively connected to the two input ends of the NAND gate NAND, the output end of the NAND gate NAND is sequentially connected to the inverter INV4 and the inverter INV5, the output end of the inverter INV5 is connected to the gate of the NMOS tube MN11 of the transmission gate; The resistor and capacitor circuits work together with the operational amplifier circuit to achieve frequency selection and amplitude control of the input signal; The operational amplifier circuit enhances the amplitude of the charge pump output signal and converts the current signal into a stable voltage signal.
2. An active loop filter for a low jitter phase-locked loop as claimed in claim 1, characterized in that: The pulse signal selection circuit includes: a NOR gate NOR and an inverter INV, wherein the two input ends of the NOR gate NOR respectively input the pulse signals UP and DOWN generated by the frequency detector and phase detector, the output end of the NOR gate NOR is connected to the input end of the inverter INV, and the output end of the inverter INV outputs the selected signal CP_MUX.
3. An active loop filter for a low jitter phase-locked loop as claimed in claim 1, characterized in that: The connection circuit of the transmission gate includes: the drain of the PMOS tube MP9 is connected to the source of the NMOS tube MN11 and is connected to the current signal I CP , the source of the PMOS tube MP9 is connected to the drain of the NMOS tube MN11 and outputs a current signal I OUT After being processed by the logic gate, the signal transmitted to the gate of the PMOS tube MP9 is TG_EN, and the signal transmitted to the gate of the NMOS tube MN11 is TG_EN.
4. An active loop filter for a low jitter phase-locked loop as claimed in claim 3, characterized in that: When the signal TG_EN is high, the charge pump is charging or discharging, and the transmission gate is turned on. The current I CP Convert to I OUT Output; when the signal TG_EN is low, the transmission gate is closed.
5. An active loop filter for a low jitter phase-locked loop as claimed in claim 1, characterized in that: The resistor-capacitor circuit includes: a capacitor C1 and resistors R1 to R3; one end of the resistor R1 is connected to the current signal I OUT The other end of the resistor R2 is connected to the output voltage signal VOUT and the resistor R3, and the other end of the resistor R3 is connected to the control voltage signal V TUNE .
6. An active loop filter for a low jitter phase-locked loop as claimed in claim 1, characterized in that: The operational amplifier circuit comprises: PMOS tubes P1-P10, NMOS tubes N1-N3, transistors Q1-Q6, resistors R4-R8, resistor Rc and capacitor Cc; the gate of the PMOS tube P1 is connected to the bias current Ibias, the source of the PMOS tube P1 is connected to the power supply voltage VDD, the drain of the PMOS tube P1 is connected to the source of the PMOS tubes P2 and PMOS tubes P3, the gate of the PMOS tube P2 is connected to the input signal CP_OUT, the drain of the PMOS tube P2 is connected to the collector and base of the transistor Q1, the emitter of the transistor Q1 is connected to the grounded resistor R4, and the gate of the PMOS tube P3 is connected to the reference voltage V REF The drain of PMOS tube P3 is connected to the collector of transistor Q2 and transistor Q3, the base of transistor Q2 is connected to the base of transistor Q1, the base of transistor Q6 and the gate of PMOS tube P9, the emitter of transistor Q2 is connected to the grounded resistor R5, the emitter of transistor Q3 is connected to the grounded resistor R6, the base of transistor Q3 is connected to the base of transistor Q4, the emitter of transistor Q4 is connected to the grounded resistor R7, the collector of transistor Q4 is connected to the grounded resistor R8, and the emitter of transistor Q4 is connected to the grounded resistor R9. The gate of PMOS tube P4 and PMOS tube P5 are connected to each other and connected to the drain of PMOS tube P5 and the base of transistor Q5. The source of PMOS tube P4 and PMOS tube P5 are connected to the power supply voltage VDD. The collector of transistor Q5 is connected to the power supply voltage VDD. The emitter of transistor Q5 is connected to the collector of transistor Q6. The emitter of transistor Q6 is connected to the grounded resistor R8. PMOS tube P6, PM The sources of the OS transistor P7 and the PMOS transistor P8 are connected to the power supply voltage VDD, the gate of the PMOS transistor P6 is connected to the bias current Ibias, the drain of the PMOS transistor P6 is connected to the drain of the NMOS transistor N1, the source of the NMOS transistor N1 is connected to the source of the PMOS transistor P9, the drain of the PMOS transistor P9 is grounded, the gates of the NMOS transistors N1 and NMOS transistors N2 are interconnected, the drain of the NMOS transistor N2 is connected to the drain and gate of the PMOS transistor P7 and the gate of the PMOS transistor P8, the source of the NMOS transistor N2 is connected to the source of the PMOS transistor P10, the drain of the PMOS transistor P10 is grounded, the gates of the PMOS transistor P10 and the NMOS transistor N3 are interconnected and connected to one end of the capacitor Cc, the other end of the capacitor Cc is connected to one end of the resistor Rc, the other end of the resistor Rc is connected to the drain of the NMOS transistor N3, the drain of the PMOS transistor P8 and the output voltage signal VOUT, and the source of the NMOS transistor N3 is grounded.
7. An active loop filter for a low jitter phase-locked loop as claimed in claim 6, characterized in that: The PMOS transistors P1-P3 and the transistors Q1-Q2 form a first-stage differential amplifier structure, which can provide high gain and suppress common-mode signal interference.
8. An active loop filter for a low jitter phase-locked loop as claimed in claim 6, characterized in that: The PMOS tube P8 and the NMOS tube N3 form a second-stage common-source amplifier structure, which can provide a large swing for the circuit.
9. An active loop filter for a low jitter phase-locked loop as claimed in claim 6, characterized in that: The PMOS tubes P4-P7, PMOS tubes P9-P10, NMOS tubes N1-N2 and transistors Q3-Q6 form a bias circuit to provide a stable static operating point for the circuit.