Simulation training equipment clock synchronization method and device
By deploying the timer counting module and clock scheduling module in the simulation training equipment, the simulation clock synchronization of each sub-system node is achieved, which solves the problem that the clocks of each sub-system node in the simulation training equipment are not easy to synchronize, and improves the training effect and equipment security .
Patent Information
- Application Number
- CN202411650857.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-02-18
AI Technical Summary
Due to the differences between the development platforms of each sub-system node and the local clock, the simulation clocks of each sub-system node of the simulated training equipment are not easy to synchronize, which affects the training effect and equipment safety.
Deploy the timer counting module at the clock source node, obtain the timer count value and frequency and issue the clock pulse counting signal; the sub-system node receives the clock pulse counting signal as a local simulation clock to promote the sub-system simulation and forward the local simulation clock; in the main simulation The node deploys a clock scheduling module to control the clock pulse counting signal cycle and release or not, and ensures the simulation synchronization of the sub-system nodes.
Through the external clock source, high-precision clock pulse counting signals are uniformly released, and each sub-system node is scheduled for simulation calculations to ensure that each sub-system node runs at a unified clock beat, and improve the realistic and safeness of simulation training.
Smart Images
Figure CN119483801A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of simulation training equipment, and in particular to a method and device for synchronizing the clock of simulation training equipment. Background Art
[0002] The simulation training equipment is a training equipment that is controlled in real time by the main simulation node, and multiple subsystem nodes work in coordination, simulating the real flight operation and flight performance of the aircraft through human-computer interaction, software simulation and hardware response. In order to ensure that the subsystem nodes of the simulation training equipment respond promptly and accurately, so that the trainees can get a nearly real flight experience, the main simulation cycle of the simulation training equipment should be fixed at 10ms, and the system time delay should be controlled within 100ms. Due to the differences in the development platform and local clock of each subsystem node, it is very necessary to calibrate the time of the clock pulse uniformly controlled by the main simulation node during the operation of the simulation training equipment to ensure the real-time simulation synchronization of each subsystem node of the simulation training equipment.
[0003] Zhu Ling, Wang Yang, et al. designed a clock synchronization method for a high-level helicopter simulator in the article "Design of Clock Synchronization Method for Helicopter Simulator". They used the clock synchronization card APC424 and designed a synchronization signal output module and a synchronization signal input module based on a modular design concept, thus realizing the clock synchronization function of the entire simulator system. However, the development platform is Linux, which lacks versatility.
[0004] In the article "Research on Synchronous Simulation Methods in Remote Networked Flight Simulator Training", Zhang Bingqiang, Fang Wei, etc. used the precise timing synchronization pulses of GPS or Beidou navigation satellites as the trigger signal for cross-regional synchronous simulation, and realized the prediction and smooth real-time processing of remote simulator status information through the DRM model, thus achieving clock synchronization of remotely connected flight simulators. However, for locally connected simulators, the system is more complex and the cost is higher. Summary of the invention
[0005] The present invention provides a method and device for synchronizing the clock of a simulation training device, which can realize the synchronization of the simulation clocks of the main simulation node and each subsystem node. The technical solution for realizing the present invention is as follows:
[0006] In a first aspect, a method for synchronizing a clock of a simulation training device is provided, the method comprising:
[0007] Step 1: Deploy a timer counting module on the clock source node to obtain the timer count value and timer frequency and publish a clock pulse counting signal;
[0008] Step 2: The subsystem node receives the clock pulse count signal as the local simulation clock to advance the subsystem simulation, and forwards the local simulation clock;
[0009] Step 3: Deploy a clock scheduling module on the main simulation node to control the clock pulse counting signal period and whether the clock pulse counting signal is released, so that the subsystem node simulation is synchronized.
[0010] The clock source node includes a chip or processor containing a timer; the timer counting module includes a timer interface scheduling submodule and a clock pulse counting submodule; the timer interface scheduling submodule is used to obtain the count value and frequency of the timer through the timer interface; the clock pulse counting submodule is used to publish a clock pulse counting signal according to the count value and frequency period of the timer.
[0011] The clock pulse counting signal is issued by the clock pulse counting submodule when the timer count value reaches the ratio of the timer frequency to the clock pulse counting frequency; the clock pulse counting frequency is the inverse of the clock pulse counting period.
[0012] The subsystem node deploys a functional simulation module and a timing advancement module; the functional simulation module is used to simulate and implement the subsystem function of the simulation training equipment, and advance the simulation according to the local simulation clock; the timing advancement module is used to control the local simulation clock beat to advance one step according to the clock pulse counting signal; the local simulation clock includes a clock beat that controls the operation of the functional simulation module, and when the local clock beat advances one step, the functional simulation module runs a simulation of one beat.
[0013] Optionally, when the main simulation node meets the conditions of a chip or processor containing a timer, it can also serve as a clock source node for the simulation training device.
[0014] The clock scheduling module includes calculating the system synchronization error of each subsystem by receiving the clock pulse count signal of the clock source node and the local simulation clock of each subsystem node; the system synchronization error is the difference between the clock pulse count signal of the clock source node and the local simulation clock of the subsystem node.
[0015] Optionally, the clock pulse counting cycle is calculated by adjusting the scaling ratio of the basic cycle according to the size of the system synchronization error; the basic cycle is a unified simulation cycle set by the simulation training equipment to ensure the real-time training; the scaling ratio is based on the size of the system synchronization error of each subsystem, and the ratio of the largest system synchronization error in each subsystem to the number of scaling cycles is taken; the number of scaling cycles is the number of beats required for the subsystem with misaligned clock beats to re-complete clock synchronization, and customization is supported.
[0016] Optionally, the specific calculation method of the clock pulse counting period is to superimpose the product of the scaling ratio and the basic period and the basic period.
[0017] The clock scheduling module also includes comparing the system synchronization error with the maximum allowable error of the system. When the system synchronization error exceeds the maximum allowable error of the system, the clock source node is controlled to stop issuing the clock pulse counting signal; the maximum allowable error of the system is the maximum clock synchronization error that does not affect the normal operation and training of the simulation training equipment.
[0018] In a second aspect, the present invention further provides a simulation training device clock synchronization device, the device comprising:
[0019] A timer counting module, used to obtain a timer count value and a timer frequency and issue a clock pulse counting signal;
[0020] A timing advancement module, used to control the local simulation clock beat to advance one step according to the clock pulse counting signal;
[0021] Functional simulation module, used to simulate and implement the subsystem functions of the simulation training equipment and advance the simulation according to the local simulation clock;
[0022] The clock scheduling module is used to control the clock pulse counting signal cycle and the release of the clock pulse counting signal.
[0023] The clock synchronization method and device of the simulation training equipment provided by the present invention deploy a timer counting module at the clock source node, obtain the timer counting value and timer frequency and publish a clock pulse counting signal; the subsystem node receives the clock pulse counting signal as the local simulation clock to promote the subsystem simulation, and forwards the local simulation clock; the clock scheduling module is deployed at the main simulation node to control the clock pulse counting signal period and whether the clock pulse counting signal is released, so that the subsystem node simulation is synchronized. Therefore, the main simulation node controls the precise clock pulse counting signal released by the clock source node, and each subsystem node receives the clock pulse counting signal to promote the subsystem simulation operation. When a certain subsystem has a delay, the main simulation node controls the clock source node to extend the period of issuing the clock pulse counting signal, which can ensure that the local simulation clocks between multiple subsystems are consistent, and effectively ensure the safe operation of the simulation training equipment. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.
[0025] Figure 1 is a schematic diagram of an implementation environment provided by an embodiment of the present invention;
[0026] Figure 2It is a schematic flow chart of a clock synchronization method provided by an embodiment of the present invention;
[0027] Figure 3 It is a schematic diagram of the structure of a clock synchronization method provided by an embodiment of the present invention;
[0028] Figure 4 It is a schematic diagram of the structure of another clock synchronization method provided by an embodiment of the present invention;
[0029] Figure 5 It is a schematic diagram of the structure of another clock synchronization method provided by an embodiment of the present invention;
[0030] Figure 6 It is a schematic diagram of the structure of another clock synchronization method provided by an embodiment of the present invention;
[0031] Figure 7 It is a schematic diagram of the structure of another clock synchronization method provided by an embodiment of the present invention;
[0032] Figure 8 It is a schematic diagram of the structure of another clock synchronization method provided by an embodiment of the present invention;
[0033] Fig. 9 is another implementation environment schematic diagram provided by an embodiment of the present invention;
[0034] Fig.10 The figure is a schematic diagram of the composition of a clock synchronization device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0035] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.
[0036] At present, in simulation training equipment, the main simulation node can uniformly control data interaction and simulation advancement according to the clock beat, and each subsystem node receives the control signal of the main simulation node to perform simulation software calculations.
[0037] However, since each subsystem node may be developed based on different platforms and run on different platforms, the local clock accuracy is also different, and the calculation complexity of the simulation software carried by each subsystem node is quite different. The system resources required and the calculation time vary greatly, which may lead to the phenomenon of subsystem mismatch, that is, some subsystems advance the simulation according to the speed of real time, while some subsystems lag behind the real time due to complex calculations, insufficient resources and other reasons, resulting in the data of each subsystem node not being on a unified clock beat, which may cause poor simulation training results at the least, and affect the safety of personnel and equipment at the worst.
[0038] In order to solve the above problems, the embodiment of the present invention provides a method and device for synchronizing the clock of a simulation training device, the method comprising: deploying a timer counting module at a clock source node, for obtaining a timer count value and a timer frequency and issuing a clock pulse counting signal; a subsystem node receiving the clock pulse counting signal as a local simulation clock to advance the subsystem simulation, and forwarding the local simulation clock; deploying a clock scheduling module at a main simulation node, for controlling the clock pulse counting signal cycle and whether the clock pulse counting signal is issued, so that the subsystem node simulation is synchronized. In this way, a high-precision clock pulse counting signal is uniformly issued through an external clock source, and each subsystem node is scheduled to perform simulation calculations, and the system synchronization error of each subsystem node is monitored by the main simulation node. When a system synchronization error occurs, the clock source node is controlled to slow down the issuance of the clock pulse counting signal, so that the subsystem with a lag phenomenon catches up with the clock beat of other subsystems; when the system synchronization error is too large, the clock source node is controlled to stop issuing the clock pulse counting signal and stop the simulation training. In this way, it can be ensured that each subsystem node runs at a unified clock beat and outputs relevant simulation data, ensuring that the simulation training is realistic and safe.
[0039] A clock synchronization method provided by an embodiment of the present invention can be applied to Figure 1 In the simulation training equipment environment shown in the figure, the clock source node 103 communicates with the main simulation node 101 and each subsystem node 102 through the switch, the clock source node 103 obtains the timer count value and the timer frequency and issues a clock pulse count signal; each subsystem node 102 receives the clock pulse count signal as a local simulation clock and promotes the subsystem simulation, while forwarding the local simulation clock; the main simulation node 101 receives the clock pulse count signal issued by the clock source node 103 and the local simulation clock forwarded by each subsystem node 102, calculates the system synchronization error of each subsystem, and thus controls the clock pulse count signal period and the issuance of the clock pulse count signal.
[0040] Among them, the subsystem node 102 includes but is not limited to a flight performance simulation subsystem node, an avionics simulation subsystem node, a visual subsystem node, a dynamic simulation subsystem node, an integrated environment simulation subsystem node, and a sound simulation subsystem node.
[0041] In an exemplary embodiment, Figure 2 As shown, a clock synchronization method is provided, comprising the following steps 201 to 203, wherein:
[0042] Step 201: deploy a timer counting module at a clock source node to obtain a timer count value and a timer frequency and issue a clock pulse counting signal;
[0043] Step 202: The subsystem node receives the clock pulse count signal as a local simulation clock to advance the subsystem simulation, and forwards the local simulation clock;
[0044] Step 203: deploy a clock scheduling module in the main simulation node to control the clock pulse counting signal period and whether the clock pulse counting signal is released.
[0045] In an exemplary embodiment, Figure 3 As shown, a clock synchronization method is provided, which is applied to Figure 1 The clock source node 103 in FIG. 1 is taken as an example to illustrate, and includes the following components 301 to 302, wherein:
[0046] Component 301: A chip or processor containing a timer, which may be an RTC (Real Time Clock) chip containing a crystal oscillator and an oscillator circuit, or a processor that receives timing from GPS, Beidou, CDMA, IRIG-B, constant temperature crystal oscillator OCXO, or atomic clock. The chip or processor outputs a high-precision clock signal to the timer counting module.
[0047] Composition 302: timer counting module, used to obtain the timer count value and timer frequency And issue clock pulse counting signal.
[0048] In some embodiments, Figure 4 As shown, the timer counting module 302 includes a timer interface scheduling submodule 3021 and a clock pulse counting submodule 3022 .
[0049] The timer interface scheduling submodule 3021 is used to obtain the count value of the timer through the timer interface. and frequency The clock pulse counting submodule 3022 is used to count the timer value. and frequency Periodically issues a clock pulse count signal.
[0050] It should be noted that the clock pulse count signal is in the timer count value The count value compared to the last time this signal was issued The increment Timer frequency reached The clock pulse count frequency Ratio When released, the clock pulse count frequency Counts the clock pulse period The reciprocal of For example, the timer count value when the clock pulse count signal was issued last time is is 1000, the timer frequency The clock pulse count cycle is 1MHz. If the timer count value of the clock pulse count signal is 10ms, Should be 11000.
[0051] In an exemplary embodiment, Figure 5 As shown, a clock synchronization method is provided, which is applied to Figure 1 The subsystem node 102 in FIG. 1 is taken as an example to illustrate, including components 401 to 402, wherein:
[0052] Composition 401: Timing advancement module, used to count signals according to clock pulses Controlling the local simulation clock Specifically, the clock source node 103 issues a clock pulse count signal starting from 0 and increments. The timing advancement module 401 receives the signal and writes it into the local simulation clock , clock pulse counting signal According to the increment of the clock pulse counting cycle T, the local simulation clock It also increases according to the clock pulse counting cycle T.
[0053] Component 402: Functional simulation module, used to simulate and implement the functions of the simulation training equipment subsystem, and advance the simulation according to the local simulation clock. For example, the functional simulation module of the flight performance simulation subsystem node has the ability to simulate the aircraft flight performance, power plant performance, aerodynamic effects, special situation phenomena, handling characteristics and flight qualities. Functional simulation module 402 is based on the local simulation clock The data of the next beat is calculated through a mathematical model.
[0054] In an exemplary embodiment, Figure 6 As shown, a clock synchronization method is provided, which is applied to Figure 1 The main simulation node 101 in the example is used for explanation, and includes a component 501, wherein:
[0055] Component 501: a clock scheduling module, for receiving the clock pulse count signal of the clock source node and the local simulation clock of each subsystem node, calculating the difference between the clock pulse count signal and the local simulation clock as the system synchronization error of each subsystem, and controlling the clock pulse count signal period and the release of the clock pulse count signal.
[0056] In some embodiments, when the number of subsystem nodes is n, the working logic of the clock scheduling module 501 can be as follows: Figure 7 As shown. Combined Figure 7, based on the clock pulse counting signal Local simulation clock of each subsystem node The difference between the two determines the system synchronization error of each subsystem node ,in . According to the system synchronization error of each subsystem node Size, determine the scaling . According to the scaling For the basic cycle Zoom in or out to determine the next clock pulse counting signal cycle .
[0057] It should be noted that the basic cycle A unified simulation cycle is set for simulation training equipment to ensure real-time training. To ensure the effectiveness of training, it is usually set to 10ms.
[0058] Furthermore, in an exemplary embodiment, Figure 8 As shown, a clock synchronization method is provided, which is applied to Figure 7 Scaling in Take this as an example to illustrate. According to the system synchronization error of each subsystem node Size, take the largest system synchronization error among all subsystem nodes With scaling cycle number The ratio of the scaling cycle The number of beats required to complete the clock synchronization of the subsystem with misaligned clock beats can be customized by the user. and the basic cycle The product of Add together to get the clock pulse counting period For example, take the base period 10ms, defines the number of scaling cycles =10, that is, after 10 clock beats, the subsystem nodes with delay will re-complete clock synchronization. When it is 5, the maximum delay in the current subsystem node is 5 clock beats, and the scaling ratio is calculated. is 0.5, the clock pulse count cycle for ms.
[0059] Optionally, Figure 6The clock scheduling module 501 in the embodiment may include comparing the system synchronization error with the maximum allowable error of the system, and when the system synchronization error exceeds the maximum allowable error of the system, controlling the clock source node to stop issuing the clock pulse counting signal. The maximum allowable error of the system is the maximum clock synchronization error that does not affect the normal operation and training of the simulation training device.
[0060] In an exemplary embodiment, Fig. 9 As shown, a clock synchronization method is provided, which can be applied to another simulation training equipment environment. Figure 1 The difference between the application environments shown is that the main simulation node 101 and the clock source node 103 exist in the same device, which can be an industrial computer, a server, or a micro industrial computer. At this time, the communication between the main simulation node 101 and the clock source node 103 can be achieved through a switch or through local memory reading and writing.
[0061] In some embodiments, Fig.10 As shown, a clock synchronization device for a simulation training device is provided, comprising:
[0062] A timer counting module 601 is used to obtain a timer count value and a timer frequency and issue a clock pulse count signal;
[0063] The timing advancement module 602 is used to control the local simulation clock beat to advance one step according to the clock pulse counting signal;
[0064] Functional simulation module 603, used to simulate and implement the subsystem functions of the simulated training device, and advance the simulation according to the local simulation clock;
[0065] The clock scheduling module 604 is used to control the period of the clock pulse counting signal and the issuance of the clock pulse counting signal.
[0066] In some embodiments, the timer counting module 601 is also used to obtain the count value and frequency of the timer through the timer interface; and to publish a clock pulse counting signal when the timer count value reaches the ratio of the timer frequency to the clock pulse counting frequency according to the count value and frequency cycle of the timer.
[0067] In some embodiments, the timing advancement module 602 is further configured to receive an incremented clock pulse count signal and write the incremented clock pulse count signal into the local simulation clock.
[0068] In some embodiments, the clock scheduling module 604 is also used to receive the clock pulse count signal of the clock source node and the local simulation clock of each subsystem node, and calculate the system synchronization error of each subsystem by subtracting the clock pulse count signal from the local simulation clock; calculate the scaling ratio by taking the ratio of the maximum system synchronization error in each subsystem and the number of scaling cycles; and calculate the clock pulse count cycle by superimposing the product of the scaling ratio and the basic cycle with the basic cycle.
[0069] In some embodiments, the clock scheduling module 604 is further used to compare the system synchronization error with the maximum allowable error of the system, and when the system synchronization error exceeds the maximum allowable error of the system, control the clock source node to stop issuing the clock pulse counting signal.
[0070] The above-mentioned clock synchronization device deploys a timer counting module at the clock source node, obtains the timer counting value and timer frequency, and publishes a clock pulse counting signal; the subsystem node receives the clock pulse counting signal as the local simulation clock to promote the subsystem simulation, and forwards the local simulation clock; the clock scheduling module is deployed at the main simulation node to control the clock pulse counting signal period and whether the clock pulse counting signal is released, so that the subsystem node simulation is synchronized. Therefore, the main simulation node controls the precise clock pulse counting signal released by the clock source node, and each subsystem node receives the clock pulse counting signal to promote the subsystem simulation operation. When a subsystem has a delay, the main simulation node controls the clock source node to extend the period of issuing the clock pulse counting signal, which can ensure the consistency of the local simulation clocks between multiple subsystems and effectively ensure the safe operation of the simulation training equipment.
[0071] Each module in the above clock synchronization device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.
[0072] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present invention.
[0073] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.
Claims
1. A method for synchronizing a clock of a simulation training device, characterized in that: The method comprises: Step 1: Deploy a timer counting module on the clock source node to obtain the timer count value and timer frequency and publish a clock pulse counting signal; Step 2: The subsystem node receives the clock pulse count signal as the local simulation clock to advance the subsystem simulation, and forwards the local simulation clock; Step 3: Deploy a clock scheduling module on the main simulation node to control the clock pulse counting signal period and whether the clock pulse counting signal is released, so that the subsystem node simulation is synchronized.
2. The method for synchronizing the clock of a simulation training device according to claim 1, characterized in that: In step one, the clock source node includes a chip or processor containing a timer; the timer counting module includes a timer interface scheduling submodule and a clock pulse counting submodule; the timer interface scheduling submodule is used to obtain the count value and frequency of the timer through the timer interface; the clock pulse counting submodule is used to publish a clock pulse counting signal according to the count value and frequency period of the timer.
3. The method for synchronizing the clock of a simulation training device according to claim 1, characterized in that: In step 1, the clock pulse counting signal is issued by the clock pulse counting submodule when the timer count value reaches the ratio of the timer frequency to the clock pulse counting frequency; the clock pulse counting frequency is the inverse of the clock pulse counting period.
4. The method for synchronizing the clock of a simulation training device according to claim 1, characterized in that: In step 2, the subsystem node deploys a function simulation module and a timing advancement module; The functional simulation module is used to simulate and implement the subsystem functions of the simulation training device, and to advance the simulation according to the local simulation clock; The timing advancement module is used to control the local simulation clock beat to advance one step according to the clock pulse counting signal; the local simulation clock includes a clock beat that controls the operation of the functional simulation module. If the local clock beat advances one step, the functional simulation module runs a simulation of one beat.
5. The method for synchronizing the clock of a simulation training device according to claim 1, characterized in that: In step three, when the main simulation node meets the conditions of a chip or processor containing a timer, it can also serve as a clock source node for a simulation training device; the clock scheduling module includes calculating the system synchronization error of each subsystem by receiving the clock pulse count signal of the clock source node and the local simulation clock of each subsystem node; the system synchronization error is the difference between the clock pulse count signal of the clock source node and the local simulation clock of the subsystem node.
6. The method for synchronizing the clock of a simulation training device according to claim 3, characterized in that: The clock pulse counting cycle is calculated by adjusting the scaling ratio of the basic cycle according to the size of the system synchronization error; the basic cycle is a unified simulation cycle set by the simulation training equipment to ensure the real-time training; the scaling ratio is based on the size of the system synchronization error of each subsystem, and the ratio of the largest system synchronization error in each subsystem to the number of scaling cycles is taken; the number of scaling cycles is the number of beats required for the subsystem with misaligned clock beats to re-complete clock synchronization, and customization is supported.
7. The method for synchronizing the clock of a simulation training device according to claim 6, characterized in that: The specific calculation method of the clock pulse counting period is to superimpose the product of the scaling ratio and the basic period and the basic period.
8. The method for synchronizing the clock of a simulation training device according to claim 1, characterized in that: In step three, the clock scheduling module also includes comparing the system synchronization error with the maximum allowable error of the system. When the system synchronization error exceeds the maximum allowable error of the system, the clock source node is controlled to stop issuing the clock pulse counting signal; the maximum allowable error of the system is the maximum clock synchronization error that does not affect the normal operation and training of the simulation training equipment.
9. A clock synchronization device, characterized in that: The device comprises: A timer counting module, used to obtain a timer count value and a timer frequency and issue a clock pulse counting signal; A timing advancement module, used to control the local simulation clock beat to advance one step according to the clock pulse counting signal; Functional simulation module, used to simulate and implement the subsystem functions of the simulation training equipment and advance the simulation according to the local simulation clock; The clock scheduling module is used to control the clock pulse counting signal cycle and the release of the clock pulse counting signal.