QR decomposition method and device
By using the computing unit pulsation array to decompose the channel matrix in the MU-MIMO wireless communication system, the problems of complexity of the QR decomposition algorithm and large hardware overhead are solved, and more efficient baseband signal processing is achieved, and system performance is improved.
Patent Information
- Application Number
- CN202310957437.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-31
- Publication Date
- 2025-02-18
AI Technical Summary
In the multi-user, multiple input, multiple output (MU-MIMO) wireless communication system, the complexity of the QR decomposition algorithm and hardware implementation overhead are large, resulting in a sharp increase in the complexity of baseband signal processing, which seriously restricts system performance.
The calculation unit pulsation array is adopted, including A diagonal element processing units and AB-A(A-1)/2 non-diagonal element processing units. Through this array, the channel matrix is decomposed into R matrix and QH matrix to reduce the Hardware implementation overhead.
It effectively reduces hardware implementation overhead, improves the efficiency of QR decomposition algorithm, reduces the complexity of baseband signal processing, and thus improves the performance of MU-MIMO wireless communication system.
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Figure CN119484207A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of communication technology, and in particular to a QR decomposition method and device. Background Art
[0002] With the widespread use of Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) technologies in wireless communication systems, the computational complexity of baseband signal processing algorithms has increased exponentially. In order to reliably communicate with multiple users in the same frequency band at the same time, the Multiple User Multiple Input Multiple Output (MU-MIMO) system has become the preferred solution for various future wireless communication systems. These new technologies have placed extremely high demands on baseband signal processors, especially MIMO and MU-MIMO technologies, which require baseband signal processors to complete real-time operations of a large number of matrices for the first time. As one of the most critical technologies for the next generation of mobile communication systems, massive MIMO will introduce real-time calculations of larger matrices in baseband signal processing. Compared with the matrix scale of current baseband signal processing, the matrix scale of future baseband signal processing will increase by dozens or even hundreds of times, resulting in a sharp increase in the complexity of future wireless baseband signal processing.
[0003] MU-MIMO technology will become one of the key technologies for baseband signal processing in most future wireless communications. Although it increases spectrum efficiency and data rate exponentially, the complexity of baseband signal processing algorithms will be greatly increased after the introduction of MU-MIMO technology. The real-time calculation of these complex algorithms will seriously restrict the performance of future wireless communication systems.
[0004] QR decomposition is an important part of the famous Tomlinson-Harashima Precoding (THP) precoding algorithm and the Standard Deviation (SD) algorithm. Its operation process has natural data dependence and mutual iteration, making it a bottleneck for the baseband signal processing link of MU-MIMO wireless communication. The current QR decomposition hardware results in high hardware overhead. Summary of the invention
[0005] The embodiments of the present application provide a QR decomposition method and device.
[0006] In a first aspect, an embodiment of the present application provides a QR decomposition device, comprising: a computing unit systolic array; wherein the computing unit systolic array comprises: A diagonal element processing units and AB-A(A-1) / 2 non-diagonal element processing units; wherein A is the number of processing units contained in the column with the largest number of processing units contained in the computing unit systolic array, and B is the number of processing units contained in the row with the largest number of processing units contained in the computing unit systolic array, and A and B are integers greater than or equal to 1; wherein each row in the computing unit systolic array comprises 1 of the diagonal element processing units, and the i-th row comprises Bi of the non-diagonal element processing units; wherein i is any integer from 1 to A; the computing unit systolic array is used to realize the decomposition of a channel matrix into an R matrix and a Q matrix. H matrix.
[0007] In a second aspect, an embodiment of the present application provides a QR decomposition method, comprising: decomposing a channel matrix into an R matrix and a Q matrix by a systolic array of computing units. H Matrix; wherein the computing unit systolic array includes: A diagonal element processing units and AB-A(A-1) / 2 non-diagonal element processing units; wherein A is the number of processing units contained in the column with the largest number of processing units contained in the computing unit systolic array, B is the number of processing units contained in the row with the largest number of processing units contained in the computing unit systolic array, and A and B are integers greater than or equal to 1; wherein each row in the computing unit systolic array includes 1 of the diagonal element processing units, and the i-th row includes Bi of the non-diagonal element processing units; wherein i is any integer from 1 to A.
[0008] The QR decomposition device provided in the embodiment of the present application implements QR decomposition based on a systolic array of computing units, thereby reducing hardware implementation overhead.
[0009] The QR decomposition method provided in the embodiment of the present application implements QR decomposition based on a systolic array of computing units, thereby reducing hardware implementation overhead. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 A block diagram of a QR decomposition device provided in one embodiment of the present application;
[0011] Figure 2 A schematic diagram of a QR decomposition device provided for an embodiment of the present application includes two systolic subarrays of computing units;
[0012] Figure 3 A systolic subarray of a computing unit provided in an embodiment of the present application is used to decompose two or more channel matrices into corresponding R matrices and Q matrices. H Schematic diagram of the matrix;
[0013] Figure 4 A block diagram of the composition of a diagonal element processing unit provided in an embodiment of the present application;
[0014] Figure 5 A block diagram of the composition of a non-diagonal element processing unit provided in an embodiment of the present application;
[0015] Figure 6 The composition frame of the computing subunit provided in the embodiment of the present application Figure 1 ;
[0016] Figure 7 The composition frame of the computing subunit provided in the embodiment of the present application Figure 2 ;
[0017] Figure 8 A flowchart of a QR decomposition method provided in another embodiment of the present application. DETAILED DESCRIPTION
[0018] In order to enable those skilled in the art to better understand the technical solution of the present application, the QR decomposition method and device provided by the present application are described in detail below with reference to the accompanying drawings.
[0019] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make this application thorough and complete and to enable those skilled in the art to fully understand the scope of this application.
[0020] In the absence of conflict, the embodiments of the present application and the features therein may be combined with each other.
[0021] As used herein, the term "and / or" includes any and all combinations of at least one of the associated listed items.
[0022] The terms used herein are only used to describe specific embodiments and are not intended to limit the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of at least one other feature, whole, step, operation, element, component and / or its group is not excluded.
[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.
[0024] In a wireless communication network, when a communication device is performing wireless communication, a receiving device needs to perform signal detection based on a received signal to obtain a transmitted signal. The signal detection process includes a QR decomposition process. Therefore, the QR decomposition method of an embodiment of the present application can be applied to any receiving device, and the receiving device may include a QR decomposition device.
[0025] Figure 1 A block diagram of the composition of a QR decomposition device provided in one embodiment of the present application.
[0026] First, refer to Figure 1 An embodiment of the present application provides a QR decomposition device, comprising: a computing unit systolic array 101; wherein the computing unit systolic array 101 comprises: A diagonal element processing units and AB-A(A-1) / 2 non-diagonal element processing units; wherein A is the number of processing units contained in the column with the largest number of processing units contained in the computing unit systolic array, and B is the number of processing units contained in the row with the largest number of processing units contained in the computing unit systolic array, and A and B are integers greater than or equal to 1; wherein each row in the computing unit systolic array comprises 1 diagonal element processing unit, and the i-th row comprises Bi non-diagonal element processing units; wherein i is any integer from 1 to A; the computing unit systolic array is used to realize decomposition of a channel matrix into an R matrix and a Q matrix. H matrix.
[0027] In some exemplary embodiments, the diagonal element processing unit is as follows: Figure 1 R11, R21, Rx1, Rn1, etc.
[0028] In some exemplary embodiments, the off-diagonal element processing unit is as follows Figure 1 R12,...,R1n, R22,...,R2(n-1), Rx2,...,Rx(n-x+1), Q11, Q12,...,Q1m, Q21, Q22,...,Q2m, Qx1, Qx2,...,Qxm, Qn1, Qn2,...,Qnm, etc.
[0029] In some exemplary embodiments, the computing unit systolic array includes at least one computing unit systolic subarray; each computing unit systolic subarray is used to implement decomposition of at least one channel matrix into corresponding R matrices and Q matrices. H A matrix; wherein the computing unit systolic subarray includes n diagonal element processing units and (m+n)nn(n-1) / 2 non-diagonal element processing units; wherein n is the number of processing units contained in the column with the largest number of processing units contained in the computing unit systolic subarray, and m+n is the number of processing units contained in the row with the largest number of processing units contained in the computing unit systolic subarray; n is less than or equal to A, and m+n is less than or equal to B; wherein each row in the computing unit systolic subarray includes 1 diagonal element processing unit, and the j1th row includes m-j1 non-diagonal element processing units; wherein j1 is any integer from 1 to n.
[0030] like Figure 1 As shown, the computing unit systolic array can be considered to include one computing unit systolic sub-array.
[0031] Figure 2 A schematic diagram is given by taking the example of a computing unit systolic array including two computing unit systolic sub-arrays. Figure 2 As shown, assuming that the two computing unit systolic subarrays are computing unit systolic subarray 1 and computing unit systolic subarray 2, then computing unit systolic subarray 1 is used to decompose the channel matrix H into the corresponding R0 matrix and Q0 matrix. H The matrix, the computing unit systolic subarray 2 is used to decompose the channel matrix A into the corresponding R1 matrix and Q1 H matrix.
[0032] In some exemplary embodiments, m is the number of rows of the channel matrix, and n is the number of columns of the channel matrix.
[0033] In some exemplary embodiments, Figure 1 As shown, in a computing unit, the systolic subarray is used to implement the decomposition of a channel matrix into corresponding R matrices and Q H In the case of a matrix, the diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit is used to perform real number processing and elimination processing on the first column elements of the channel matrix.
[0034] The k1th non-diagonal element processing unit in the 1st row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the k1+1th column elements of the channel matrix, and send the processed 2nd row elements to the nth row elements in the k1+1th column elements to the k1th processing unit in the 2nd row processing unit; wherein k1 is any integer from 1 to n-1.
[0035] The diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform real number processing and elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the 1st non-diagonal element processing unit in the j2-1th row; wherein j2 is any integer from 2 to n.
[0036] The k2th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th column elements in the column elements processed by the k2+1th non-diagonal element processing unit in the j2-1th row, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k2th processing unit in the j2+1th row processing unit; wherein k2 is any integer from 1 to n-j2.
[0037] The k3th non-diagonal element processing unit in the 1st row of processing units in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the k3-nth column elements of the unit matrix, and send the processed 2nd row elements to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the 2nd row of processing units; wherein k3 is any integer from n+1 to m+n.
[0038] The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the k4+1th non-diagonal element processing unit in the j2-1th row, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k4-1th processing unit in the j2+1th row processing unit; wherein k4 is any integer from n-j2+1 to m+n-j2+1.
[0039] In some exemplary embodiments, Figure 3 As shown, in a computing unit, the systolic subarray is used to decompose two or more channel matrices into corresponding R matrices and Q H In the case of a matrix, the diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit is used to perform real number processing and elimination processing on the first column elements of two or more channel matrices in a time division multiplexing manner.
[0040] The k1th non-diagonal element processing unit in the 1st row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the k1+1th column elements of two or more channel matrices in a time division multiplexing manner, and send the processed 2nd row elements to the nth row elements in the k1+1th column elements to the k1th processing unit in the 2nd row processing unit; wherein k1 is any integer from 1 to n-1.
[0041] The diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform real number processing and elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by two or more j2-1th row 1st non-diagonal element processing units in a time division multiplexing manner; wherein j2 is any integer from 2 to n.
[0042] The k2th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th column elements in the column elements processed by two or more j2-1th row and k2+1th non-diagonal element processing units in a time division multiplexing manner, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k2th processing unit in the j2+1th row processing unit; wherein k2 is any integer from 1 to n-j2.
[0043] The k3th non-diagonal element processing unit in the 1st row of processing units in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the k3-nth column elements of two or more unit matrices in a time division multiplexing manner, and send the processed 2nd row elements to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the 2nd row of processing units; wherein k3 is any integer from n+1 to m+n.
[0044] The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by two or more j2-1th row k4+1th non-diagonal element processing units in a time division multiplexing manner, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k4-1th processing unit in the j+1th row processing unit; wherein k4 is any integer from n-j2+1 to m+n-j2+1.
[0045] In some exemplary embodiments, it also includes: a controller, used to input the k5th column element of the channel matrix to the k5th processing unit in the 1st row of processing units; wherein k5 is any integer from 1 to n; and input the k6-nth column element in the unit matrix to the k6th processing unit in the 1st row of processing units; wherein k6 is any integer from n+1 to m+n.
[0046] In some exemplary embodiments, when the diagonal element processing units in the 1st row processing units in the computing unit systolic subarray perform real number processing on the 1st column elements of the channel matrix, the controller inputs the 1st column elements of the channel matrix from the 1st row elements to the mth row elements to the diagonal element processing units in the 1st row processing units in sequence, one element at a time.
[0047] In some exemplary embodiments, when the diagonal element processing unit in the 1st row processing unit in the computing unit systolic subarray performs elimination processing on the 1st column elements of the channel matrix, the diagonal element processing unit in the 1st row processing unit performs real number processing on the 1st row elements and the 2nd row elements in the 1st column elements, and then performs elimination processing according to the real number processed 1st row elements and the real number processed 2nd row elements, that is, the real number processed 2nd row elements are changed to 0; after the diagonal element processing unit in the 1st row processing unit performs real number processing on the 1st row elements and the 3rd row elements in the 1st column elements, it performs elimination processing according to the real number processed 1st row elements and the real number processed 3rd row elements, that is, the real number processed 3rd row elements are changed to 0; and so on, until the real number processed mth row elements are changed to 0.
[0048] In some exemplary embodiments, when the diagonal element processing unit in the first row processing unit in the computing unit systolic subarray performs real number processing on each element in the first column of the channel matrix, the Coordinate Rotation Digital Computer (CORDIC) algorithm is used to perform real number processing on each element, that is, the formula x is used. n+1 =x n cosθ-y n sinθ and y n+1 =y n cosθ+x n sinθ calculates the coordinates after each rotation, where (x n+1 ,y n+1 ) is the coordinate after the nth rotation, (x n ,y n ) is the coordinate before the nth rotation, θ is the angle of rotation, and during the first rotation, the real part of the element to be processed is used as the y value and the imaginary part is used as the x value.
[0049] In some exemplary embodiments, the formula x may also be used. n+1 =x n -y n tanθ and y n+1 =y n +x n tanθ calculates the coordinates after each rotation.
[0050] In some exemplary embodiments, when performing elimination processing according to the first row elements after real number processing and the third row elements after real number processing, the CORDIC algorithm can be used for elimination processing, that is, using the formula x n+1 =x n cosθ-y n sinθ and y n+1 =y n cosθ+x n sinθ calculates the coordinates after each rotation, where (x n+1 ,y n+1 ) is the coordinate after the nth rotation, (x n ,y n ) is the coordinate before the nth rotation, θ is the rotation angle, and in the first rotation, the first row of elements after real number processing is used as the y value, and the third row of elements after real number processing is used as the x value. The other elimination processing is similar and will not be repeated here.
[0051] In some exemplary embodiments, the formula x may also be used. n+1 =x n -y n tanθ and y n+1 =y n +x n tanθ calculates the coordinates after each rotation.
[0052] In some exemplary embodiments, during the real number processing and the element elimination processing, the angle θ of each rotation is sent to the next non-diagonal element processing unit.
[0053] In some exemplary embodiments, the non-diagonal element processing unit performs equivalent real number processing and equivalent element elimination processing according to the received rotation angle θ, that is, performs the same processing process as the real number processing and element elimination processing on the received elements.
[0054] In some exemplary embodiments, Figure 4 As shown, the diagonal element processing unit includes: a real numbering subunit 401, which is used to perform real numbering processing on each input element; and an elimination subunit 402, which is used to perform elimination processing on each element after the real numbering processing.
[0055] like Figure 5 As shown, the non-diagonal element processing unit includes: an equivalent real numbering subunit 501, which is used to perform equivalent real numbering processing on each input element; and an equivalent elimination subunit 502, which is used to perform equivalent elimination processing on each element after the equivalent real numbering processing.
[0056] In some exemplary embodiments, any one of the realization subunit, the elimination subunit, the equivalent realization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; wherein, Figure 6 As shown, a set of computing subunits includes: four multipliers, one adder, and one subtractor.
[0057] The two input terminals of multiplier 1 are connected to cosθ and x n The output terminal is connected to one input terminal of the subtractor, and the two input terminals of the multiplier 2 are connected to sinθ and y n The output is connected to the other input of the subtractor, and the subtractor outputs x n+1 .
[0058] The two input terminals of multiplier 3 are connected to cosθ and y n The output terminal is connected to one input terminal of the adder, and the two input terminals of the multiplier 4 are connected to sinθ and x n The output terminal is connected to the other input terminal of the adder, and the adder outputs y n+1 .
[0059] In some exemplary embodiments, any one of the realization subunit, the elimination subunit, the equivalent realization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; wherein, Figure 7 As shown, a set of computing subunits includes: two shifters, an adder, a subtractor, and at least one multiplier.
[0060] Among them, the input of shifter 1 is connected to y n The output is connected to one input of the subtractor, and the other input of the subtractor is connected to x n Connection, subtractor output x n+1 .
[0061] The input of shifter 2 is equal to x n The output is connected to one input of the adder, and the other input of the adder is connected to y n Connect, adder output y n+1 .
[0062] The QR decomposition device provided in the embodiment of the present application implements QR decomposition based on a systolic array of computing units, thereby reducing hardware implementation overhead.
[0063] Figure 8 A flowchart of a QR decomposition method provided in another embodiment of the present application.
[0064] Second, refer to Figure 8 Another embodiment of the present application provides a QR decomposition method, including:
[0065] Step 800, decomposing the channel matrix into an R matrix and a Q matrix by means of a systolic array of computing units H matrix.
[0066] The computing unit systolic array includes: A diagonal element processing units and AB-A(A-1) / 2 non-diagonal element processing units; wherein A is the number of processing units contained in the column with the largest number of processing units contained in the computing unit systolic array, B is the number of processing units contained in the row with the largest number of processing units contained in the computing unit systolic array, and A and B are integers greater than or equal to 1.
[0067] Each row in the computing unit systolic array includes one diagonal element processing unit, and the i-th row includes Bi non-diagonal element processing units; wherein i is any integer from 1 to A.
[0068] In some exemplary embodiments, the diagonal element processing unit is as follows: Figure 1 R11, R21, Rx1, Rn1, etc.
[0069] In some exemplary embodiments, the off-diagonal element processing unit is as follows Figure 1 R12,...,R1n, R22,...,R2(n-1), Rx2,...,Rx(n-x+1), Q11, Q12,...,Q1m, Q21, Q22,...,Q2m, Qx1, Qx2,...,Qxm, Qn1, Qn2,...,Qnm, etc.
[0070] In some exemplary embodiments, the computing unit systolic array includes at least one computing unit systolic sub-array.
[0071] The channel matrix is decomposed into R matrix and Q matrix by computing unit systolic array. H The matrix includes: decomposing at least one channel matrix into corresponding R matrices and Q matrices through each computing unit systolic subarray respectively. H matrix.
[0072] The computing unit systolic subarray includes n diagonal element processing units and (m+n)nn(n-1) / 2 non-diagonal element processing units; wherein n is the number of processing units contained in the column with the largest number of processing units contained in the computing unit systolic subarray, and m+n is the number of processing units contained in the row with the largest number of processing units contained in the computing unit systolic subarray; n is less than or equal to A, and m+n is less than or equal to B.
[0073] Each row in the computing unit systolic subarray includes one diagonal element processing unit, and the j1th row includes m-j1 non-diagonal element processing units; wherein j1 is any integer from 1 to n.
[0074] like Figure 1 As shown, the computing unit systolic array can be considered to include one computing unit systolic sub-array.
[0075] Figure 2 A schematic diagram is given by taking the example of a computing unit systolic array including two computing unit systolic sub-arrays. Figure 2 As shown, assuming that the two computing unit systolic subarrays are computing unit systolic subarray 1 and computing unit systolic subarray 2, then computing unit systolic subarray 1 is used to decompose the channel matrix H into the corresponding R0 matrix and Q0 matrix. H The matrix, the computing unit systolic subarray 2 is used to decompose the channel matrix A into the corresponding R1 matrix and Q1 H matrix.
[0076] In some exemplary embodiments, m is the number of rows of the channel matrix, and n is the number of columns of the channel matrix.
[0077] In some exemplary embodiments, Figure 1 As shown, in a computing unit, the systolic subarray is used to implement the decomposition of a channel matrix into corresponding R matrices and Q H In the case of a matrix, at least one channel matrix is decomposed into corresponding R matrices and Q matrices by each computing unit systolic subarray. H The matrix includes:
[0078] The diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit performs real number processing and elimination processing on the first column elements of the channel matrix.
[0079] The k1th non-diagonal element processing unit in the 1st row processing unit in the computing unit systolic subarray performs equivalent real number processing and equivalent elimination processing on the k1+1th column elements of the channel matrix, and sends the processed 2nd row elements to the nth row elements in the k1+1th column elements to the k1th processing unit in the 2nd row processing unit; wherein k1 is any integer from 1 to n-1.
[0080] The diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray performs real number processing and elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the 1st non-diagonal element processing unit in the j2-1th row; wherein j2 is any integer from 2 to n.
[0081] The k2th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray performs equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th column elements in the column elements processed by the k2+1th non-diagonal element processing unit in the j2-1th row, and sends the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k2th processing unit in the j2+1th row processing unit; wherein k2 is any integer from 1 to n-j2.
[0082] The k3th non-diagonal element processing unit in the 1st row of processing units in the computing unit systolic subarray performs equivalent real number processing and equivalent elimination processing on the k3-nth column elements of the unit matrix, and sends the processed 2nd row elements to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the 2nd row of processing units; wherein k3 is any integer from n+1 to m+n.
[0083] The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray performs equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the k4+1th non-diagonal element processing unit in the j2-1th row, and sends the processed 2nd row elements to the n-j2+1th row elements in the column elements to the k4-1th processing unit in the j2+1th row processing unit; wherein k4 is any integer from n-j2+1 to m+n-j2+1.
[0084] In some exemplary embodiments, Figure 3 As shown, in a computing unit, the systolic subarray is used to decompose two or more channel matrices into corresponding R matrices and Q H In the case of a matrix, at least one channel matrix is decomposed into corresponding R matrices and Q matrices by each computing unit systolic subarray. H The matrix includes:
[0085] The diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit performs real number processing and elimination processing on the first column elements of two or more channel matrices in a time division multiplexing manner.
[0086] The k1th non-diagonal element processing unit in the 1st row processing unit in the computing unit systolic subarray performs equivalent real number processing and equivalent elimination processing on the k1+1th column elements of two or more channel matrices in a time division multiplexing manner, and sends the processed 2nd row elements to the nth row elements in the k1+1th column elements to the k1th processing unit in the 2nd row processing unit; wherein k1 is any integer from 1 to n-1.
[0087] The diagonal element processing unit in the j2-th row processing unit in the computing unit systolic subarray uses time division multiplexing to perform real number processing and elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by two or more j2-1th row 1st non-diagonal element processing units; wherein j2 is any integer from 2 to n.
[0088] The k2th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray uses time division multiplexing to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th column elements in the column elements processed by two or more j2-1th row k2+1th non-diagonal element processing units, and sends the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k2th processing unit in the j2+1th row processing unit; wherein k2 is any integer from 1 to n-j2.
[0089] The k3th non-diagonal element processing unit in the 1st row of processing units in the computing unit systolic subarray performs equivalent real number processing and equivalent elimination processing on the k3-nth column elements of two or more unit matrices in a time division multiplexing manner, and sends the processed 2nd row elements to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the 2nd row of processing units; wherein k3 is any integer from n+1 to m+n.
[0090] The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray uses time division multiplexing to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by two or more j2-1th row k4+1th non-diagonal element processing units, and sends the processed 2nd row elements to the n-j2+1th row elements in the column elements to the k4-1th processing unit in the j+1th row processing unit; wherein k4 is any integer from n-j2+1 to m+n-j2+1.
[0091] In some exemplary embodiments, it also includes: the controller inputs the k5th column element of the channel matrix to the k5th processing unit in the 1st row of processing units; wherein k5 is any integer from 1 to n; and inputs the k6-nth column element in the unit matrix to the k6th processing unit in the 1st row of processing units; wherein k6 is any integer from n+1 to m+n.
[0092] In some exemplary embodiments, when the diagonal element processing units in the 1st row processing units in the computing unit systolic subarray perform real number processing on the 1st column elements of the channel matrix, the controller inputs the 1st column elements of the channel matrix from the 1st row elements to the mth row elements to the diagonal element processing units in the 1st row processing units in sequence, one element at a time.
[0093] In some exemplary embodiments, when the diagonal element processing unit in the 1st row processing unit in the computing unit systolic subarray performs elimination processing on the 1st column elements of the channel matrix, the diagonal element processing unit in the 1st row processing unit performs real number processing on the 1st row elements and the 2nd row elements in the 1st column elements, and then performs elimination processing according to the real number processed 1st row elements and the real number processed 2nd row elements, that is, the real number processed 2nd row elements are changed to 0; after the diagonal element processing unit in the 1st row processing unit performs real number processing on the 1st row elements and the 3rd row elements in the 1st column elements, it performs elimination processing according to the real number processed 1st row elements and the real number processed 3rd row elements, that is, the real number processed 3rd row elements are changed to 0; and so on, until the real number processed mth row elements are changed to 0.
[0094] In some exemplary embodiments, when the diagonal element processing unit in the first row processing unit in the computing unit systolic subarray performs real number processing on each element in the first column of the channel matrix, the Coordinate Rotation Digital Computer (CORDIC) algorithm is used to perform real number processing on each element, that is, the formula x is used. n+1 =x n cosθ-y n sinθ and y n+1 =y n cosθ+x n sinθ calculates the coordinates after each rotation, where (x n+1 ,y n+1 ) is the coordinate after the nth rotation, (x n ,y n ) is the coordinate before the nth rotation, θ is the angle of rotation, and during the first rotation, the real part of the element to be processed is used as the y value and the imaginary part is used as the x value.
[0095] In some exemplary embodiments, the formula x may also be used. n+1 =x n -y n tanθ and y n+1 =y n +x n tanθ calculates the coordinates after each rotation.
[0096] In some exemplary embodiments, when performing elimination processing according to the first row elements after real number processing and the third row elements after real number processing, the CORDIC algorithm can be used for elimination processing, that is, using the formula x n+1 =x n cosθ-y n sinθ and y n+1 =y n cosθ+x n sinθ calculates the coordinates after each rotation, where (x n+1 ,y n+1 ) is the coordinate after the nth rotation, (x n ,y n ) is the coordinate before the nth rotation, θ is the rotation angle, and in the first rotation, the first row of elements after real number processing is used as the y value, and the third row of elements after real number processing is used as the x value. The other elimination processing is similar and will not be repeated here.
[0097] In some exemplary embodiments, the formula x may also be used. n+1 =x n -y n tanθ and y n+1 =y n +x n tanθ calculates the coordinates after each rotation.
[0098] In some exemplary embodiments, during the real number processing and the element elimination processing, the angle θ of each rotation is sent to the next non-diagonal element processing unit.
[0099] In some exemplary embodiments, the non-diagonal element processing unit performs equivalent real number processing and equivalent element elimination processing according to the received rotation angle θ, that is, performs the same processing process as the real number processing and element elimination processing on the received elements.
[0100] In some exemplary embodiments, Figure 4 As shown, the diagonal element processing unit includes: a real numbering subunit 401, which is used to perform real numbering processing on each input element; and an elimination subunit 402, which is used to perform elimination processing on each element after the real numbering processing.
[0101] like Figure 5 As shown, the non-diagonal element processing unit includes: an equivalent real numbering subunit 501, which is used to perform equivalent real numbering processing on each input element; and an equivalent elimination subunit 502, which is used to perform equivalent elimination processing on each element after the equivalent real numbering processing.
[0102] In some exemplary embodiments, any one of the realization subunit, the elimination subunit, the equivalent realization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; wherein, Figure 6 As shown, a set of computing subunits includes: four multipliers, one adder, and one subtractor.
[0103] The two input terminals of multiplier 1 are connected to cosθ and x n The output terminal is connected to one input terminal of the subtractor, and the two input terminals of the multiplier 2 are connected to sinθ and y n The output is connected to the other input of the subtractor, and the subtractor outputs x n+1 .
[0104] The two input terminals of multiplier 3 are connected to cosθ and y n The output terminal is connected to one input terminal of the adder, and the two input terminals of the multiplier 4 are connected to sinθ and x n The output terminal is connected to the other input terminal of the adder, and the adder outputs y n+1 .
[0105] In some exemplary embodiments, any one of the realization subunit, the elimination subunit, the equivalent realization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; wherein, Figure 7 As shown, a set of computing subunits includes: two shifters, an adder, a subtractor, and at least one multiplier.
[0106] Among them, the input of shifter 1 is connected to y n The output is connected to one input of the subtractor, and the other input of the subtractor is connected to x n Connection, subtractor output x n+1 .
[0107] The input of shifter 2 is equal to x n The output is connected to one input of the adder, and the other input of the adder is connected to y n Connect, adder output y n+1 .
[0108] The QR decomposition method provided in the embodiment of the present application implements QR decomposition based on a systolic array of computing units, thereby reducing hardware implementation overhead.
[0109] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.
[0110] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present application as set forth in the appended claims.
Claims
1. A QR decomposition device, comprising: a systolic array of computing units; The computing unit systolic array includes: A diagonal element processing units and AB-A(A-1) / 2 off-diagonal element processing units; wherein A is the number of processing units in the column with the largest number of processing units in the computing unit systolic array, B is the number of processing units in the row with the largest number of processing units in the computing unit systolic array, and A and B are integers greater than or equal to 1; Each row of the computing unit systolic array includes one diagonal element processing unit, and the i-th row includes Bi non-diagonal element processing units; wherein i is any integer from 1 to A; The computing unit systolic array is used to decompose the channel matrix into an R matrix and a Q H matrix.
2. The QR decomposition device according to claim 1, wherein: The computing unit systolic array includes at least one computing unit systolic subarray; Each of the systolic subarrays of the computing units is used to decompose at least one channel matrix into corresponding R matrices and Q matrices. H matrix; The computing unit systolic subarray includes n diagonal element processing units and (m+n)nn(n-1) / 2 off-diagonal element processing units; wherein n is the number of processing units in the column with the largest number of processing units in the computing unit systolic subarray, and m+n is the number of processing units in the row with the largest number of processing units in the computing unit systolic subarray; n is less than or equal to A, and m+n is less than or equal to B; Each row of the computing unit systolic subarray includes one diagonal element processing unit, and the j1th row includes m-j1 non-diagonal element processing units; wherein j1 is any integer from 1 to n.
3. The QR decomposition device according to claim 2, wherein: In a computing unit, the systolic subarray is used to implement the decomposition of a channel matrix into corresponding R matrices and Q H In the case of a matrix, the diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit is used to perform real number processing and elimination processing on the first column elements of the channel matrix; The k1th non-diagonal element processing unit in the 1st row processing unit in the systolic subarray of the computing unit is used to perform equivalent real number processing and equivalent elimination processing on the k1+1th column elements of the channel matrix, and send the processed 2nd row elements to the nth row elements in the k1+1th column elements to the k1th processing unit in the 2nd row processing unit; wherein k1 is any integer from 1 to n-1; The diagonal element processing unit in the j2-th row processing unit in the computing unit systolic subarray is used to perform real number processing and elimination processing on the elements in the second row to the n-j2+1-th row of the column elements processed by the first non-diagonal element processing unit in the j2-1-th row; wherein j2 is any integer from 2 to n; The k2th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th column elements in the column elements processed by the k2+1th non-diagonal element processing unit in the j2-1th row, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k2th processing unit in the j2+1th row processing unit; wherein k2 is any integer from 1 to n-j2; The k3th non-diagonal element processing unit in the 1st row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the k3-nth column elements of the unit matrix, and send the processed 2nd row elements to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the 2nd row processing unit; wherein k3 is any integer from n+1 to m+n; The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the k4+1th non-diagonal element processing unit in the j2-1th row, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k4-1th processing unit in the j2+1th row processing unit; wherein k4 is any integer from n-j2+1 to m+n-j2+1.
4. The QR decomposition device according to claim 2, wherein: In one of the computing units, the systolic subarray is used to implement the decomposition of two or more channel matrices into corresponding R matrices and Q H In the case of a matrix, the diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit is used to perform real number processing and elimination processing on the first column elements of two or more channel matrices in a time division multiplexing manner; The k1th non-diagonal element processing unit in the 1st row processing unit in the systolic subarray of the computing unit is used to perform equivalent real number processing and equivalent elimination processing on the k1+1th column elements of two or more channel matrices in a time division multiplexing manner, and send the processed 2nd row elements to the nth row elements in the k1+1th column elements to the k1th processing unit in the 2nd row processing unit; wherein k1 is any integer from 1 to n-1; The diagonal element processing unit in the j2-th row processing unit in the computing unit systolic subarray is used to perform real number processing and elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the first non-diagonal element processing unit in the j2-1-th row in a time division multiplexing manner; wherein j2 is any integer from 2 to n; The k2th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th column elements in the column elements processed by two or more j2-1th row k2+1th non-diagonal element processing units in a time division multiplexing manner, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k2th processing unit in the j2+1th row processing unit; wherein k2 is any integer from 1 to n-j2; The k3th non-diagonal element processing unit in the 1st row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the k3-nth column elements of two or more unit matrices in a time division multiplexing manner, and send the processed 2nd row elements to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the 2nd row processing unit; wherein k3 is any integer from n+1 to m+n; The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by two or more j2-1th row k4+1th non-diagonal element processing units in a time division multiplexing manner, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k4-1th processing unit in the j+1th row processing unit; wherein k4 is any integer from n-j2+1 to m+n-j2+1.
5. The QR decomposition device according to any one of claims 3 to 4, further comprising: A controller, used to input the k5th column element of the channel matrix to the k5th processing unit in the first row of processing units; wherein k5 is any integer from 1 to n; and input the k6-nth column element in the unit matrix to the k6th processing unit in the first row of processing units; wherein k6 is any integer from n+1 to m+n.
6. The QR decomposition device according to any one of claims 3 to 4, wherein: The diagonal element processing unit comprises: The real number subunit is used to perform real number processing on each input element; An elimination subunit, used for performing elimination processing on each element after the real number processing; The off-diagonal element processing unit comprises: The equivalent real number subunit is used to perform equivalent real number processing on each input element; The equivalent elimination subunit is used to perform equivalent elimination processing on each element after equivalent real number processing.
7. The QR decomposition device according to claim 6, wherein: Any one of the realization subunit, the elimination subunit, the equivalent realization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; Among them, a set of the computing subunits includes: four multipliers, an adder, and a subtractor.
8. The QR decomposition device according to claim 6, wherein: Any one of the realization subunit, the elimination subunit, the equivalent realization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; Among them, a set of the computing subunits includes: two shifters, an adder, a subtractor, and at least one multiplier.
9. A QR decomposition method, comprising: The channel matrix is decomposed into R matrix and Q matrix by computing unit systolic array. H matrix; The computing unit systolic array includes: A diagonal element processing units and AB-A(A-1) / 2 off-diagonal element processing units; wherein A is the number of processing units in the column with the largest number of processing units in the computing unit systolic array, B is the number of processing units in the row with the largest number of processing units in the computing unit systolic array, and A and B are integers greater than or equal to 1; Each row in the computing unit systolic array includes one diagonal element processing unit, and the i-th row includes Bi non-diagonal element processing units; wherein i is any integer from 1 to A.
10. The QR decomposition method according to claim 9, wherein: The computing unit systolic array includes at least one computing unit systolic subarray; The channel matrix is decomposed into R matrix and Q matrix by computing unit systolic array. H The matrix includes: At least one channel matrix is decomposed into corresponding R matrix and Q matrix by each of the systolic subarrays of the computing unit. H matrix; The computing unit systolic subarray includes n diagonal element processing units and (m+n)nn(n-1) / 2 off-diagonal element processing units; wherein n is the number of processing units in the column with the largest number of processing units in the computing unit systolic subarray, and m+n is the number of processing units in the row with the largest number of processing units in the computing unit systolic subarray; n is less than or equal to A, and m+n is less than or equal to B; Each row of the computing unit systolic subarray includes one diagonal element processing unit, and the j1th row includes m-j1 non-diagonal element processing units; wherein j1 is any integer from 1 to n.