Printed circuit board

Abstract

The present disclosure relates to a printed circuit board including: a plurality of insulating layers having a through portion; the plurality of wiring layers are respectively arranged on the plurality of insulating layers and / or arranged in the plurality of insulating layers; a plurality of via layers respectively penetrating at least a portion of a corresponding one of the plurality of insulating layers and respectively connected to a corresponding one of the plurality of wiring layers; an electronic component at least partially disposed in the through portion and embedded in at least one of the plurality of insulating layers; and an insulating film disposed in the plurality of insulating layers and covering at least a portion of a side surface of the electronic component and at least a portion of a wall surface of the through portion.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0104624 filed on August 10, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Due to the densification of circuits and the miniaturization and thinning of electronic products, technology for embedding electronic components such as semiconductor chips and passive devices in printed circuit boards is being actively studied, and a large amount of research is being conducted on substrate structures and methods related thereto.

[0004] On the other hand, when manufacturing the substrate, surface treatment is usually performed to ensure adhesion between the metal layer and the insulating layer, and since the built-in electronic components are individually set, it may not be easy to modify the surface during the substrate manufacturing operation. Therefore, reliability problems may occur due to insufficient adhesion between the electronic components and the insulating layer. Summary of the invention

[0005] An aspect of the present disclosure is to provide a printed circuit board that can ensure reliability by improving adhesion between an electronic component embedded in a substrate and an insulating layer.

[0006] One of various schemes proposed by the present disclosure is to form an insulating film covering at least a portion of an electronic component embedded in a substrate using a thin film deposition process such as an atomic layer deposition (ALD) method or a molecular vapor deposition (MVD) method in a substrate manufacturing process.

[0007] For example, according to one aspect of the present disclosure, a printed circuit board may include: a plurality of insulating layers having through portions; a plurality of wiring layers, respectively arranged on and / or in the plurality of insulating layers; a plurality of via layers, respectively penetrating at least a portion of a corresponding insulating layer in the plurality of insulating layers and respectively connected to a corresponding wiring layer in the plurality of wiring layers; an electronic component, at least partially arranged in the through portions and embedded in at least one insulating layer in the plurality of insulating layers; and an insulating film, arranged in the plurality of insulating layers and covering at least a portion of a side surface of the electronic component and at least a portion of a wall surface of the through portion.

[0008] For example, according to one aspect of the present disclosure, a printed circuit board may include: a plurality of insulating layers; a plurality of wiring layers, respectively arranged on and / or in the plurality of insulating layers; a plurality of via layers, respectively penetrating at least a portion of a corresponding insulating layer in the plurality of insulating layers and respectively connected to a corresponding wiring layer in the plurality of wiring layers; an electronic component, arranged in the plurality of insulating layers; and an insulating film, arranged in the plurality of insulating layers and covering at least a portion of at least one wiring layer in the plurality of wiring layers and at least a portion of the electronic component.

[0009] The present disclosure has the effect of providing a printed circuit board that can ensure reliability by improving adhesion between an electronic component embedded in a substrate and an insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating an example embodiment of an electronic device system; Figure 2 is a perspective view schematically illustrating an example embodiment of an electronic device; Figure 3 is a cross-sectional view schematically illustrating an example embodiment of a printed circuit board; FIG. 4A to FIG. 4J It is schematically shown Figure 3 A process cross-sectional view of an exemplary embodiment of a process for manufacturing a printed circuit board; Figure 5 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board; FIG. 6A to FIG. 6I It is schematically shown Figure 5 A process cross-sectional view of an exemplary embodiment of a process for manufacturing a printed circuit board; Figure 7 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board; and FIG. 8A to FIG. 8G It is schematically shown Figure 7 A process cross-sectional view of an exemplary embodiment of a process for manufacturing a printed circuit board. DETAILED DESCRIPTION

[0011] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer description.

[0012] Electronic Devices Figure 1is a block diagram schematically illustrating an example embodiment of an electronic device system.

[0013] Reference Figure 1 , the electronic device 1000 accommodates a mainboard 1010 therein. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the mainboard 1010. These components are also connected to other electronic components to be described below through various signal lines 1090.

[0014] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, flash memory), etc.; application processor chips, such as central processing units (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have the form of a package including the above-mentioned chips or electronic components.

[0015] The network-related components 1030 may include components that are compatible with or communicate using protocols such as: Wireless Fidelity (Wi-Fi) (such as the IEEE 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access Plus (HSPA+), High Speed ​​Downlink Packet Access Plus (HSDPA+), High Speed ​​Uplink Packet Access Plus (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G) Protocols, Fourth Generation Mobile Communication Technology (4G) Protocols, and Fifth Generation Mobile Communication Technology (5G) Protocols, as well as any other wireless standards or protocols and wired standards or protocols specified hereafter. However, the network-related component 1030 is not limited thereto, and may also include a component that is compatible with or communicates using any of a variety of other wireless standards or protocols and wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0016] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto and may also include passive components in the form of chip components for various other purposes. In addition, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0017] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, and may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition to this, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0018] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component. However, the electronic device 1000 is not limited thereto, and in addition thereto, the electronic device 1000 may also be any other electronic device capable of processing data.

[0019] Figure 2 is a perspective view schematically illustrating an example embodiment of an electronic device.

[0020] Reference Figure 2, the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components (e.g., component packages 1121), but the present disclosure is not limited thereto. The component package 1121 may have the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. Alternatively. The component package 1121 may have the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is embedded. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0021] Printed Circuit Board Figure 3 is a cross-sectional view schematically illustrating an example embodiment of a printed circuit board.

[0022] Reference Figure 3The printed circuit board 100A according to the example embodiment may include: a plurality of insulating layers 111, 112, 113, 114, and 115; a plurality of wiring layers 121, 122, 123, and 124, which are respectively disposed on and / or in the plurality of insulating layers 111, 112, 113, 114, and 115; a plurality of via layers 131, 132, and 133, which respectively penetrate at least a portion of at least one insulating layer of the plurality of insulating layers 111, 112, 113, 114, and 115 and are respectively connected to at least one of the plurality of wiring layers 121, 122, 123, and 124. In other words, the plurality of via layers 131, 132, and 133 may be They respectively penetrate at least a portion of the corresponding insulating layers among the multiple insulating layers 111, 112, 113, 114 and 115 and can be respectively connected to the corresponding wiring layers among the multiple wiring layers 121, 122, 123 and 124; an electronic component 140, which is arranged in the multiple insulating layers 111, 112, 113, 114 and 115; and insulating films 151 and 152, which are arranged in the multiple insulating layers 111, 112, 113, 114 and 115 and cover at least one insulating layer among the multiple insulating layers 111, 112, 113, 114 and 115, at least one wiring layer among the multiple wiring layers 121, 122, 123 and 124 and at least a portion of each of the electronic components 140. The plurality of insulating layers 111, 112, 113, 114, and 115 may have a through portion H1, and at least a portion of the electronic component 140 may be disposed in the through portion H1 and may be embedded in at least one of the plurality of insulating layers 111, 112, 113, 114, and 115. The insulating films 151 and 152 may cover at least a portion of each of at least one side surface of the electronic component 140 and a wall surface of the through portion H1.

[0023] The plurality of insulating layers 111, 112, 113, 114, and 115 may include: a first insulating layer 111 having a through portion H1; a second insulating layer 112 covering at least a portion of each of the first insulating layer 111 and the electronic component 140 and filling at least a portion of the through portion H1; and a third insulating layer 113 disposed on a lower surface of the second insulating layer 112. The through portion H1 may include a through cavity H1 penetrating the first insulating layer 111. The plurality of wiring layers 121, 122, 123, and 124 may include: a first wiring layer 121 and a second wiring layer 122 disposed on an upper surface and a lower surface of the first insulating layer 111, respectively; a third wiring layer 123 disposed on an upper surface of the second insulating layer 112; and a fourth wiring layer 124 disposed on a lower surface of the third insulating layer 113. The plurality of via layers 131 , 132 , and 133 may include a first via layer 131 penetrating at least a portion of the first insulating layer 111 , a second via layer 132 penetrating at least a portion of the second insulating layer 112 , and a third via layer 133 penetrating at least a portion of the third insulating layer 113 .

[0024] The electronic component 140 may have a front surface on which the pad P is provided and a rear surface opposite thereto, and the electronic component 140 may be arranged so that the front surface faces downward. The insulating films 151 and 152 may include a first insulating film 151 and a second insulating film 152. The first insulating film 151 and the second insulating film 152 may be connected to each other. The first insulating film 151 and the second insulating film 152 may be a coating formed using a thin film deposition method such as an atomic layer deposition (ALD) method or a molecular vapor deposition (MVD) method. For example, each of the first insulating film 151 and the second insulating film 152 may include a thin film having a thickness of less than 100 nm (e.g., about 1 nm to 10 nm thick), and the thin film may be an aluminum oxide film (e.g., an oxide film containing Al2O3). However, the present disclosure is not limited thereto, and each of the first insulating film 151 and the second insulating film 152 may be an oxide film including TiO2, ZnO, SiO2, etc. The first insulating film 151 may cover at least a portion of each of the upper and lower surfaces of the first insulating layer 111, the wall surface of the through cavity H1, the upper and side surfaces of the first wiring layer 121, the side surface of the second wiring layer 122, and the front, rear, and side surfaces of the electronic component 140 with a substantially constant thickness. Figure 3As shown in , the first insulating film 151 may cover a portion of the upper surface of the first wiring layer 121 that is not in contact with the via layer 132, and a portion of the first insulating film 151 disposed on the upper surface of the first wiring layer 121 is in contact with at least a portion of the via layer 132. The second insulating film 152 may cover at least a portion of each of the lower surface of the second insulating layer 112 and the lower surface of the second wiring layer 122 with a substantially constant thickness. The second insulating layer 112 may cover at least a portion of the first insulating film 151, and the third insulating layer 113 may cover at least a portion of the second insulating film 152.

[0025] In this manner, in the printed circuit board 100A according to the example embodiment, the first insulating film 151 and the second insulating film 152 may cover at least a portion of each of the electronic component 140, the first insulating layer 111, the wall surface of the through cavity H1, and the first wiring layer 121 and the second wiring layer 122, and may be at least partially disposed between the above components and the second insulating layer 112 and the third insulating layer 113. In this case, the first insulating film 151 and the second insulating film 152 may have excellent adhesion to the second insulating layer 112 and the third insulating layer 113, and thus may serve as an adhesion auxiliary layer. Therefore, reliability may be ensured by improving adhesion between the electronic component 140, the first insulating layer 111, the wall surface of the through cavity H1, the first wiring layer 121 and the second wiring layer 122, and the like, and the second insulating layer 112 and the third insulating layer 113.

[0026] Hereinafter, components of a printed circuit board 100A according to example embodiments will be described in more detail with reference to the accompanying drawings.

[0027] Each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating an inorganic filler, an organic filler, and / or a glass fiber (such as a glass fabric exemplified by glass cloth) in a resin. For example, the insulating material may be a non-photosensitive insulating material (such as a copper clad laminate (CCL), an Ajinomoto deposited film (ABF), or a prepreg (PPG)), but the present disclosure is not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material (such as a photosensitive dielectric (PID)). As a non-limiting example, the first insulating layer 111 may include a CCL, and each of the second insulating layer 112 and the third insulating layer 113 may include ABF or PPG, but the present disclosure is not limited thereto. The first insulating layer 111 may be a core layer, and each of the second insulating layer 112 and the third insulating layer 113 may be a deposited layer. The first insulating layer 111 and the second insulating layer 112 may be separated from each other by the second insulating film 152 .

[0028] Each of the fourth insulating layer 114 and the fifth insulating layer 115 may include a liquid solder resist or a film-type solder resist, but the present disclosure is not limited thereto and may include other types of insulating materials such as ABF. Each of the fourth insulating layer 114 and the fifth insulating layer 115 may have an opening that exposes at least a portion of the third wiring layer 123 and the fourth wiring layer 124, respectively, and a surface treatment layer may be formed on the exposed patterns of the third wiring layer 123 and the fourth wiring layer 124 as needed.

[0029] Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include copper (Cu), but the present disclosure is not limited thereto. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may perform various functions according to the design. For example, the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a signal pattern, a power pattern, and a ground pattern. Each of these patterns may have various forms, such as a line, a plane, and a pad. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer).

[0030] Each of the first via layer 131, the second via layer 132, and the third via layer 133 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include copper (Cu), but the present disclosure is not limited thereto. The first via layer 131 may include a through-hole. Each of the second via layer 132 and the third via layer 133 may include a micro via. The micro via may be a filled via formed by filling the via hole with a metal material or a conformal via formed by arranging a metal material along the wall surface of the via hole. The micro via may be arranged in a stacked type and / or an interlaced type. The vias of the first via layer 131, the second via layer 132, and the third via layer 133 may perform various functions according to the design of the corresponding layer. For example, the first via layer 131, the second via layer 132, and the third via layer 133 may include a ground via, a power via, and a signal via. Each of the first via layer 131, the second via layer 132, and the third via layer 133 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. Each of the first via layer 131, the second via layer 132, and the third via layer 133 may include a sputtering layer instead of an electroless plating layer, and may include both a sputtering layer and an electroless plating layer. The first via layer 131 may have a columnar shape or an hourglass shape, and the second via layer 132 and the third via layer 133 may have a shape tapered in opposite directions, but the present disclosure is not limited thereto.

[0031] The electronic component 140 may be a sheet-type component and may be an active component or a passive component. For example, the electronic component 140 may be an active component such as a memory chip, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM, flash memory), etc.; an application processor chip, such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc.; and a logic chip, such as an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc. Alternatively, the electronic component 140 may be a passive component, such as a high-frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low-temperature co-fired ceramic (LTCC) component, an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), etc. In the case where the electronic component 140 is an active component, the front surface on which the pad P is provided may be an active surface, and the rear surface on the opposite side may be a passive surface. In the case where the electronic component 140 is a passive component, an external electrode may be provided instead of the pad P, and the external electrode may include a first electrode and a second electrode respectively provided at both ends in a longitudinal direction, but the present disclosure is not limited thereto and the external electrode may be formed in various ways.

[0032] As described above, each of the first insulating film 151 and the second insulating film 152 may include a thin film having a thickness less than 100 nm (e.g., a thickness of about 1 nm to 10 nm), and as described above, the thin film may be an aluminum oxide film (e.g., an oxide film including Al2O3), but the present disclosure is not limited thereto, and alternatively, the thin film may be an oxide film including TiO2, ZnO, and / or SiO2. The first insulating film 151 and the second insulating film 152 may include substantially the same material. The first insulating film 151 may be a first adhesion auxiliary layer, and the second insulating film 152 may be a second adhesion auxiliary layer. If necessary, an additional insulating film may be formed on the second insulating layer 112 and the third insulating layer 113, for example, the additional insulating film may be formed on the upper surface of the second insulating layer 112 and the lower surface of the third insulating layer 113. At least a portion of these additional insulating films may be disposed between the second insulating layer 112 and the third wiring layer 123 and between the third insulating layer 113 and the fourth wiring layer 124, respectively, and may be used as an adhesion auxiliary layer. In addition, each of the first insulating film 151 and the second insulating film 152 may be thinner than each of the multiple insulating layers 111, 112, 113, 114 and 115 and each of the multiple wiring layers 121, 122, 123 and 124, and may include a material different from that of the multiple insulating layers 111, 112, 113, 114 and 115.

[0033] FIG. 4A to FIG. 4J It is schematically shown Figure 3 A process cross-sectional view of an exemplary embodiment of a process for manufacturing a printed circuit board.

[0034] Reference Figure 4A , a first insulating layer 111 is prepared using CCL or the like, and a through cavity H1 and a first via layer 131 are formed in the first insulating layer 111, and a first wiring layer 121 and a second wiring layer 122 are formed on the upper surface and the lower surface of the first insulating layer 111, respectively. The through cavity H1 can be formed using mechanical drilling, laser processing, sandblasting, etc. The via hole for the first via layer 131 can also be formed using mechanical drilling, laser processing, etc. The first wiring layer 121 and the second wiring layer 122 and the first via layer 131 can be formed by a circuit formation process (such as an additive process (AP), a semi-additive process (SAP), a modified semi-additive process (MSAP), or a hole sealing (TT) process, etc.).

[0035] Reference Figure 4B , a tape 210 is attached to the lower side of the first insulating layer 111. The tape 210 may be attached to the lower surface of the second wiring layer 122. The tape 210 may block the lower portion of the through cavity H1.

[0036] Reference Figure 4C, the electronic component 140 is disposed in the through cavity H1 . When the electronic component 140 is an active component, the electronic component 140 may be disposed in a face-down form such that the front surface on which the pad P is disposed is attached to the tape 210 .

[0037] Reference Figure 4D , forming the first insulating film 151. The first insulating film 151 may be formed on the tape 210 to cover at least a portion of each of the first insulating layer 111, the wall surface of the through cavity H1, the first wiring layer 121, the second wiring layer 122, and the electronic component 140. For example, the first insulating film 151 may be provided Figure 4C The first insulating film 151 may be formed using a thin film deposition method such as ALD or MVD as described above.

[0038] Reference Figure 4E , a second insulating layer 112 in which the first insulating layer 111, the first wiring layer 121, the second wiring layer 122, and the electronic component 140 are embedded is formed on the tape 210. In addition, a first film 220 (including polyethylene terephthalate (PET) or the like) may be formed on the second insulating layer 112. The second insulating layer 112 may be formed by a lamination process and may be attached to the first film 220 at the same time. The method of forming the first film 220 is not limited, and for example, the first film 220 may be formed using a lamination process.

[0039] Reference Figure 4F , remove belt 210.

[0040] Reference Figure 4G , forming the second insulating film 152. The second insulating film 152 may be formed in the region where the tape 210 is removed. The second insulating film 152 may be formed to cover at least a portion of each of the second insulating layer 112 and the second wiring layer 122. If necessary, the second insulating film 152 may be formed to further cover at least a portion of the pad P. When forming the second insulating layer 152, an insulating film may be additionally formed on the upper surface of the first film 220. The second insulating film 152 may also be formed using a thin film deposition method such as ALD or MVD as described above.

[0041] Reference Figure 4H , a third insulating layer 113 is formed on the second insulating film 152 to cover the second insulating film 152. In addition, a second film 230 (including PET, etc.) may be formed on the third insulating layer 113. The third insulating layer 113 may also be formed by a lamination process while being attached to the second film 230. The method of forming the second film 230 is not limited, and for example, the second film 230 may be formed using a lamination process.

[0042] Reference Fig. 4I, the first film 220 and the second film 230 are removed. In addition, the insulating film provided on the first film 220 is removed.

[0043] Reference Figure 4J , a third wiring layer 123 is formed on the second insulating layer 112 and a second via layer 132 is formed in the second insulating layer 112, a fourth wiring layer 124 is formed on the third insulating layer 113 and a third via layer 133 is formed in the third insulating layer 113. In addition, the fourth insulating layer 114 and the fifth insulating layer 115 are formed as the outermost layers using a solder resist or ABF, and if necessary, openings are formed in the fourth insulating layer 114 and the fifth insulating layer 115, respectively. Via holes for the second via layer 132 and the third via layer 133 may be formed using mechanical drilling, laser processing, or the like. Each of the via holes for the second via layer 132 and the third via layer 133 may penetrate a portion of the first insulating film 151 and a portion of the second insulating film 152, respectively, and therefore, a portion of each of the first wiring layer 121 and the second wiring layer 122 may be exposed from the first insulating film 151 and the second insulating film 152, respectively. In addition, the via hole for the second via layer 133 may penetrate another portion of the second insulating film 152 located on the pad P to expose the pad P from the second insulating film 152. The third and fourth wiring layers 123 and 124 and the second and third via layers 132 and 133 may be formed by the above-mentioned circuit formation process such as AP, SAP, MSAP, or TT.

[0044] The printed circuit board 100A according to the above-described exemplary embodiment may be manufactured through a series of processes, and a redundant description thereof will be omitted.

[0045] Figure 5 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board.

[0046] Reference Figure 5, compared with the printed circuit board 100A according to the above-described exemplary embodiment, in the printed circuit board 100B according to another exemplary embodiment, in the case where the electronic component 140 is an active component, the electronic component 140 may be arranged so that the front surface on which the pad P is arranged is arranged to face upward. Therefore, the first insulating film 151 may cover at least a portion of each of the upper and lower surfaces of the first insulating layer 111, the wall surface of the through cavity H1, the upper and side surfaces of the first wiring layer 121, the side surface of the second wiring layer 122, and the front and side surfaces of the electronic component 140. In addition, the second insulating layer 112 may cover at least a portion of the first insulating film 151. In addition, if necessary, the second insulating film 152 may be omitted. In this way, even when the electronic component 140 is arranged in a face-up form, the adhesive force can be improved by applying the first insulating film 151, and as a result, the reliability can be improved. The other contents are substantially the same as the above contents, and therefore the redundant description thereof will be omitted.

[0047] FIG. 6A to FIG. 6I It is schematically shown Figure 5 A process cross-sectional view of an exemplary embodiment of a process for manufacturing a printed circuit board.

[0048] Reference Fig. 6A As described above, the first insulating layer 111 is prepared using CCL or the like, and a through cavity H1 and a first via layer 131 are formed in the first insulating layer 111 , and a first wiring layer 121 and a second wiring layer 122 are formed on the upper and lower surfaces of the first insulating layer 111 , respectively.

[0049] Reference Figure 6B As described above, the tape 210 is attached to the lower side of the first insulating layer 111. The tape 210 may be attached to the lower surface of the second wiring layer 122. The tape 210 may block the lower portion of the through cavity H1.

[0050] Reference Figure 6C , the electronic component 140 is disposed in the through cavity H1. In this case, when the electronic component 140 is an active component, the electronic component 140 may be disposed in a face-up form with its rear surface attached to the tape 210.

[0051] Reference Fig.6D , forming a first insulating film 151. The first insulating film 151 may be formed to cover at least a portion of each of the first insulating layer 111, the first wiring layer 121, the second wiring layer 122, the front surface and the side surface of the electronic component 140, and the wall surface of the through cavity H1. For example, the first insulating film 151 may be provided Figure 6C210 . If necessary, the first insulating film 151 may be formed to further cover at least a portion of the pad P. The first insulating film 151 may be formed using a thin film deposition method such as ALD or MVD as described above.

[0052] Reference Fig. 6E , forming the second insulating layer 112. In addition, a first film 220 (including PET, etc.) may be formed on the second insulating layer 112. The second insulating layer 112 may be formed to cover at least a portion of each of the first insulating layer 111, the first wiring layer 121, the second wiring layer 122, the electronic component 140, and the first insulating film 151. As described above, the second insulating layer 112 may be formed by a lamination process and may be attached to the first film 220 at the same time. The method of forming the first film 220 is not limited, and for example, the first film 220 may be formed using a lamination process.

[0053] Reference Fig. 6F , remove belt 210.

[0054] Reference Figure 6G , a third insulating layer 113 is formed in the area where the tape 210 is removed. In addition, a second film 230 (including PET, etc.) may be formed on the third insulating layer 113. The third insulating layer 113 may be formed to cover at least a portion of the lower surface of each of the second insulating layer 112 and the second wiring layer 122. The third insulating layer 113 may also be formed by a lamination process and may be attached to the second film 230 at the same time. The method of forming the second film 230 is not limited, and for example, the second film 230 may be formed using a lamination process.

[0055] Reference Figure 6H , the first film 220 and the second film 230 are removed.

[0056] Reference Fig.6I As described above, the third wiring layer 123 is formed on the second insulating layer 112 and the second via layer 132 is formed in the second insulating layer 112, and the fourth wiring layer 124 is formed on the third insulating layer 113 and the third via layer 133 is formed in the third insulating layer 113. In addition, the fourth insulating layer 114 and the fifth insulating layer 115 are formed as the outermost layers using solder resist or ABF, and if necessary, openings are formed in the fourth insulating layer 114 and the fifth insulating layer 115, respectively. The via holes for the second via layer 132 and the third via layer 133 can be formed using mechanical drilling, laser processing, etc. The via hole for the second via layer 132 can penetrate a portion of the first insulating film 151, and therefore, a portion of each of the first wiring layer 121 and the pad P can be exposed from the first insulating film 151. The third wiring layer 123 and the fourth wiring layer 124 and the second via layer 132 and the third via layer 133 can be formed by the above-mentioned circuit formation process.

[0057] The printed circuit board 100B according to the above-described another exemplary embodiment may be manufactured through a series of processes, and a redundant description thereof will be omitted.

[0058] Figure 7 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board.

[0059] Reference Figure 7Compared with the printed circuit board 100A according to the above-mentioned example embodiment and the printed circuit board 100B according to another example embodiment, the printed circuit board 100C according to another example embodiment may include a through portion H2, and the through portion H2 may penetrate at least one of the plurality of second insulating layers 112a, 112b, and 112c instead of penetrating the first insulating layer 111, for example, the through portion H2 may include a blind cavity H2, and the blind cavity H2 penetrates the second-first insulating layer 112a and the second-second insulating layer 112b, and the barrier layer M is provided as a bottom surface of the blind cavity H2. The multiple insulating layers 111, 112a, 112b, 112c, 113a, 113b, 113c, 114 and 115 may include: a first insulating layer 111; a plurality of second insulating layers 112a, 112b and 112c, which are arranged on the upper surface of the first insulating layer 111 and have a through portion H2; a plurality of third insulating layers 113a, 113b and 113c, which are arranged on the lower surface of the first insulating layer 111; and a fourth insulating layer 114 and a fifth insulating layer 115, which are respectively arranged on the upper surface of the second insulating layer 112c and the lower surface of the third insulating layer 113c to form the uppermost layer and the lowermost layer of the printed circuit board 100C. The plurality of wiring layers 121, 122, 123a, 123b, 123c, 124a, 124b and 124c may include: a first wiring layer 121 and a second wiring layer 122, which are respectively arranged on the upper surface and the lower surface of the first insulating layer 111; a plurality of third wiring layers 123a, 123b and 123c, which are respectively arranged on the plurality of second insulating layers 112a, 112b and 112c and / or in the plurality of second insulating layers 112a, 112b and 112c; and a plurality of fourth wiring layers 124a, 124b and 124c, which are respectively arranged on the plurality of third insulating layers 113a, 113b and 113c and / or in the plurality of third insulating layers 113a, 113b and 113c. The plurality of via layers 131, 132a, 132b, 132c, 133a, 133b, and 133c may include: a first via layer 131 penetrating at least a portion of the first insulating layer 111; a plurality of second via layers 132a, 132b, and 132c penetrating at least a portion of a corresponding second insulating layer among the plurality of second insulating layers 112a, 112b, and 112c; and a plurality of third via layers 133a, 133b, and 133c penetrating at least a portion of a corresponding third insulating layer among the plurality of third insulating layers 113a, 113b, and 113c. The blind cavity H2 may penetrate at least one of the plurality of second insulating layers 112a, 112b, and 112c (e.g., the second-first insulating layer 112a and the second-second insulating layer 112b). The second-third insulating layer 112c may fill at least a portion of the blind cavity H2. The first wiring layer 121 may include a barrier layer M providing a bottom surface of the blind cavity H2.When the electronic component 140 is an active component, the electronic component 140 may be disposed so that the front surface on which the pad P is disposed is disposed to face upward. For example, the rear surface of the electronic component 140 may be attached to the barrier layer M using an adhesive such as a chip attach film (DAF). The insulating films 151 and 153 may include a first insulating film 151 and a third insulating film 153 disposed to be spaced apart from each other. The first insulating film 151 may cover at least a portion of each of the following surfaces: an upper surface of at least one of the plurality of second insulating layers 112a, 112b, and 112c (e.g., the second-second insulating layer 112b), a wall surface of the blind cavity H2, an upper surface of the barrier layer M, an upper surface and a side surface of at least one of the third wiring layers 123a, 123b, and 123c (e.g., the third-second wiring layer 123b), and a front surface and a side surface of the electronic component 140. The third insulating film 153 may cover at least a portion of each of the following surfaces: the lower surface of at least one of the plurality of third insulating layers 113a, 113b, and 113c (e.g., the third-second insulating layer 113b) and the lower surface and side surfaces of at least one of the plurality of fourth wiring layers 124a, 124b, and 124c (e.g., the fourth-second wiring layer 124b). At least another of the plurality of second insulating layers 112a, 112b, and 112c (e.g., the second-third insulating layer 112c) may cover at least a portion of the first insulating film 151. At least another of the plurality of third insulating layers 113a, 113b, and 113c (e.g., the third-third insulating layer 113c) may cover at least a portion of the third insulating film 153. In addition, each of the first insulating film 151 and the third insulating film 153 may be thinner than each of the plurality of insulating layers 111, 112a, 112b, 112c, 113a, 113b, 113c, 114, and 115 and each of the plurality of wiring layers 121, 122, 123a, 123b, 123c, 124a, 124b, and 124c, and may include a material different from that of the plurality of insulating layers 111, 112a, 112b, 112c, 113a, 113b, 113c, 114, and 115. Other contents are substantially the same as those described above, and thus a redundant description thereof will be omitted.

[0060] FIG. 8A to FIG. 8G It is schematically shown Figure 7 A process cross-sectional view of an exemplary embodiment of a process for manufacturing a printed circuit board.

[0061] Reference Fig. 8A, a first insulating layer 111 is prepared using CCL or the like, and a first wiring layer 121 and a second wiring layer 122 are formed on the upper surface and the lower surface of the first insulating layer 111, respectively, and a first via layer 131 is formed in the first insulating layer 111. The via hole for the first via layer 131 may be formed using mechanical drilling, laser processing, or the like. The first wiring layer 121 and the second wiring layer 122 and the first via layer 131 may be formed by a circuit forming process such as AP, SAP, MSAP, or TT. The first wiring layer 121 may include a barrier layer M. The barrier layer M may be formed together with other portions of the first wiring layer 121 by a circuit forming process.

[0062] Reference Figure 8B , through a deposition process, a second-first insulating layer 112a is formed on the upper surface of the first insulating layer 111, a third-first wiring layer 123a is formed on the upper surface of the second-first insulating layer 112a and a second-first via layer 132a is formed in the second-first insulating layer 112a, a second-second insulating layer 112b is formed on the second-first insulating layer 112a, a third-second wiring layer 123b is formed on the upper surface of the second-second insulating layer 112b and a second-second via layer 132a is formed in the second-second insulating layer 112b. 32b; a third-first insulating layer 113a is formed on the lower surface of the first insulating layer 111, a fourth-first wiring layer 124a is formed on the lower surface of the third-first insulating layer 113a and a third-first via layer 133a is formed in the third-first insulating layer 113a, a third-second insulating layer 113b is formed on the third-first insulating layer 113a, a fourth-second wiring layer 124b is formed on the lower surface of the third-second insulating layer 113b and a third-second via layer 133b is formed in the third-second insulating layer 113b. The second-first insulating layer 112a and the second-second insulating layer 112b and the third-first insulating layer 113a and the third-second insulating layer 113b may be formed by a lamination process, and the third-first wiring layer 123a and the third-second wiring layer 123b, the fourth-first wiring layer 124a and the fourth-second wiring layer 124b, the second-first via layer 132a and the second-second via layer 132b and the third-first via layer 133a and the third-second via layer 133b may be formed by the above-mentioned circuit formation process. The via hole may be formed by mechanical drilling or laser processing.

[0063] Reference Figure 8C , forming the blind cavity H2. The blind cavity H2 may be formed using the barrier layer M. For example, the blind cavity H2 may be formed by sandblasting. However, the present disclosure is not limited thereto, and the blind cavity H2 may be formed by mechanical drilling, laser processing, or etching process.

[0064] Reference Fig.8D, an electronic component 140 is disposed in the blind cavity H2. When the electronic component 140 is an active component, the electronic component 140 may be disposed face-up so that the pad P faces up. For example, the rear surface of the electronic component 140 may be attached to the upper surface of the barrier layer M using an adhesive or the like.

[0065] Reference Fig. 8E , forming a first insulating film 151 and a third insulating film 153. The first insulating film 151 may be formed to cover at least a portion of each of the second-second insulating layer 112b, the third-second wiring layer 123b, the electronic component 140, the pad P, the wall surface of the blind cavity H2, and the barrier layer M. The third insulating film 153 may cover at least a portion of each of the third-second insulating layer 113b and the fourth-second wiring layer 124b. The first insulating film 151 and the third insulating film 153 may be formed using a thin film deposition method such as ALD or MVD as described above.

[0066] Reference Figure 8F , a second-third insulating layer 112c is formed on the first insulating film 151, and a third-third insulating layer 113c is formed on the third insulating film 153. Each of the second-third insulating layer 112c and the third-third insulating layer 113c may be formed by a lamination process.

[0067] Reference Figure 8G , a third-third wiring layer 123c is formed on the second-third insulating layer 112c and a second-third via layer 132c is formed in the second-third insulating layer 112c, a fourth-third wiring layer 124c is formed on the third-third insulating layer 113c and a third-third via layer 133c is formed in the third-third insulating layer 113c. In addition, the fourth insulating layer 114 and the fifth insulating layer 115 are formed as the outermost layers using a solder resist or ABF, and if necessary, openings are formed in the fourth insulating layer 114 and the fifth insulating layer 115, respectively. Via holes for the second-third via layer 132c and the third-third via layer 133c can be formed using mechanical drilling, laser processing, etc. The via holes for the second-third via layer 132c and the third-third via layer 133c may penetrate a portion of the first insulating film 151 and the third insulating film 153, respectively, and a portion of each of the third-second wiring layer 123b and the fourth-second wiring layer 124b may be exposed from the first insulating film 151 and the third insulating film 153, respectively. In addition, the via hole for the second-third via layer 132c may penetrate another portion of the first insulating film 151 disposed on the pad P, thereby exposing a portion of the pad P from the first insulating film 151. The third-third wiring layer 123c and the fourth-third wiring layer 124c and the second-third via layer 132c and the third-third via layer 133c may be formed by the above-mentioned circuit formation process such as AP, SAP, MSAP, or TT.

[0068] The printed circuit board 100C according to the above-described example embodiment may be manufactured through a series of processes, and a redundant description thereof will be omitted.

[0069] In the present disclosure, "substantially" may be a concept including process errors or position deviations during the manufacturing process and errors during measurement. For example, when line width, spacing, thickness, height, etc. have a substantially specific value, not only the value but also values ​​similar to the value may be included. In addition, substantially coplanar may include not only a completely coplanar situation but also an approximately coplanar situation.

[0070] In the present disclosure, a cross-sectional view may indicate a view of a cross-sectional shape when an object is cut vertically, or a view showing a cross-sectional shape when the object is viewed from a side view. In addition, a plan view may indicate a view of a plane shape when an object is cut horizontally, or a view showing a plane shape when the object is viewed from a top view or a bottom view.

[0071] In the present disclosure, "lower" in the lower side, lower part and lower surface is used to refer to the downward direction relative to the cross section of the drawings, and "upper" in the upper side, upper part and upper surface is used to refer to the opposite direction thereof. However, this is to define the direction for the convenience of explanation, and the scope of rights of the claims is not particularly limited by the description of such directions, and the concepts of upper and lower may be changed at any time.

[0072] In the present disclosure, connection is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, electrical connection is a concept including both physical connection and non-physical connection. In addition, expressions such as first and second are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component.

[0073] The expression "exemplary embodiment" used in this disclosure does not mean the same embodiment, and is provided for illustrating different unique features. However, the exemplary embodiments presented above do not exclude being implemented in combination with features of other exemplary embodiments. For example, even if the contents described in a particular exemplary embodiment are not described in other exemplary embodiments, they can be understood as descriptions related to other exemplary embodiments unless there are descriptions that are contrary or contradictory to the contents in other exemplary embodiments.

[0074] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, unless they are clearly indicated as different in the context, the singular expression includes the plural expression.

[0075] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A plurality of insulating layers having through portions; A plurality of wiring layers, respectively arranged on the plurality of insulating layers and / or in the plurality of insulating layers; a plurality of via layers, each penetrating at least a portion of a corresponding insulating layer among the plurality of insulating layers and each connected to a corresponding wiring layer among the plurality of wiring layers; an electronic component, at least partially disposed in the through-portion and embedded in at least one insulating layer of the plurality of insulating layers; as well as An insulating film is provided in the plurality of insulating layers and covers at least a portion of a side surface of the electronic component and at least a portion of a wall surface of the through portion.

2. The printed circuit board according to claim 1, wherein: The insulating film covers the at least a portion of the side surface of the electronic component and the at least a portion of the wall surface of the through portion with a substantially constant thickness.

3. The printed circuit board according to claim 2, wherein: The insulating film includes an oxide film having a thickness less than 100 nm.

4. The printed circuit board according to claim 3, wherein: The oxide film includes at least one of Al2O3, TiO2, ZnO, and SiO2.

5. The printed circuit board according to claim 1, wherein The electronic component has a front surface on which a pad is provided and a rear surface opposite to the front surface, and The insulating film also covers at least a portion of the front surface of the electronic component.

6. The printed circuit board according to claim 5, wherein: The insulating film also covers at least a portion of the rear surface of the electronic component.

7. The printed circuit board according to claim 1, wherein: The insulating film also covers at least a portion of at least one wiring layer among the plurality of wiring layers.

8. The printed circuit board according to claim 7, wherein: The insulating film is in contact with at least a portion of at least one via layer among the plurality of via layers connected to the at least one wiring layer among the plurality of wiring layers.

9. The printed circuit board according to claim 1, wherein: The plurality of insulating layers include: a first insulating layer having the through-portion; a second insulating layer covering at least a portion of each of the first insulating layer and the electronic component and disposed in at least a portion of the through-portion; and a third insulating layer disposed on a lower surface of the second insulating layer. The plurality of wiring layers include: a first wiring layer and a second wiring layer, which are respectively arranged on the upper surface and the lower surface of the first insulating layer; a third wiring layer, which is arranged on the upper surface of the second insulating layer; and a fourth wiring layer, which is arranged on the lower surface of the third insulating layer. The plurality of via layers include: a first via layer penetrating at least a portion of the first insulating layer; a second via layer penetrating at least a portion of the second insulating layer; and a third via layer penetrating at least a portion of the third insulating layer, and The through portion includes a through cavity that penetrates the first insulating layer.

10. The printed circuit board according to claim 9, wherein: The electronic component has a front surface on which a pad is provided and a rear surface opposite to the front surface, and is arranged so that the front surface faces downward, The insulating film includes a first insulating film and a second insulating film connected to each other, the first insulating film covers at least a portion of each of the upper surface and the lower surface of the first insulating layer, the wall surface of the through cavity, the upper surface and the side surface of the first wiring layer, the side surface of the second wiring layer, and the front surface, the rear surface, and the side surface of the electronic component, the second insulating film covers at least a portion of each of the lower surface of the second insulating layer and the lower surface of the second wiring layer, The second insulating layer covers at least a portion of the first insulating film, and The third insulating layer covers at least a portion of the second insulating film.

11. The printed circuit board according to claim 9, wherein: The electronic component has a front surface on which a pad is provided and a rear surface opposite to the front surface, and is arranged so that the front surface faces upward, The insulating film covers at least a portion of each of the upper and lower surfaces of the first insulating layer, the wall surface of the through cavity, the upper and side surfaces of the first wiring layer, the side surface of the second wiring layer, and the front and side surfaces of the electronic component, and The second insulating layer covers at least a portion of the insulating film.

12. The printed circuit board according to claim 1, wherein: The plurality of insulating layers include: a first insulating layer; a plurality of second insulating layers disposed on an upper surface of the first insulating layer and having the through-portions; and a plurality of third insulating layers disposed on a lower surface of the first insulating layer. The plurality of wiring layers include: a first wiring layer and a second wiring layer, which are respectively arranged on the upper surface and the lower surface of the first insulating layer; a plurality of third wiring layers, which are respectively arranged on the plurality of second insulating layers and / or in the plurality of second insulating layers; and a plurality of fourth wiring layers, which are respectively arranged on the plurality of third insulating layers and / or in the plurality of third insulating layers. The plurality of via layers include: a first via layer penetrating at least a portion of the first insulating layer; a plurality of second via layers penetrating at least a portion of a corresponding second insulating layer among the plurality of second insulating layers; and a plurality of third via layers penetrating at least a portion of a corresponding third insulating layer among the plurality of third insulating layers, and The through portion includes a blind cavity that penetrates at least one second insulating layer among the plurality of second insulating layers.

13. The printed circuit board according to claim 12, wherein: The electronic component is arranged so that the front surface faces upward, The insulating film includes a first insulating film and a third insulating film that are spaced apart from each other, the first insulating film covers at least a portion of each of an upper surface of at least one of the plurality of second insulating layers, a wall surface of the blind cavity, an upper surface and a side surface of at least one of the plurality of third wiring layers, and a front surface and a side surface of the electronic component, the third insulating film covers at least a portion of each of a lower surface of at least one third insulating layer among the plurality of third insulating layers and a lower surface and a side surface of at least one fourth wiring layer among the plurality of fourth wiring layers, At least another second insulating layer of the plurality of second insulating layers covers at least a portion of the first insulating film, and At least another third insulating layer of the plurality of third insulating layers covers at least a portion of the third insulating film.

14. The printed circuit board according to claim 13, wherein: The first wiring layer includes a barrier layer, and the barrier layer serves as a bottom surface of the blind cavity. The rear surface of the electronic component is attached to the barrier layer, The first insulating film also covers at least a portion of an upper surface of the barrier layer.

15. The printed circuit board according to claim 1, wherein The insulating film is thinner than each of the plurality of insulating layers and each of the plurality of wiring layers, and includes a material different from that of the plurality of insulating layers.

16. A printed circuit board, comprising: Multiple insulation layers; A plurality of wiring layers, respectively arranged on the plurality of insulating layers and / or in the plurality of insulating layers; a plurality of via layers, each penetrating at least a portion of a corresponding insulating layer among the plurality of insulating layers and each connected to a corresponding wiring layer among the plurality of wiring layers; An electronic component disposed in the plurality of insulating layers; as well as An insulating film is provided in the plurality of insulating layers and covers at least a portion of at least one wiring layer among the plurality of wiring layers and at least a portion of the electronic component.

17. The printed circuit board according to claim 16, wherein: The electronic component is provided in at least one insulating layer among the plurality of insulating layers, the at least one wiring layer among the plurality of wiring layers includes a first wiring layer provided on an upper surface of the at least one insulating layer among the plurality of insulating layers, and The insulating film is provided with a substantially constant thickness on at least a portion of each of the upper surface and the side surface of the at least one insulating layer among the plurality of insulating layers, the surface of the electronic component in contact with the at least one insulating layer, and the upper surface and the side surface of the first wiring layer.

18. The printed circuit board according to claim 17, wherein: The insulating film includes an aluminum oxide film.

19. The printed circuit board according to claim 18, wherein The aluminum oxide film has a thickness of less than 100 nm.

20. The printed circuit board according to any one of claims 16 to 19, wherein: The insulating film is thinner than each of the plurality of insulating layers and each of the plurality of wiring layers, and includes a material different from that of the plurality of insulating layers.

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