Technological method for solving residual defect of polycrystalline silicon grid electrode of power device

Abstract

The invention discloses a process method for solving a residual defect of a polycrystalline silicon gate of a power device, which comprises the following steps of: after polycrystalline silicon deposition of a groove type gate of the power device on a wafer is completed, performing global grinding on a polycrystalline silicon layer by adopting a polycrystalline silicon grinding process until the polycrystalline silicon on the surface of an active region is completely removed; carrying out certain amount of etching on the polycrystalline silicon in the gate trench by using a microwave reaction dry etching process; the problem of etching residue of the grid polycrystalline silicon is solved, and the occurrence probability of product IGSS0 failure can be remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device technology, and in particular to a process method for solving residual defects of polysilicon gates of power devices. Background Art

[0002] Shielded Gate Trench (SGT) devices are widely used because of their low specific on-resistance and low gate-drain coupling capacitance. The gate structure of the SGT device includes shielding polysilicon and polysilicon gate. The shielding polysilicon is also commonly referred to as source polysilicon. Both are formed in the trench. According to the different settings of the shielding polysilicon and the polysilicon gate in the trench, they are usually divided into an upper and lower structure and a left and right structure. In the upper and lower structure, the shielding gate polysilicon is located at the bottom of the trench, and the polysilicon gate is located at the top of the trench. There is an insulating dielectric layer between the polysilicon gate and the shielding polysilicon to isolate them from each other.

[0003] A conventional gate process includes depositing a layer of polysilicon on the upper half of the trench to fill the trench, and then performing dry etching of the gate polysilicon. The main steps of the dry etching are: first, a preliminary etching (Breakthrough) step is performed, mainly by etching with CF4 etching gas for 10 to 18 seconds to remove a small amount of silicon oxide that may exist on the surface of the polysilicon, and then a main etching process is performed. The etching gas is Cl2 / SF6 / He. The main etching step etches the polysilicon at a faster etching rate; then the Cl2 / HBr / He etching gas is used for endpoint detection etching, and finally, the etching gas Cl2 / HBr is used in an oxygen atmosphere to perform an over-etching process to ensure that the polysilicon is etched cleanly. Since the main etching process step and the etching endpoint detection step have a large amount of etching and a long process time, defects are easily generated. The etching process still cannot ensure that the polysilicon in the trench is etched cleanly. In some cases, polysilicon residues are caused, causing the prepared device to fail.

[0004] The analysis of gate-source current IGSS0 failure cases of some low-voltage SGT products shows that there are indeed residual defects in the gate polysilicon.

[0005] The reason is that impurities in the gate polysilicon deposition and etching process easily lead to etching barriers, and the residual defects of the gate polysilicon are the main factor causing IGSSO failure. Therefore, it is necessary to ensure that the gate polysilicon is etched thoroughly. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a process method for solving the residual defects of polysilicon gate of power devices.

[0007] In order to solve the above problems, the present invention provides a process for solving residual defects of polysilicon gate of power devices, comprising: After the polysilicon deposition for making the trench gate of the power device on the wafer is completed, the polysilicon layer is first globally ground using a polysilicon grinding process until all the polysilicon on the surface of the active area is removed; then a microwave reactive dry etching process is used to etch a certain amount of polysilicon in the gate trench.

[0008] The power device is a separated gate trench type power device, the lower part of the trench is a shielding gate, and the upper part of the trench is a gate; the polysilicon layer is a polysilicon layer deposited to make the gate on the upper part of the trench.

[0009] Furthermore, the polysilicon grinding process is CMP grinding.

[0010] Furthermore, the microwave reactive dry etching process is to achieve isotropic etching by diffusing ion clusters to the wafer surface under a pressure of 0.5 Torr in the etching chamber without RF power; the etching gas and parameters are CF4 / O2=30 / 80sccm; increasing the proportion of O2 can control the reaction rate and the etching selectivity of Si / oxide layer.

[0011] Furthermore, the use of the microwave reactive dry etching method can omit the preliminary etching step and reduce the etching loss of the gate oxide layer as much as possible.

[0012] Furthermore, the microwave reactive dry etching process can reduce the height difference between the top surface of the polysilicon in the groove and the groove opening plane to within 1000Å after etching, and can further remove the gate polysilicon in the local area including the step where the source polysilicon in the active area is led out.

[0013] The process method for solving the residual defects of polysilicon gate of power device described in the present invention solves the problem of gate polysilicon etching residue and can significantly reduce the probability of IGSSO failure of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figures 1 to 3 is a schematic diagram of the process steps of the present invention, Figure 1 This is a schematic diagram after the gate polysilicon is deposited. Figure 2 This is a schematic diagram of global CMP polishing of polysilicon. Figure 3 This is a schematic diagram after microwave reactive dry etching.

[0015] Figure 4 It is a schematic diagram of the IGSSO curves of testing a device manufactured by a conventional process and a device manufactured by the process of the present invention.

[0016] Figure 5 It is a process flow chart of the present invention. DETAILED DESCRIPTION

[0017] The following is a specific implementation of the present invention in conjunction with the accompanying drawings, and the technical solutions in the present invention are clearly and completely described, but the present invention is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0018] The present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layers and zones may be exaggerated, and the same reference numerals represent the same elements from beginning to end. In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0019] The present invention provides a new process method. Aiming at the problem that the gate polysilicon cannot be completely etched cleanly in the existing process, resulting in local retention and IGSSO failure defects, the present invention improves the existing process to ensure that the gate polysilicon is completely etched without defective residues.

[0020] Specifically, the present invention is directed to a trench power device, taking a separated gate trench power device as an example, etching to form a trench, forming an isolation dielectric layer on the inner wall of the trench, depositing polysilicon and etching back, and forming a shielding electrode at the bottom of the trench; then performing a thermal oxidation process in the trench to form a gate dielectric layer, and depositing polysilicon for making a gate again, wherein the polysilicon for making a gate fills the trench and covers a certain thickness of the wafer surface at the same time, such as Figure 1 The polysilicon mentioned in the subsequent steps refers to the polysilicon deposited for making gates.

[0021] Then, the CMP grinding process of polysilicon is used to perform global grinding on the wafer until the gate polysilicon on the surface of the active area of ​​the power device is completely polished. Figure 2 shown.

[0022] The polysilicon in the trench is then etched using a microwave reactive dry etching process until the height difference between the top surface of the polysilicon in the trench and the trench opening plane is no more than 1000Å. The etching amount is controlled by the etching time. After the etching is completed, the top surface of the polysilicon is slightly lower than the trench opening. Figure 3 This etching step can further clean the polysilicon in a local area within the power device layout area, such as the step where the source end polysilicon leads out.

[0023] The microwave reaction dry etching is to achieve isotropic etching in which the ion group diffuses to the wafer surface under the action of the etching chamber with a pressure of 0.5Torr (i.e. 67Pa) without adding RF bias power. The etching gas is CF4 and O2, and the volume ratio of CF4 / O2=30 / 80sccm. The use of a higher proportion of O2 can well control the reaction rate and the etching selectivity ratio of Si: OX (oxide layer). Compared with the conventional polysilicon etching method, this etching method omits the Breakthrough (preparatory etching) step, which can reduce the etching loss of the gate oxide layer as much as possible, and the etching loss can be controlled within 50Å.

[0024] After testing the power device using the process of the present invention, the test curve is as follows: Figure 4 As shown in the figure, the IGSS0 failure rate of the device is significantly reduced.

[0025] The present invention improves the gate polysilicon etching process of the power device, solves the gate polysilicon etching residue problem, and can significantly reduce the probability of IGSS0 fail of the product.

[0026] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A process for solving residual defects of polysilicon gate of power device, characterized by: After the polysilicon deposition for making the trench gate of the power device on the wafer is completed, the polysilicon layer is first globally ground using a polysilicon grinding process until all the polysilicon on the surface of the active area is removed; then a microwave reactive dry etching process is used to etch a certain amount of polysilicon in the gate trench.

2. The process for solving the residual defects of polysilicon gate of power device according to claim 1, characterized in that: The power device is a separated gate trench type power device, the lower part of the trench is a shielding gate, and the upper part of the trench is a gate; the polysilicon layer is a polysilicon layer deposited to make the gate on the upper part of the trench.

3. The process for solving the residual defects of polysilicon gate of power device according to claim 1, characterized in that: The polysilicon grinding process is CMP grinding.

4. The process for solving the residual defects of polysilicon gate of power device according to claim 1, characterized in that: The microwave reactive dry etching process is to achieve isotropic etching by diffusing ion clusters to the wafer surface under a pressure of 0.5 Torr in an etching chamber without RF power; the etching gas and parameters are CF4 / O2=30 / 80sccm; increasing the proportion of O2 can control the reaction rate and the etching selectivity of Si / oxide layer.

5. The process for solving the residual defects of polysilicon gate of power device according to claim 4, characterized in that: The use of a microwave reactive dry etching method can omit the preliminary etching step and reduce the etching loss of the gate oxide layer as much as possible.

6. The process for solving the residual defects of polysilicon gate of power device according to claim 1, characterized in that: The microwave reactive dry etching process can reduce the recess of the polysilicon in the groove to within 1000Å after etching, where the recess refers to the height difference between the top surface of the polysilicon in the groove and the groove opening plane; and can further remove the gate polysilicon in the local area including the step where the source polysilicon in the active area is led out.

7. The process for solving the residual defects of polysilicon gate of power device according to claim 1, characterized in that: In the microwave reaction dry etching process, the etching amount is controlled by the process duration.

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