Light emitting diode with improved light emitting uniformity and preparation method thereof
By providing a plurality of small spaced first recessed holes on the surface of the epitaxial layer of the light emitting diode and providing a first electrode therein, the problem of reducing the area of the light emitting region and poor luminescence uniformity in the prior art is solved, and further High brightness uniformity.
Patent Information
- Application Number
- CN202411435985.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-02-18
AI Technical Summary
The existing light emitting diodes have a groove on the surface of the epitaxial layer that reduces the area of the light emitting region, affects the luminous luminance, and has poor luminous uniformity.
Design a light emitting diode, wherein the epitaxial layer is provided with a plurality of small spaced first concave holes on the surface of the second semiconductor layer, and each of the first electrodes is provided with a cross-sectional area of the plurality of first concave holes. The ratio to the surface area of the second semiconductor layer is less than or equal to 0.1.
By optimizing the groove design, large-area light emitting area losses are avoided, the brightness uniformity of the light emitting diode is improved, and the light emitting uniformity of the light emitting diode is improved.
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Figure CN119486403A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved light emission uniformity and a preparation method thereof. Background Art
[0002] Light Emitting Diode (LED) is a very influential new product in the optoelectronics industry. It has the characteristics of small size, long service life, rich colors and low energy consumption. It is widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.
[0003] In the related art, a light emitting diode generally includes an epitaxial layer and an electrode. The surface of the epitaxial layer has a groove exposing the semiconductor layer inside the epitaxial layer. The groove is used to set the electrode so that current can be transmitted to the semiconductor layer through the electrode.
[0004] Since grooves are formed on the surface of the epitaxial layer, the area of the light-emitting region of the epitaxial layer is reduced, thereby affecting the light-emitting brightness and causing poor uniformity of the light-emitting brightness in different regions on the epitaxial layer. Summary of the invention
[0005] The embodiment of the present disclosure provides a light emitting diode with improved light uniformity and a method for manufacturing the same, which can increase the brightness of the light emitting diode and improve the light uniformity of the light emitting diode. The technical solution is as follows:
[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes an epitaxial layer and a first electrode, the epitaxial layer including a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, the surface of the second semiconductor layer away from the first semiconductor layer has a plurality of first recessed holes exposing the first semiconductor layer, the plurality of first recessed holes are arranged at intervals, the first electrode corresponds to the first recessed holes one by one, and the first electrode is located in the corresponding first recessed hole; the ratio of the sum of the cross-sectional areas of the plurality of first recessed holes to the area of the surface of the second semiconductor layer away from the first semiconductor layer is less than or equal to 0.1.
[0007] Optionally, the light-emitting diode also includes a passivation layer and a first connecting electrode; the passivation layer is located on the surface of the second semiconductor layer away from the first semiconductor layer and in the first recessed hole, and the surface of the passivation layer away from the first semiconductor layer has a via hole exposing the first electrode; the first connecting electrode is located on the surface of the passivation layer away from the first semiconductor layer, and is connected to the first electrode through the via hole.
[0008] Optionally, the first concave hole is located in a central area of the second semiconductor layer, and a plurality of the first concave holes are arranged at intervals along the same straight line.
[0009] Optionally, the light-emitting diode also includes a plurality of second electrodes and a second connecting electrode, and the plurality of second electrodes are arranged at intervals on the surface of the second semiconductor layer away from the first semiconductor layer; the passivation layer covers the plurality of second electrodes, and the surface of the passivation layer away from the epitaxial layer also has second recessed holes corresponding to each of the second electrodes one by one, and the second recessed holes expose the corresponding second electrodes; the second connecting electrode is located on the surface of the passivation layer away from the first semiconductor layer, and is connected to the second electrode through each of the second recessed holes.
[0010] Optionally, the second recessed hole is located at a peripheral edge of the surface of the passivation layer.
[0011] Optionally, a distribution spacing between adjacent first concave holes is greater than a distribution spacing between adjacent second concave holes.
[0012] Optionally, a ratio of a distribution spacing between adjacent first concave holes to a distribution spacing between adjacent second concave holes is greater than or equal to 1.5.
[0013] Optionally, the surface of the passivation layer away from the epitaxial layer is a rectangular surface, and the cross-sectional area of the second recessed hole located in the corner region of the rectangular surface is larger than the cross-sectional area of the second recessed hole in the area of the rectangular surface other than the corner region.
[0014] On the other hand, an embodiment of the present disclosure also provides a method for preparing a light-emitting diode, the preparation method comprising: producing an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence; forming a plurality of first recessed holes exposing the first semiconductor layer on a surface of the second semiconductor layer away from the first semiconductor layer, the plurality of first recessed holes being arranged at intervals, and the ratio of the sum of the cross-sectional areas of the plurality of first recessed holes to the area of the surface of the second semiconductor layer away from the first semiconductor layer is less than or equal to 0.1; and forming a first electrode in each of the first recessed holes.
[0015] Optionally, after forming the first electrode in each of the first recessed holes, the method further includes: forming a passivation layer and a plurality of second electrodes on a surface of the second semiconductor layer away from the first semiconductor layer, the plurality of second electrodes being arranged at intervals, and the passivation layer covering the plurality of second electrodes; forming second recessed holes corresponding to each of the second electrodes one by one on a surface of the passivation layer away from the epitaxial layer, the second recessed holes exposing the corresponding second electrodes, and the second recessed holes being located at the peripheral edge of the surface of the second semiconductor layer.
[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:
[0017] The epitaxial layer in the light-emitting diode provided in the embodiment of the present disclosure is provided with a plurality of first concave holes exposing the first semiconductor layer on the surface of the second semiconductor layer, and the plurality of first concave holes are arranged at intervals on the second semiconductor layer, and a first electrode is provided in each first concave hole, so as to facilitate power supply to the first semiconductor layer through the first electrode in the first concave hole. The ratio of the sum of the cross-sectional areas of the plurality of first concave holes to the area of the surface of the second semiconductor layer away from the first semiconductor layer is less than or equal to 0.1. That is, the size of the first concave hole is designed to be smaller to avoid digging a larger light-emitting area on the epitaxial layer, thereby ensuring that the light-emitting area of the epitaxial layer is large enough.
[0018] At the same time, compared with the related art that opens a single large groove on the surface of the epitaxial layer, the embodiment of the present disclosure optimizes the centralized groove into multiple dispersed first concave holes. After such optimization, the current can be injected into different areas of the epitaxial layer through the first concave holes, making the current injection more uniform and improving the uniformity of the light emitting brightness of the light emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0020] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;
[0021] Figure 2 is a top view of a passivation layer provided by an embodiment of the present disclosure;
[0022] Figure 3 It is a flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure.
[0023] The descriptions of the marks in the figure are as follows:
[0024] 10. Substrate;
[0025] 20, epitaxial layer; 21, first semiconductor layer; 22, multi-quantum well layer; 23, second semiconductor layer; 201, first concave hole;
[0026] 31. a first electrode; 32. a second electrode;
[0027] 40. passivation layer; 41. second concave hole;
[0028] 51. a first connecting electrode; 52. a second connecting electrode;
[0029] 60. Insulation layer;
[0030] 70. Solder point block. DETAILED DESCRIPTION
[0031] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0032] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0033] Figure 1 Schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 As shown, the light-emitting diode includes an epitaxial layer 20 and a first electrode 31. The epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence. The surface of the second semiconductor layer 23 away from the first semiconductor layer 21 has a plurality of first recessed holes 201 exposing the first semiconductor layer 21. The plurality of first recessed holes 201 are arranged at intervals. The first electrodes 31 correspond to the first recessed holes 201 one by one, and the first electrodes 31 are located in the corresponding first recessed holes 201.
[0034] The ratio of the sum of the cross-sectional areas of the plurality of first recessed holes 201 to the area of the surface of the second semiconductor layer 23 away from the first semiconductor layer 21 is less than or equal to 0.1.
[0035] The epitaxial layer 20 in the light-emitting diode provided in the embodiment of the present disclosure is provided with a plurality of first concave holes 201 exposing the first semiconductor layer 21 on the surface of the second semiconductor layer 23, and the plurality of first concave holes 201 are arranged at intervals on the second semiconductor layer 23, and a first electrode 31 is provided in each first concave hole 201, so as to facilitate power supply to the first semiconductor layer 21 through the first electrode 31 in the first concave hole 201. The ratio of the sum of the cross-sectional areas of the plurality of first concave holes 201 to the area of the surface of the second semiconductor layer 23 away from the first semiconductor layer 21 is less than or equal to 0.1. That is, the size of the first concave hole 201 is designed to be smaller, so as to avoid digging a larger light-emitting area on the epitaxial layer 20, thereby ensuring that the light-emitting area of the epitaxial layer 20 is large enough.
[0036] At the same time, compared with the related art that opens a single large groove on the surface of the epitaxial layer 20, the embodiment of the present disclosure optimizes the centralized groove into a plurality of dispersed first concave holes 201. After such optimization, the current can be injected into different areas of the epitaxial layer 20 through the first concave holes 201, making the current injection more uniform and improving the uniformity of the light emitting brightness of the light emitting diode.
[0037] Optionally, the aperture of the first concave hole 201 is 2.0±0.5μm. By setting the aperture of the first concave hole 201 within the above range, the size of the first concave hole 201 can be controlled to be small enough to avoid digging out a large light-emitting area on the epitaxial layer 20, thereby ensuring that the light-emitting area of the epitaxial layer 20 is large enough.
[0038] Exemplarily, the diameter of the first concave hole 201 is 2.0 μm.
[0039] Alternatively, if Figure 1 As shown, the light emitting diode further comprises a substrate, and the epitaxial layer 20 is located on the surface of the substrate.
[0040] Optionally, the substrate is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.
[0041] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.
[0042] As an example, the first semiconductor layer 21 is a p-type layer, and the second semiconductor layer 23 is an n-type layer.
[0043] Optionally, the first semiconductor layer 21 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
[0044] Optionally, the multi-quantum well layer 22 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately. The Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different. The multi-quantum well layer 22 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers stacked alternately.
[0045] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.
[0046] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.
[0047] Optionally, the second semiconductor layer 23 is an indium-doped p-type AlInP layer. The thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
[0048] Alternatively, the first electrode 31 may include at least one of an AuBe layer, an Au layer, a Ti layer, a Ni layer, and a Pt layer.
[0049] Among these metal layers, the AuBe layer, the Au layer and the Ti layer have good conductivity, can improve the conductivity of the electrode, and are beneficial to current injection.
[0050] Among these metal layers, the Ni layer and the Pt layer have good etching resistance and toughness. During the etching process, the metal Ni layer can prevent the electrode from being corroded and improve the reliability of the electrode.
[0051] Illustratively, in a direction away from the epitaxial layer 20 , the first electrode 31 includes a stacked AuBe layer, an Au layer, a Ti layer, and a Ni layer.
[0052] In this way, the AuBe layer and the Au layer with good conductivity are arranged in the first two layers, which is conducive to current injection. The Ti layer has good adhesion, so that the Ni layer and the Au layer can be adhered together. The Ni layer is used as the last layer, which takes advantage of the good etching resistance and toughness of the Ni layer to prevent the electrode from being corroded through the Ni layer, thereby improving the reliability of the electrode.
[0053] Exemplarily, the AuBe layer has a thickness of 800 angstroms to 1200 angstroms. As an example, the AuBe layer has a thickness of 1000 angstroms.
[0054] Exemplarily, the thickness of the Au layer is 800 angstroms to 1200 angstroms. As an example, the thickness of the Au layer is 900 angstroms.
[0055] Exemplarily, the thickness of the Ti layer is 300 angstroms to 700 angstroms. As an example, the thickness of the Ti layer is 500 angstroms.
[0056] Exemplarily, the thickness of the Ni layer is 2000 angstroms to 4000 angstroms. As an example, the thickness of the Ni layer is 3000 angstroms.
[0057] Alternatively, if Figure 1 As shown, the light emitting diode further includes a passivation layer 40 and a first connection electrode 51. The passivation layer 40 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21 and in the first concave hole 201. The surface of the passivation layer 40 away from the first semiconductor layer 21 has a via hole exposing the first electrode 31.
[0058] like Figure 1 As shown, part of the film layer of the passivation layer 40 extends into the first concave hole 201 , and the via hole of the passivation layer 40 is also located in the first concave hole 201 .
[0059] like Figure 1 As shown, the first connection electrode 51 is located on a surface of the passivation layer 40 away from the first semiconductor layer 21 , and the first connection electrode 51 is connected to the first electrode 31 through a via hole.
[0060] Since the size of the first recessed hole 201 is too small, in order to realize electrical connection between the first electrode 31 and an external power source, a first connecting electrode 51 is designed on the surface of the passivation layer 40 so that the first connecting electrode 51 enters the first recessed hole 201 and is electrically connected to the first electrode 31, thereby leading the first electrode 31 to the top of the passivation layer 40, so as to facilitate subsequent power supply to the first electrode 31.
[0061] At the same time, since there are multiple first recessed holes 201, the first connecting electrode 51 is extended into each first recessed hole 201 at the same time, so that multiple first electrodes 31 can be connected to the first connecting electrode 51. When power is subsequently supplied to the multiple first electrodes 31, it can be directly supplied to the first connecting electrode 51.
[0062] Exemplarily, the passivation layer 40 may be a distributed Bragg reflector (DBR) layer or a silicon oxide layer.
[0063] Exemplarily, the first connection electrode 51 may be a metal trace, the width of the metal trace may be greater than or equal to the aperture of the first recessed hole 201 , and the ratio of the width of the metal trace to the aperture of the first recessed hole 201 is 1 to 1.2.
[0064] Exemplarily, the ratio of the width of the metal trace to the aperture of the first recessed hole 201 is 1.1.
[0065] In this way, the width of the metal wiring is just larger than the first concave hole 201 to cover the first concave hole 201, and the width of the metal wiring is not too large to cover the epitaxial layer 20 and absorb more light to ensure the light emitting effect of the light emitting diode.
[0066] Alternatively, the first connection electrode 51 may include at least one of an Au layer, a Ti layer, a Ni layer, and a Pt layer.
[0067] Exemplarily, in a direction away from the epitaxial layer 20 , the first connection electrode 51 includes an Au layer, a Ti layer, and a Ni layer stacked one on another.
[0068] Exemplarily, the thickness of the Au layer is 800 angstroms to 1000 angstroms. As an example, the thickness of the Au layer is 900 angstroms.
[0069] Exemplarily, the thickness of the Ti layer is 300 angstroms to 600 angstroms. As an example, the thickness of the Ti layer is 300 angstroms.
[0070] Exemplarily, the thickness of the Ni layer is 2000 angstroms to 3000 angstroms. As an example, the thickness of the Ni layer is 2000 angstroms.
[0071] Figure 2 FIG. 4 is a top view of a passivation layer 40 provided in an embodiment of the present disclosure. Figure 2 As shown, the first concave hole 201 is located in the central area of the second semiconductor layer 23, and a plurality of first concave holes 201 are arranged at intervals along the same straight line.
[0072] For example, Figure 2 As shown, four first concave holes 201 are provided on the second semiconductor layer 23 , and the four first concave holes 201 are arranged at intervals along the same straight line.
[0073] In this way, the plurality of first concave holes 201 are arranged along the same straight line at intervals, so that the first connection electrodes 51 located above the first concave holes 201 can also be arranged along the straight line. That is, the first connection electrodes 51 are in the shape of long strips, thereby reducing the area covered by the first connection electrodes 51 on the epitaxial layer 20 and reducing the light absorption of the first connection electrodes 51.
[0074] At the same time, the first concave hole 201 is arranged in the middle area, so that the area where the epitaxial layer 20 injects current is concentrated in the center, which can effectively ensure the light-emitting effect of the light-emitting diode.
[0075] Alternatively, if Figure 1 As shown, the light emitting diode further includes a plurality of second electrodes 32 and a second connecting electrode 52 . The plurality of second electrodes 32 are arranged at intervals on a surface of the second semiconductor layer 23 away from the first semiconductor layer 21 .
[0076] like Figure 1 As shown, the passivation layer 40 covers the plurality of second electrodes 32 , and the surface of the passivation layer 40 away from the epitaxial layer 20 further has second recesses 41 corresponding to each second electrode 32 , and the second recesses 41 expose the corresponding second electrodes 32 .
[0077] like Figure 1 As shown, the second connection electrode 52 is located on the surface of the passivation layer 40 away from the first semiconductor layer 21 , and is connected to the second electrode 32 through each second recessed hole 41 .
[0078] In the disclosed embodiment, a second electrode 32 is provided on the surface of the second semiconductor layer 23 and a passivation layer 40 covers the second electrode 32 . A second recessed hole 41 exposing the second electrode 32 is provided on the passivation layer 40 so that the second connecting electrode 52 can be connected to the second electrode 32 through the second recessed hole 41 .
[0079] There are a plurality of second concave holes 41 , which are arranged at intervals, so that the second connection electrode 52 can inject current into different regions of the second electrode 32 through different second concave holes 41 , thereby improving the uniformity of current injection.
[0080] Alternatively, the second electrode 32 may include at least one of an AuBe layer, an Au layer, a Ti layer, a Ni layer, and a Pt layer.
[0081] Among these metal layers, the AuBe layer, the Au layer and the Ti layer have good conductivity, can improve the conductivity of the electrode, and are beneficial to current injection.
[0082] Among these metal layers, the Ni layer and the Pt layer have good etching resistance and toughness. During the etching process, the metal Ni layer can prevent the electrode from being corroded and improve the reliability of the electrode.
[0083] Illustratively, in a direction away from the epitaxial layer 20 , the second electrode 32 includes a stacked AuBe layer, an Au layer, a Ti layer, and a Ni layer.
[0084] In this way, the AuBe layer and the Au layer with good conductivity are arranged in the first two layers, which is conducive to current injection. The Ti layer has good adhesion, so that the Ni layer and the Au layer can be adhered together. The Ni layer is used as the last layer, which takes advantage of the good etching resistance and toughness of the Ni layer to prevent the electrode from being corroded through the Ni layer, thereby improving the reliability of the electrode.
[0085] Exemplarily, the AuBe layer has a thickness of 800 angstroms to 1200 angstroms. As an example, the AuBe layer has a thickness of 1000 angstroms.
[0086] Exemplarily, the thickness of the Au layer is 800 angstroms to 1200 angstroms. As an example, the thickness of the Au layer is 900 angstroms.
[0087] Exemplarily, the thickness of the Ti layer is 300 angstroms to 700 angstroms. As an example, the thickness of the Ti layer is 500 angstroms.
[0088] Exemplarily, the thickness of the Ni layer is 2000 angstroms to 4000 angstroms. As an example, the thickness of the Ni layer is 3000 angstroms.
[0089] Alternatively, the second connection electrode 52 may include at least one of an Au layer, a Ti layer, a Ni layer, and a Pt layer.
[0090] Exemplarily, in a direction away from the epitaxial layer 20 , the second connection electrode 52 includes an Au layer, a Ti layer, and a Ni layer stacked one on another.
[0091] Exemplarily, the thickness of the Au layer is 800 angstroms to 1000 angstroms. As an example, the thickness of the Au layer is 900 angstroms.
[0092] Exemplarily, the thickness of the Ti layer is 300 angstroms to 600 angstroms. As an example, the thickness of the Ti layer is 300 angstroms.
[0093] Exemplarily, the thickness of the Ni layer is 2000 angstroms to 3000 angstroms. As an example, the thickness of the Ni layer is 2000 angstroms.
[0094] Alternatively, if Figure 2 As shown, the second concave holes 41 are located at the peripheral edge of the surface of the passivation layer 40. In the embodiment of the present disclosure, since a large number of the second concave holes 41 are provided, the distribution area of the second concave holes 41 is set at the edge of the epitaxial layer 20 to avoid the second concave holes 41 occupying too much of the central area of the epitaxial layer 20, so as to ensure the luminous brightness of the epitaxial layer 20.
[0095] At the same time, the second concave holes 41 are distributed at the peripheral edge of the epitaxial layer 20, while the first concave holes 201 are distributed at the middle area of the epitaxial layer 20. In this way, the current injected into the epitaxial layer 20 will cross the peripheral edge and the middle area of the epitaxial layer 20, that is, the current will flow more evenly in the epitaxial layer 20, thereby improving the brightness uniformity of the light-emitting diode.
[0096] Alternatively, if Figure 2 As shown, the distribution pitch of adjacent first recessed holes 201 is greater than the distribution pitch of adjacent second recessed holes 41 .
[0097] Optionally, a ratio of a distribution spacing between adjacent first recessed holes 201 to a distribution spacing between adjacent second recessed holes 41 is greater than or equal to 1.5.
[0098] Exemplarily, the ratio of the distribution spacing between adjacent first recessed holes 201 to the distribution spacing between adjacent second recessed holes 41 is 2.
[0099] In the above implementation, the distribution spacing of the first concave holes 201 is larger than the distribution spacing of the second concave holes 41, that is, the distribution of the first concave holes 201 is more sparse, and the distribution of the second concave holes 41 is more dense. In this way, the number of first concave holes 201 set on the epitaxial layer 20 is relatively small, so as to avoid too many grooves in the middle area of the epitaxial layer 20, thereby losing a large light-emitting area. If the second concave holes 41 are arranged at the edge, a relatively large number of them can be set to improve the injection efficiency of the current and make the current injection more uniform.
[0100] Alternatively, if Figure 2 As shown, the surface of the passivation layer 40 away from the epitaxial layer 20 is a rectangular surface, and the cross-sectional area of the second recessed hole 41 located in the corner region of the rectangular surface is larger than the cross-sectional area of the second recessed hole 41 in the area other than the corner region of the rectangular surface.
[0101] For example, Figure 2 As shown, the cross-sectional areas of the four second recessed holes 41 distributed at the four corners of the surface of the passivation layer 40 are larger than the cross-sectional area of the second recessed holes 41 distributed near the side edges of the surface of the passivation layer 40 .
[0102] Since the luminous intensity of the corner area of the light-emitting diode is usually the weakest, a second concave hole 41 of a larger size is provided in the corner area, so that the epitaxial layer 20 loses less luminous area and does not affect the luminous brightness. At the same time, the second concave hole 41 provided in the corner area is larger in size, so that the current is more easily injected into the corner area, thereby improving the luminous intensity of the corner area of the epitaxial layer 20.
[0103] Exemplarily, the cross-sectional area of the second recessed hole 41 located in the corner region of the rectangular surface is twice the cross-sectional area of the second recessed hole 41 in the region other than the corner region of the rectangular surface.
[0104] Optionally, the second recessed hole 41 may have a diameter of 3.0±1.5 μm. For example, the second recessed hole 41 located at the corner region of the rectangular surface has a diameter of 4.0±0.5 μm, and the second recessed hole 41 located in the area other than the corner region of the rectangular surface has a diameter of 2.0±0.5 μm.
[0105] Alternatively, if Figure 1 As shown, the light emitting diode further includes: two solder joint blocks 70 and an insulating layer 60, wherein the insulating layer 60 is located on the surface of the passivation layer 40 and covers the first connecting electrode 51 and the second connecting electrode 52, and the insulating layer 60 has through holes respectively exposing the first connecting electrode 51 and the second connecting electrode 52.
[0106] like Figure 1 As shown, two soldering blocks 70 are located on the insulating layer 60 , and the two soldering blocks 70 are connected to the first connecting electrode 51 and the second connecting electrode 52 through the through holes on the insulating layer 60 .
[0107] For example, in the embodiment of the present disclosure, the insulating layer 60 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.
[0108] For example, the solder joint block 70 may include a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer, and a Ti layer stacked in sequence, and the thickness of each metal layer is 30 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 500 angstroms, 2000 angstroms, and 500 angstroms, respectively.
[0109] Figure 3 is a flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure. Figures 1 to 2 The light emitting diode shown. Figure 3 As shown, the preparation method comprises:
[0110] S11: preparing an epitaxial layer 20 .
[0111] The epitaxial layer 20 is prepared on the substrate.
[0112] Exemplarily, the epitaxial layer 20 may include a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 sequentially stacked on the substrate. The first semiconductor layer 21 has a first conductivity type, the second semiconductor layer 23 has a second conductivity type different from the first conductivity type, and the multi-quantum well layer 22 is used to generate light through electron-hole recombination.
[0113] One of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.
[0114] As an example, the first semiconductor layer 21 is a p-type layer, and the second semiconductor layer 23 is an n-type layer.
[0115] The step S11 of making an epitaxial wafer may include the following steps:
[0116] The first step is to provide a GaAs wafer.
[0117] In the second step, a second semiconductor layer 23, a multi-quantum well layer 22 and a first semiconductor layer 21 are grown in sequence on the GaAs wafer.
[0118] For example, the second semiconductor layer 23 may be an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
[0119] Exemplarily, the first semiconductor layer 21 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
[0120] Optionally, the multi-quantum well layer 22 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately. The Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different. The multi-quantum well layer 22 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers stacked alternately.
[0121] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.
[0122] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.
[0123] In the second step, an etching stop layer may be grown before growing the second semiconductor layer 23 , and an AlInP carrier confinement layer may be grown before growing the multi-quantum well layer 22 .
[0124] A GaP window layer may be further grown after the first semiconductor layer 21 is grown, wherein the thickness of the GaP window layer is 10000 angstroms to 20000 angstroms.
[0125] Exemplarily, the thickness of the GaP window layer is 3 μm.
[0126] In the third step, a bonding layer is formed between the first semiconductor layer 21 and the sapphire substrate, the epitaxial layer 20 is bonded to the sapphire substrate, and the GaAs wafer is removed to obtain an epitaxial wafer.
[0127] Since the sapphire substrate has a relatively high light transmittance, and the sapphire material is relatively hard and has relatively stable chemical properties, the use of a sapphire substrate can make the light-emitting diode have good light-emitting effect and stability.
[0128] Specifically, the process may include: coating silicon oxide liquid on the surface of the second semiconductor layer 23, placing a sapphire substrate on the surface of the second semiconductor layer 23, and heating the epitaxial wafer to heat and solidify the silicon oxide liquid to form a bonding layer between the second semiconductor layer 23 and the sapphire substrate.
[0129] Optionally, the heating temperature of the epitaxial wafer is 250° C. to 350° C. Exemplarily, the heating temperature may be 300° C.
[0130] Step S12 : forming a plurality of first recessed holes 201 exposing the first semiconductor layer 21 on a surface of the second semiconductor layer 23 away from the first semiconductor layer 21 .
[0131] The plurality of first recessed holes 201 are arranged at intervals, and the ratio of the sum of the cross-sectional areas of the plurality of first recessed holes 201 to the area of the surface of the second semiconductor layer 23 away from the first semiconductor layer 21 is less than or equal to 0.1.
[0132] For example, Figure 2 As shown, the first concave hole 201 is located in the central area of the second semiconductor layer 23, and a plurality of first concave holes 201 are arranged at intervals along the same straight line.
[0133] Step S13 : forming a first electrode 31 in each first recess 201 .
[0134] Alternatively, the first electrode 31 may include at least one of an AuBe layer, an Au layer, a Ti layer, a Ni layer, and a Pt layer.
[0135] Illustratively, in a direction away from the epitaxial layer 20 , the first electrode 31 includes a stacked AuBe layer, an Au layer, a Ti layer, and a Ni layer.
[0136] Exemplarily, the AuBe layer has a thickness of 800 angstroms to 1200 angstroms. As an example, the AuBe layer has a thickness of 1000 angstroms.
[0137] Exemplarily, the thickness of the Au layer is 800 angstroms to 1200 angstroms. As an example, the thickness of the Au layer is 900 angstroms.
[0138] Exemplarily, the thickness of the Ti layer is 300 angstroms to 700 angstroms. As an example, the thickness of the Ti layer is 500 angstroms.
[0139] Exemplarily, the thickness of the Ni layer is 2000 angstroms to 4000 angstroms. As an example, the thickness of the Ni layer is 3000 angstroms.
[0140] Step S14 : forming a passivation layer 40 and a plurality of second electrodes 32 on a surface of the second semiconductor layer 23 away from the first semiconductor layer 21 . The plurality of second electrodes 32 are arranged at intervals, and the passivation layer 40 covers the plurality of second electrodes 32 .
[0141] Alternatively, the passivation layer 40 may be a DBR layer or a silicon oxide layer.
[0142] Alternatively, the second electrode 32 may include at least one of an AuBe layer, an Au layer, a Ti layer, a Ni layer, and a Pt layer.
[0143] Illustratively, in a direction away from the epitaxial layer 20 , the second electrode 32 includes a stacked AuBe layer, an Au layer, a Ti layer, and a Ni layer.
[0144] Exemplarily, the AuBe layer has a thickness of 800 angstroms to 1200 angstroms. As an example, the AuBe layer has a thickness of 1000 angstroms.
[0145] Exemplarily, the thickness of the Au layer is 800 angstroms to 1200 angstroms. As an example, the thickness of the Au layer is 900 angstroms.
[0146] Exemplarily, the thickness of the Ti layer is 300 angstroms to 700 angstroms. As an example, the thickness of the Ti layer is 500 angstroms.
[0147] Exemplarily, the thickness of the Ni layer is 2000 angstroms to 4000 angstroms. As an example, the thickness of the Ni layer is 3000 angstroms.
[0148] Step S15 : forming second recessed holes 41 corresponding to the second electrodes 32 on a surface of the passivation layer 40 away from the epitaxial layer 20 .
[0149] The second recessed hole 41 exposes the corresponding second electrode 32 , and the second recessed hole 41 is located at the peripheral edge of the surface of the second semiconductor layer 23 .
[0150] Optionally, the second recessed hole 41 is located at a peripheral edge of the surface of the passivation layer 40 .
[0151] Optionally, the distribution spacing between adjacent first recessed holes 201 is greater than the distribution spacing between adjacent second recessed holes 41 .
[0152] Exemplarily, the ratio of the distribution spacing of adjacent first concave holes 201 to the distribution spacing of adjacent second concave holes 41 is greater than or equal to 1.5.
[0153] After step S15, the preparation method may further include the following steps:
[0154] In the first step, a through hole exposing the first electrode 31 and the second electrode 32 is formed by etching on the surface of the passivation layer 40 .
[0155] In the second step, a first connection electrode 51 and a second connection electrode 52 are formed on the surface of the passivation layer 40 , so that the first connection electrode 51 is connected to the first electrode 31 through the through hole, and the second connection electrode 52 is connected to the second electrode 32 through the through hole.
[0156] Optionally, the first connection electrode 51 and the second connection electrode 52 may each include at least one of an Au layer, a Ti layer, a Ni layer, and a Pt layer.
[0157] Exemplarily, in a direction away from the epitaxial layer 20 , the second connection electrode 52 includes an Au layer, a Ti layer, and a Ni layer stacked one on another.
[0158] Exemplarily, the thickness of the Au layer is 800 angstroms to 1000 angstroms. As an example, the thickness of the Au layer is 900 angstroms.
[0159] Exemplarily, the thickness of the Ti layer is 300 angstroms to 600 angstroms. As an example, the thickness of the Ti layer is 300 angstroms.
[0160] Exemplarily, the thickness of the Ni layer is 2000 angstroms to 3000 angstroms. As an example, the thickness of the Ni layer is 2000 angstroms.
[0161] In the third step, an insulating layer 60 is formed on the surface of the passivation layer 40 , the surfaces of the first connection electrode 51 and the second connection electrode 52 .
[0162] Optionally, the insulating layer 60 includes a silicon oxide layer.
[0163] When preparing the insulating layer 60, the deposition temperature of the insulating layer 60 is controlled to be 150°C to 250°C, and the deposition rate of the insulating layer 60 is controlled to be 15 angstroms / second to 25 angstroms / second. The insulating layer 60 prepared according to this process can release stress and improve the preparation quality of the light-emitting diode.
[0164] Exemplarily, the deposition temperature of the insulating layer 60 is 200° C., and the deposition rate of the insulating layer 60 is 20 angstroms / second.
[0165] In the fourth step, two through holes are formed on the insulating layer 60 to expose the first connection electrode 51 and the second connection electrode 52 respectively.
[0166] In the fifth step, after the through holes are formed, two soldering blocks 70 are made on the surface of the insulating layer 60 . The two soldering blocks 70 are connected to the first connection electrode 51 and the second connection electrode 52 through the through holes respectively.
[0167] Finally, the sapphire can be cut and scratched invisible, which can effectively reduce the loss of brightness. Then, the light-emitting diode is obtained by testing.
[0168] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A light emitting diode, characterized in that: The light emitting diode comprises an epitaxial layer (20) and a first electrode (31); the epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22) and a second semiconductor layer (23) which are stacked in sequence; a surface of the second semiconductor layer (23) away from the first semiconductor layer (21) comprises a plurality of first concave holes (201) exposing the first semiconductor layer (21); the plurality of first concave holes (201) are arranged at intervals; the first electrodes (31) correspond to the first concave holes (201) one by one, and the first electrodes (31) are located in the corresponding first concave holes (201); The ratio of the sum of the cross-sectional areas of the plurality of first recessed holes (201) to the area of the surface of the second semiconductor layer (23) away from the first semiconductor layer (21) is less than or equal to 0.
1.
2. The light emitting diode according to claim 1, characterized in that: The light emitting diode further comprises a passivation layer (40) and a first connecting electrode (51); The passivation layer (40) is located on a surface of the second semiconductor layer (23) away from the first semiconductor layer (21) and in the first concave hole (201), and the surface of the passivation layer (40) away from the first semiconductor layer (21) has a via hole exposing the first electrode (31); The first connecting electrode (51) is located on a surface of the passivation layer (40) away from the first semiconductor layer (21), and is connected to the first electrode (31) through a via hole.
3. The light emitting diode according to claim 2, characterized in that: The first concave hole (201) is located in the central area of the second semiconductor layer (23), and a plurality of the first concave holes (201) are arranged at intervals along the same straight line.
4. The light emitting diode according to claim 2, characterized in that: The light emitting diode further comprises a plurality of second electrodes (32) and a second connecting electrode (52); the plurality of second electrodes (32) are arranged at intervals on a surface of the second semiconductor layer (23) away from the first semiconductor layer (21); The passivation layer (40) covers a plurality of second electrodes (32), and a surface of the passivation layer (40) away from the epitaxial layer (20) further comprises second recessed holes (41) corresponding to each of the second electrodes (32) one by one, and the second recessed holes (41) expose the corresponding second electrodes (32); The second connecting electrode (52) is located on a surface of the passivation layer (40) away from the first semiconductor layer (21), and is connected to the second electrode (32) through each of the second recessed holes (41).
5. The light emitting diode according to claim 4, characterized in that: The second recessed hole (41) is located at a peripheral edge of the surface of the passivation layer (40).
6. The light emitting diode according to claim 5, characterized in that: The distribution spacing of adjacent first concave holes (201) is greater than the distribution spacing of adjacent second concave holes (41).
7. The light emitting diode according to claim 6, characterized in that: The ratio of the distribution spacing of adjacent first concave holes (201) to the distribution spacing of adjacent second concave holes (41) is greater than or equal to 1.
5.
8. The light emitting diode according to claim 5, characterized in that: The surface of the passivation layer (40) away from the epitaxial layer (20) is a rectangular surface, and the cross-sectional area of the second recessed hole (41) located in the corner region of the rectangular surface is larger than the cross-sectional area of the second recessed hole (41) in the area of the rectangular surface other than the corner region.
9. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: Manufacturing an epitaxial layer, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence; A plurality of first concave holes are formed on a surface of the second semiconductor layer away from the first semiconductor layer to expose the first semiconductor layer, the plurality of first concave holes are arranged at intervals, and a ratio of a sum of cross-sectional areas of the plurality of first concave holes to an area of the surface of the second semiconductor layer away from the first semiconductor layer is less than or equal to 0.1; A first electrode is formed in each of the first recesses.
10. The preparation method according to claim 9, characterized in that: After forming the first electrode in each of the first recessed holes, the method further includes: forming a passivation layer and a plurality of second electrodes on a surface of the second semiconductor layer away from the first semiconductor layer, wherein the plurality of second electrodes are arranged at intervals, and the passivation layer covers the plurality of second electrodes; Second recessed holes corresponding to the second electrodes are formed on a surface of the passivation layer away from the epitaxial layer, the second recessed holes expose the corresponding second electrodes, and the second recessed holes are located at the peripheral edge of the surface of the second semiconductor layer.