Non-pressure low void ratio welding method for large-size power chip

Abstract

The invention discloses a large-size power chip no-pressure low-void-ratio welding method, which comprises the following steps of: determining proper thickness and size of a soldering lug according to the size of a chip and the material of a substrate; then cutting and carrying out plasma cleaning on the soldering lug to remove dirt on the surface of the soldering lug; welding sample assembly is completed through an automatic chip mounter; setting a vacuum welding curve according to the material characteristics of the welding sheet, determining key welding parameters such as formic acid pressure, formic acid reduction temperature, formic acid reduction time, peak temperature, peak temperature holding time, furnace chamber pressure and holding time and the like, and completing chip welding according to the set curve; and finally, measuring the internal void ratio of the welding seam by adopting an X-ray detector. On the basis of the vacuum eutectic welding technology, under the non-pressure welding condition, the air holes in the welding flux layer are discharged by regulating and controlling the environment pressure change in the welding process, and low-void-ratio welding of the large-size chip is achieved.

Description

Technical Field

[0001] The invention relates to the technical field of electronic packaging, in particular to a non-pressure low-void rate welding method for a large-size power chip. Background Art

[0002] With the advancement of integrated circuit technology and third-generation semiconductor technology, the electronic systems of aerospace equipment are developing in the direction of integration, high density and high power. Power devices, such as IGBT, MOSFET high-power chips, are widely used in key components of radar and servo systems. This type of chip is mainly responsible for equipment power transmission and control. Under high voltage and high current working environment, the heat consumption of the chip itself increases significantly. Studies have shown that the internal holes in the solder layer will affect the transfer of heat in the solder. Therefore, low-porosity weld joints are conducive to quickly conducting the heat generated by the chip to the outside world, thereby reducing the thermal resistance of the chip, suppressing the internal thermal stress deformation of the device, and improving the reliability and service life of the device.

[0003] At present, the connection methods between semiconductor chips and substrates mainly include colloid bonding, reflow soldering and other technologies. The colloid bonding process uses a polymer adhesive doped with conductive particles to bond and solidify the chip and the substrate. Due to the high resistivity and low thermal conductivity of the colloid itself, it is mostly used in low-power scenarios such as consumer electronic products. The reliability is poor under high-power application conditions. In high-power scenarios, eutectic welding technology is mostly used to achieve reliable connection between the chip and the substrate. Traditional reflow soldering uses metal solder to form a metal solder layer between the chip and the substrate by high-temperature welding. However, during the welding process, a certain pressure still needs to be applied to the chip surface by means of tooling fixation, which reduces welding efficiency and increases the risk of chip damage. In addition, the gas generated during the welding process is difficult to discharge, which increases the internal porosity of the solder layer and affects the reliability of the solder layer. Summary of the invention

[0004] The present invention provides a method for non-pressure low-porosity welding of large-sized power chips. The technical problem to be solved by the present invention is: how to achieve low-porosity welding of large-sized power chips under the condition of non-pressure welding during the power chip welding process. The present invention further solves the problem of determining a reasonable welding process curve for different solder materials to achieve low-porosity welding of various types of large-sized power chips.

[0005] In a first aspect, a method for welding a large-size power chip without pressure and with low void rate is provided, comprising:

[0006] After assembling the substrate, pads and chip, they are welded. The welding process includes:

[0007] The preheating stage is used to preheat the product;

[0008] The formic acid reduction stage is used to pass nitrogen containing formic acid into the vacuum brazing furnace cavity to ensure that the chip, substrate and solder are in a formic acid environment. The formic acid undergoes a reduction reaction at high temperature to remove the oxide layer and contamination on the surface of the chip, substrate and solder.

[0009] During the welding stage, it is used to melt the solder by heating up and keep the furnace chamber in a negative pressure state, so that the residual gas inside the solder is discharged from the inside of the solder into the furnace chamber under the action of the environmental pressure difference and the surface tension of the liquid solder, thereby reducing the porosity inside the weld. After the pores are discharged by vacuum, nitrogen is flushed in to increase the pressure inside the furnace chamber, compress the pore volume inside the solder, and reduce the porosity inside the weld.

[0010] The cooling stage is used to reduce the temperature and solidify the solder;

[0011] The temperature of at least one of the preheating stage, the formic acid reduction stage and the welding stage is adjusted by a temperature adjustment value Q, and Q is related to the difference between the surface temperature of the welding sample substrate and the temperature of the hot plate.

[0012] In combination with the first aspect, in certain implementations of the first aspect, Q satisfies: Q=T0-T, wherein T0 is the temperature of the heating plate of the vacuum brazing furnace, ℃; T is the measured temperature of the surface of the welding sample substrate, ℃; Q is measured by the welding sample, the welding sample is placed in a vacuum brazing furnace and the heating plate temperature is set to T0; during the welding process, the measured temperature of the surface of the welding sample substrate is measured to obtain the value of T, thereby determining Q.

[0013] In combination with the first aspect, in certain implementations of the first aspect, Q is measured by multiple welding samples, each welding sample corresponds to a test welding temperature, the test welding temperature is a point value in the range of T1+(20°C~60°C), T1 is the melting point of the solder, and the test welding temperatures corresponding to the multiple welding samples are different; then the multiple welding samples are welded according to the corresponding test welding temperatures, and the temperature difference between the surface temperature of the welding sample substrate and the hot plate temperature is measured during the welding process; the average of the multiple measured temperature differences is calculated to obtain Q.

[0014] In combination with the first aspect, in some implementations of the first aspect, the welding sheet satisfies at least one of the following:

[0015] The solder sheet material includes any one of lead-tin, tin-silver-copper, tin-antimony, and tin-bismuth;

[0016] The melting point of the solder is at least 50°C higher than the peak operating temperature of the chip;

[0017] The thickness of the soldering piece is between 0.5 mm and 2.0 mm, and the side length of the soldering piece accounts for 80% to 100% of the side length of the chip.

[0018] In combination with the first aspect, in certain implementations of the first aspect, when the substrate coating is Au or Ag, the side length of the solder pad accounts for 80% to 90% of the side length of the chip; when the substrate coating material is Cu or Ni, the side length of the solder pad accounts for 90% to 100% of the side length of the chip.

[0019] In combination with the first aspect, in certain implementations of the first aspect, the temperature in the preheating stage is (60% to 70%) T1+Q, T1 is the melting point of the solder, the heating rate is 30°C / min to 60°C / min, and the holding time in the preheating stage is 10s to 60s.

[0020] In combination with the first aspect, in certain implementations of the first aspect, the formic acid reduction temperature is (75% to 85%) T1+Q, T1 is the melting point of the solder, and the formic acid reduction time is 30s to 240s.

[0021] In combination with the first aspect, in certain implementations of the first aspect, the peak temperature in the welding stage is T1+(20°C-40°C)+Q, T1 is the melting point of the solder, and the peak temperature is maintained for 10s-30s.

[0022] In combination with the first aspect, in certain implementations of the first aspect, the vacuum degree in the welding stage is ≤10 mbar, the vacuum holding time is 10 s to 60 s, the nitrogen backfill pressure is 800 mbar to 1000 mbar, and the nitrogen backfill time is 10 s to 60 s.

[0023] In combination with the first aspect, in certain implementations of the first aspect, the solder is solidified by cooling in the cooling stage by water cooling or air cooling, with a cooling rate of 40° C. / min to 60° C. / min.

[0024] Compared with the prior art, the solution provided by the present invention includes at least the following beneficial technical effects:

[0025] (1) The solder sheet and chip automatic mounting and vacuum eutectic welding methods are used to achieve pressureless welding of large-size chips, solving the problems of complex chip pressurization operation and high risk of chip damage in the existing chip welding process;

[0026] (2) A method of segmented control of the welding process environmental pressure is adopted to eliminate pores in the solder layer and achieve a porosity rate in the solder layer of ≤1%, thereby solving the problem of high porosity in the solder layer during the existing large-size chip welding process. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is the pressure-free welding flow chart for large-size power chips.

[0028] Figure 2 Schematic diagram for determining temperature correction value.

[0029] Figure 3This is a schematic diagram related to large-size power chips. Figure 3 The left picture is a schematic diagram of the sintering sample of a large-size power chip. Figure 3 The right picture in the figure is a schematic diagram of the sintering porosity distribution of large-size power chips. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] like Figure 1 As shown, the present invention provides a method for welding a large-size power chip without pressure and with low void ratio. The specific steps are as follows.

[0032] Step (1), determine the material and size of the soldering sheet.

[0033] Determine the soldering material according to the metal coating material on the substrate surface and the operating temperature.

[0034] In some embodiments, the solder sheet material includes but is not limited to lead-based and tin-based solders such as lead-tin, tin-silver-copper, tin-antimony, and tin-bismuth.

[0035] In some embodiments, the solder melting point should be at least 50°C higher than the chip peak operating temperature.

[0036] In some embodiments, the thickness of the selected soldering pad should be 0.5mm to 2.0mm, and the side length of the soldering pad should account for 80% to 100% of the side length of the chip. For example, the length of the soldering pad is 80% to 100% of the length of the chip, and the width of the soldering pad is 80% to 100% of the width of the chip. For example, if the substrate coating is a material with good wettability including but not limited to Au, Ag, etc., the side length of the soldering pad should account for 80% to 90% of the side length of the chip. For another example, if the substrate coating material is a material with general wettability including but not limited to Cu, Ni, etc., the side length of the soldering pad should account for 90% to 100% of the side length of the chip.

[0037] (2) Cutting and cleaning solder joints.

[0038] Cut the soldering pieces according to the determined size to ensure that they are flat without warping, bending or deformation. Then use argon plasma cleaning to remove oxidation and dirt on the surface of the soldering pieces to ensure that the surface of the soldering pieces is clean.

[0039] (3) The substrate, pads and chip are assembled.

[0040] A high-precision automatic placement machine is used to sequentially mount the solder pads and chips at the designated positions on the substrate to ensure that the center positions of the solder pads and chips are consistent.

[0041] (4) Determine the temperature adjustment value Q, which is related to the difference between the surface temperature of the welding sample substrate and the temperature of the hot plate.

[0042] In one embodiment, Q satisfies: Q=T0-T, where T0 is the temperature of the vacuum brazing furnace heating plate, °C; T is the measured temperature of the welding sample substrate surface, °C. T0 can be determined by conventional methods; then the welding sample is placed in the vacuum brazing furnace and the heating plate temperature is set to T0; during the welding process, the measured temperature of the welding sample substrate surface is measured to obtain the value of T, and then Q is determined.

[0043] In one embodiment, multiple welding samples can be prepared when measuring Q, and each welding sample corresponds to a test welding temperature, and the test welding temperature is a point value in the range of T1+(20°C to 60°C), where T1 is the melting point of the solder. Then, the multiple welding samples are welded according to the corresponding test welding temperatures, and the temperature difference between the surface temperature of the welding sample substrate and the temperature of the hot plate is measured during the welding process. The average value of the multiple temperature differences measured is calculated to obtain the value of Q.

[0044] (5) Determine the welding curve, and then use a vacuum brazing furnace to sinter the chip according to the set welding curve.

[0045] The welding process includes four stages: preheating, formic acid reduction, welding and cooling. The key parameters of the welding curve for large-size power chips are shown in Table 1.

[0046] The preheating stage is to preheat the product and optimize the subsequent welding effect. The temperature in the preheating stage should be (60% to 70%) T1+Q, T1 is the melting point of the solder, the heating rate is 30℃ / min to 60℃ / min, and the holding time in the preheating stage is 10s to 60s.

[0047] In the formic acid reduction stage, nitrogen containing formic acid is introduced into the vacuum brazing furnace cavity to ensure that the chip, solder sheet, substrate, etc. are in a formic acid environment. The formic acid undergoes a reduction reaction at high temperature to remove the oxide layer and contamination on the surface of the chip, substrate and solder. The formic acid reduction temperature should be (75% to 85%) T1+Q, T1 is the melting point of the solder, and the formic acid reduction time is 30s to 240s.

[0048] During the welding stage, the temperature is raised to melt the solder, and the furnace chamber is kept at a negative pressure state, so that the residual gas inside the solder is discharged from the inside of the solder into the furnace chamber under the action of the environmental pressure difference and the surface tension of the liquid solder, reducing the porosity inside the weld. After the pores are vacuumed out, nitrogen is flushed in to increase the pressure in the furnace chamber, compressing the volume of pores inside the solder, and further reducing the porosity inside the weld. The peak temperature is T1+(20℃~40℃)+Q, T1 is the melting point of the solder, and the peak temperature is maintained for 10s~30s; the vacuum degree during the welding stage is ≤10mbar, the vacuum is maintained for 10s~60s, the nitrogen backfill pressure is 800mbar~1000mbar, and the nitrogen backfill time is 10s~60s.

[0049] During the cooling stage, the solder is cooled by water cooling or air cooling to solidify the solder, with a cooling rate of 40°C / min to 60°C / min.

[0050] Table 1 List of key parameters of welding curve

[0051]

[0052] The internal porosity of the solder layer between the chip and the substrate can be detected by an X-ray detector. The solution provided by the present invention is conducive to ensuring that the bubble porosity in the solder layer is ≤1%, that is, a qualified weld.

[0053] The present invention selects suitable solder sheet materials according to the application conditions; determines the appropriate solder sheet thickness and size according to the chip size and substrate material; then cuts and plasma cleans the solder sheet to remove surface dirt; uses an automatic chip mounter to complete the assembly of welding samples; sets a vacuum welding curve according to the characteristics of the solder sheet material, determines key welding parameters such as formic acid pressure, formic acid reduction temperature, formic acid reduction time, peak temperature, peak temperature holding time, furnace chamber pressure and holding time, and completes chip welding according to the set curve; finally, uses an X-ray detector to determine the internal porosity of the weld. The present invention is based on vacuum eutectic welding technology. Under pressureless welding conditions, the pores in the solder layer are discharged by regulating the environmental pressure changes during the welding process, thereby achieving low porosity welding of large-size chips.

[0054] Example 1

[0055] (1) Determination of soldering sheet material and size: To solve the welding problem between large-sized IGBT (12.0 mm*11.0 mm) chips and ceramic copper-clad substrates (DBC) in IGBT power modules, a 0.1 mm thick Pb92.5Sn5Ag2.5 lead-tin solder sheet (melting point: 287°C) is selected according to the working conditions of the IGBT chip at an operating temperature of 150°C to 180°C. The size of the soldering sheet is the same as the chip size, 12.0 mm*11.0 mm.

[0056] (2) Cutting and cleaning of solder pieces: According to the size of the solder pieces in step 1, use an automatic cutter to cut the solder pieces of the required size. After cutting, ensure that the surface of the solder pieces is clean and flat. Use an argon plasma cleaner to clean the solder pieces for 5 minutes to remove dirt and oxidation on the surface of the solder pieces.

[0057] (3) Assembly of welding samples: Use an automatic chip mounter to sequentially overlap the solder pad and chip and mount them to the designated chip position on the substrate, ensuring that the solder pad is aligned with the center of the chip and that the solder pad is completely located under the chip;

[0058] (4) Determination of temperature correction value: Figure 2 As shown, before determining the curve temperature, the difference between the surface temperature of the welding sample and the temperature of the hot plate should be measured, Q = 20 °C;

[0059] (5) Determination of welding curve: The JFHK HJL / 300 vacuum brazing furnace was used for sintering, the hot plate temperature was set to 350°C, the sample temperature on the substrate surface was measured to be 330°C, and the temperature difference Q = 20°C was determined. According to the melting point of Pb92.5Sn5Ag2.5 lead-tin solder sheet being 287°C, the key welding process parameters were determined as shown in Table 2.

[0060] Table 2

[0061]

[0062] (6) Vacuum eutectic welding: Place the welding sample on the hot plate of a vacuum welding furnace and perform vacuum welding according to the set welding curve. According to the welding curve, adjust the pressure in the furnace chamber during the heating process to ensure that the gas in the molten solder layer is discharged and the porosity of the solder layer is reduced.

[0063] (7) Porosity detection: Use an X-ray detector to measure the porosity in the solder layer. The results are as follows: Figure 3 As shown, the porosity in the solder layer is less than 1%.

[0064] Although the present invention is disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A method for welding large-size power chips without pressure and with low porosity, characterized in that: include: After assembling the substrate, pads and chip, they are welded. The welding process includes: The preheating stage is used to preheat the product; The formic acid reduction stage is used to pass nitrogen containing formic acid into the vacuum brazing furnace cavity to ensure that the chip, substrate and solder are in a formic acid environment. The formic acid undergoes a reduction reaction at high temperature to remove the oxide layer and contamination on the surface of the chip, substrate and solder. During the welding stage, it is used to melt the solder by heating up and keep the furnace chamber in a negative pressure state, so that the residual gas inside the solder is discharged from the inside of the solder into the furnace chamber under the action of the environmental pressure difference and the surface tension of the liquid solder, thereby reducing the porosity inside the weld. After the pores are discharged by vacuum, nitrogen is flushed in to increase the pressure inside the furnace chamber, compress the pore volume inside the solder, and reduce the porosity inside the weld. The cooling stage is used to reduce the temperature and solidify the solder; The temperature of at least one of the preheating stage, the formic acid reduction stage and the welding stage is adjusted by a temperature adjustment value Q, and Q is related to the difference between the surface temperature of the welding sample substrate and the temperature of the hot plate.

2. The method according to claim 1, characterized in that Q satisfies: Q=T0-T, where T0 is the temperature of the heating plate of the vacuum brazing furnace, ℃; T is the measured temperature of the surface of the welding sample substrate, ℃; Q is measured by the welding sample, the welding sample is placed in the vacuum brazing furnace and the heating plate temperature is set to T0; during the welding process, the measured temperature of the surface of the welding sample substrate is measured to obtain the value of T, thereby determining Q.

3. The method according to claim 1, characterized in that Q is measured by multiple welding samples, each welding sample corresponds to a test welding temperature, the test welding temperature is a point value in the range of T1+(20℃~60℃), T1 is the melting point of the solder, and the test welding temperatures corresponding to the multiple welding samples are different; then the multiple welding samples are welded according to the corresponding test welding temperatures, and the temperature difference between the surface temperature of the welding sample substrate and the hot plate temperature is measured during the welding process; the average value of the measured multiple temperature differences is calculated to obtain Q.

4. The method according to any one of claims 1 to 3, characterized in that The temperature in the preheating stage is (60% to 70%) T1+Q, T1 is the melting point of the solder, the heating rate is 30°C / min to 60°C / min, and the holding time in the preheating stage is 10s to 60s.

5. The method according to any one of claims 1 to 3, characterized in that The formic acid reduction temperature is (75% to 85%) T1+Q, T1 is the melting point of the solder, and the formic acid reduction time is 30s to 240s.

6. The method according to any one of claims 1 to 3, characterized in that The peak temperature during the welding stage is T1+(20℃~40℃)+Q, where T1 is the melting point of the solder and the peak temperature is maintained for 10s~30s.

7. The method according to any one of claims 1 to 3, characterized in that During the welding stage, the vacuum degree is ≤10mbar, the vacuum holding time is 10s to 60s, the nitrogen backfill pressure is 800mbar to 1000mbar, and the nitrogen backfill time is 10s to 60s.

8. The method according to any one of claims 1 to 3, characterized in that During the cooling stage, the solder is solidified by cooling with water or air, with a cooling rate of 40°C / min to 60°C / min.

9. The method according to claim 1, characterized in that: The soldering sheet satisfies at least one of the following: The solder sheet material includes any one of lead-tin, tin-silver-copper, tin-antimony, and tin-bismuth; The melting point of the solder is at least 50°C higher than the peak operating temperature of the chip; The thickness of the soldering piece is between 0.5 mm and 2.0 mm, and the side length of the soldering piece accounts for 80% to 100% of the side length of the chip.

10. The method according to claim 9, characterized in that When the substrate coating is Au or Ag, the side length of the solder piece accounts for 80% to 90% of the side length of the chip; when the substrate coating material is Cu or Ni, the side length of the solder piece accounts for 90% to 100% of the side length of the chip.

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