Dividing film and method of manufacturing semiconductor package by using same

Abstract

The invention provides a dividing film and a method of manufacturing a semiconductor package. In the dividing film, the adhesive strength of the adhesive layer constituting the dividing film can be sufficiently reduced after heat treatment, and the semiconductor die can be easily separated from the dividing film. Therefore, an effect of improving pickup performance of the semiconductor die can be obtained.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0107096 filed in the Korean Intellectual Property Office on August 16, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a dicing film and a method of manufacturing a semiconductor package by using the dicing film. Background Art

[0004] Recently, the demand for portable devices has rapidly increased in the electronic product market.

[0005] Therefore, there is a continuous demand for miniaturization and weight reduction of electronic components (eg, semiconductor chips) mounted on these products. To achieve miniaturization and weight reduction of electronic components, semiconductor packages mounted thereon need to process high-capacity data while having a small volume.

[0006] Therefore, high integration and single packaging of semiconductor chips mounted on semiconductor packages are required. In order to meet these requirements, the substrate structure is divided to form a plurality of semiconductor dies, and each of the semiconductor dies can be manufactured as a semiconductor package. Therefore, a dividing film with excellent pickup performance is required for manufacturing semiconductor dies after the process of dividing the substrate structure. Summary of the invention

[0007] Aspects of the present inventive concept provide a separation film, and more specifically, provide a separation film including a high temperature curable adhesive and a method of manufacturing a semiconductor package by using the separation film. The adhesive strength of an adhesive layer constituting the separation film can be sufficiently reduced after performing a heat treatment thereon, and a semiconductor die can be easily separated from the separation film, and therefore, the pickup performance of the semiconductor die can be improved.

[0008] The present inventive concept provides a method of manufacturing a semiconductor package, in which the adhesive strength of an adhesive layer constituting a dicing film can be sufficiently reduced after heat treatment is performed thereon, and a semiconductor die can be easily separated from the dicing film, and thus, pickup performance of the semiconductor die can be improved.

[0009] The objects of the inventive concept are not limited to those described above, and other objects not mentioned herein will be clearly understood by those of ordinary skill in the art from the following description.

[0010] According to an aspect of the present inventive concept, there is provided a splitting film including a base layer, an intermediate layer on the base layer, and an adhesive layer on the intermediate layer, wherein the adhesive layer includes an acrylate polymer composition including acrylonitrile.

[0011] According to another aspect of the present inventive concept, a pressure-sensitive adhesive is provided, which includes an acrylate polymer composition containing acrylonitrile in a range of 3 wt % to 50 wt %, wherein the adhesive strength of the pressure-sensitive adhesive increases after performing an ultraviolet treatment on the pressure-sensitive adhesive, and the adhesive strength of the pressure-sensitive adhesive decreases after performing a heat treatment on the pressure-sensitive adhesive.

[0012] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, the method comprising: preparing a substrate structure having a first surface bonded to a carrier substrate; bonding a second surface of the substrate structure opposite to the first surface to a segmentation film; separating the carrier substrate from the substrate structure and performing an ultraviolet treatment on the separated substrate structure; bonding solder balls to the first surface of the substrate structure and performing a heat treatment on the substrate structure; separating the substrate structure into a plurality of semiconductor dies by cutting the substrate structure along a segmentation line; peeling and picking up the semiconductor dies from the segmentation film; and forming the semiconductor dies into semiconductor packages respectively, wherein the segmentation film comprises a base layer, an intermediate layer on the base layer, and an adhesive layer on the intermediate layer, and wherein the adhesive layer comprises an acrylate polymer composition comprising acrylonitrile.

[0013] A method for manufacturing a semiconductor package according to the present invention includes: preparing a semiconductor wafer; bonding a separation film to the semiconductor wafer; performing ultraviolet treatment on the separation film; performing heat treatment on the separation film; and peeling the semiconductor wafer from the separation film, wherein the separation film includes a base layer, an intermediate layer on the base layer, and an adhesive layer on the intermediate layer, and wherein the adhesive layer includes an acrylate polymer composition containing acrylonitrile. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a schematic cross-sectional view showing a dividing film according to an embodiment;

[0016] Figure 2 It shows that according to Figure 1 A diagram showing a change in the formula of the heat treatment of the adhesive layer of the split film;

[0017] Figure 3 It shows that according to Figure 1 A graph showing an experimental example of heat treatment of an adhesive layer of a split film;

[0018] Figure 4is a graph showing changes in adhesive strength when acrylonitrile is not added to the adhesive layer of the split film;

[0019] Figure 5 is a graph showing changes in adhesive strength when acrylonitrile is added to an adhesive layer of a split film;

[0020] Figure 6 is a flow chart of a method for manufacturing a semiconductor package according to an embodiment;

[0021] Figures 7 to 16 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment; and

[0022] Figures 17 to 19 are diagrams illustrating other semiconductor packages manufactured by the method of manufacturing a semiconductor package according to the inventive concept. DETAILED DESCRIPTION

[0023] Embodiments will be described in detail with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the example embodiments set forth herein. It should be emphasized that the present disclosure provides details of alternative examples, but such enumeration of alternatives is not exhaustive. In addition, any consistency of details between the various examples should not be construed as requiring such. The language of the claims should be referenced when determining the requirements of the present invention.

[0024] Figure 1 is a schematic cross-sectional view showing a splitting film 10 according to an embodiment, Figure 2 It shows that according to Figure 1 A diagram showing a change in the heat treatment formula of the adhesive layer 15 of the splitting film 10, and Figure 3 It shows that according to Figure 1 A graph showing an experimental example of heat treatment of the adhesive layer 15 of the dividing film 10.

[0025] Reference Figures 1 to 3 The split film 10 may include a base layer 11, an intermediate layer 13 on the base layer 11, and an adhesive layer 15 on the intermediate layer 13. The split film 10 may also be referred to as a split support film or a substrate support film.

[0026] The split film 10 may have a circular shape with a first diameter. The first diameter may be greater than a second diameter of the substrate structure (e.g., the split film 10 may have a surface area greater than a surface area of ​​the substrate structure to which the split film 10 is applied). The second diameter is the diameter of the wafer constituting the substrate structure, and may be, for example, about 300 mm (12 inches) or about 450 mm (18 inches).

[0027] The terms "adhesion" and "bonding" as used herein may be different words from each other in a strict sense, but the term "bonding" as used herein may be used as a comprehensive term including both adhesion and bonding. In addition, the term "bonding" as used herein may be used as a term including both adhesion and bonding. The elements constituting the partition film 10 will be described in more detail.

[0028] The base layer 11 may be referred to as a base film. The base layer 11 may be formed of and / or include a synthetic resin having a specific elastic modulus. The specific elastic modulus may be a specific Young's modulus. For example, the Young's modulus may be between 2 gigapascals and 4 gigapascals. For example, the base layer 11 may be formed of and / or include a material selected from polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyetheretherketone (PEEK), and polyimide (PI). The base layer 11 may have a first thickness 11T. In some embodiments, the first thickness 11T may be from about 20 microns to about 30 microns. The base layer 11 may improve the physical reliability of the split film 10 by physically supporting the adhesive layer 15 in the process of processing the substrate structure. In addition, the base layer 11 may improve the chemical reliability of the split film 10 by preventing moisture absorption (moisture penetration or moisture inhalation) that may occur in the process of processing the substrate structure.

[0029] The intermediate layer 13 may be disposed on the base layer 11. The intermediate layer 13 may be referred to as an anchor film. When the substrate structure bonded to the carrier substrate is mounted on the split film 10, the intermediate layer 13 may be physically used as a buffer. The intermediate layer 13 may have a second thickness 13T. In some embodiments, the second thickness 13T may be about 1 micron to about 10 microns. The second thickness 13T of the intermediate layer 13 may be less than the first thickness 11T of the base layer 11. For example, the intermediate layer 13 may be formed of and / or include the following materials: a curable synthetic resin that may be an ultraviolet (UV) curable synthetic resin or a non-UV curable synthetic resin. In some embodiments, the intermediate layer 13 may be formed of and / or include an acrylate polymer and a crosslinking agent.

[0030] In the following description, the amount of a material may be expressed as a weight percent (wt%). The weight percent refers to the mass of a material divided by the total mass of the component being described. For example, the weight percent of a particular material in a particular layer is given by dividing the mass of the particular material in the particular layer by the total mass of the particular layer. Alternatively, in another example, the weight percent of a particular material in a particular composition is given by dividing the mass of the particular material in a unit mass of the particular composition by the total mass of the unit mass of the particular composition.

[0031] The monomer composition constituting the acrylate polymer may include a first monomer, such as 2-ethylhexyl acrylate, 2-hydroxyethyl acrylate or butyl acrylate, and the amount of the first monomer included in the acrylate polymer may be in the range of about 50wt% to about 90wt%. The acrylate polymer may include a second monomer, such as methyl acrylate, vinyl acetate or styrene as an adhesive component. The amount of the second monomer may be in the range of about 10wt% to about 40wt%. In addition, the acrylate polymer may include a third monomer, such as acrylic acid or methacrylic acid. The third monomer may be included as a functional group, and the amount of the third monomer may be in the range of about 2wt% to about 20wt%. However, the monomer composition constituting the acrylate polymer is not limited thereto. In the acrylate polymer, the total amount of the monomer composition may be 100wt% or less.

[0032] Terms such as "about" or "approximately" can reflect an amount, size, orientation, or arrangement that varies only in a relatively small manner and / or in a manner that does not significantly alter the operation, function, or structure of a particular element. For example, a range from "about 0.1 to about 1" can encompass ranges such as 0% to 5% deviations around 0.1 and 0% to 5% deviations around 1, especially if such deviations maintain the same effect as the listed range.

[0033] The crosslinking agent is not particularly limited as long as the crosslinking agent includes an isocyanate. For example, the crosslinking agent may be at least one agent selected from the group consisting of an alicyclic compound (such as isophorone diisocyanate or methylenebiscyclohexane diisocyanate), an aliphatic compound (such as hexamethylene diisocyanate), and an aromatic compound (such as toluene diisocyanate, methylene diphenyl diisocyanate, or meta-tetramethylxylene diisocyanate), but the inventive concept is not limited thereto.

[0034] The adhesive layer 15 may be disposed on the intermediate layer 13. The adhesive layer 15 may be referred to as an adhesive film. In addition, the adhesive layer 15 may be a single layer. When the substrate structure bonded to the carrier substrate is mounted on the split film 10, the adhesive layer 15 may be used as an adhesive. The adhesive layer 15 may have a third thickness 15T. In some embodiments, the third thickness 15T may be about 30 microns to about 40 microns. The third thickness 15T of the adhesive layer 15 may be greater than the first thickness 11T of the base layer 11. The adhesive layer 15 may be formed of, for example, a high temperature curable, high heat resistant pressure sensitive adhesive (PSA) and / or include, for example, a high temperature curable, high heat resistant pressure sensitive adhesive (PSA). In some embodiments, the adhesive layer 15 may be formed of, for example, an acrylate polymer, a crosslinking agent and a photoinitiator and / or include, for example, an acrylate polymer, a crosslinking agent and a photoinitiator. The acrylate polymer and the crosslinking agent constituting the adhesive layer 15 may be the same, substantially the same or similar to those described above. Although the acrylate polymer and crosslinking agent constituting the adhesive layer 15 may be the same, substantially the same, or similar to those described above, the acrylate polymer and crosslinking agent constituting the adhesive layer 15 are not necessarily the same as those constituting the intermediate layer 13 in the embodiment of the partition film 10 .

[0035] The photoinitiator may be, for example, at least one material selected from the group consisting of a benzoin compound, an acetophenone compound, an acylphosphine oxide compound, a titanocene compound, a thioxanthone compound, an amine, and a quinone. In some embodiments, the photoinitiator may be one of 1-hydroxycyclohexyl phenyl ketone, benzoin, benzoin methyl ether, benzoin ethyl ether, benzoin isopropyl ether, benzyl phenyl sulfide, tetramethylthiuram monosulfide, azobisisobutyronitrile, bibenzyl, biacetyl, and β-chloroanthraquinone, but the inventive concept is not limited thereto.

[0036] In the split film 10 according to the present inventive concept, acrylonitrile may be included in the acrylate polymer as the main component of the adhesive layer 15. In some embodiments, the adhesive layer 15 may include acrylonitrile in the range of about 3wt% to about 50wt%. The inventors found that when the adhesive layer 15 includes less than about 3wt% of acrylonitrile, the high temperature curing effect cannot be fully achieved. In addition, the inventors found that when the adhesive layer 15 includes more than about 50wt% of acrylonitrile, sufficient bonding strength cannot be ensured to bond the substrate structure.

[0037] The inventors found that, by including acrylonitrile in the adhesive layer 15 , the adhesive strength of the adhesive layer 15 increases after UV treatment is performed thereon, and decreases after heat treatment is performed thereon.

[0038] The UV treatment may cause the acrylate polymer in the adhesive layer 15 to be cured by the photoinitiator. That is, the polymerization reaction of the acrylate polymer may include a free radical polymerization reaction using a photoinitiator. However, it is determined that due to the large amount of light emitting diode (LED) UV irradiation used in the process of manufacturing semiconductor packages, the temperature of the substrate structure is increased to about 150°C, and therefore, the adhesive strength is increased.

[0039] In addition, during the heat treatment at a specific temperature, the following chemical changes occur in acrylonitrile in the adhesive layer 15. Although not bound by a specific theory, it is determined that this chemical change causes additional curing that further improves the cohesive force of the random copolymer, and therefore, the adhesive strength decreases. Specifically, in the heat treatment at a specific temperature, acrylonitrile undergoes a crosslinking reaction from the following formula (1) to the following formula (2).

[0040] [Formula (1)]

[0041]

[0042] [Formula (2)]

[0043]

[0044] like Figure 2 As shown in , formula (1) undergoes an intermediate change at about 175° C. and becomes formula (2) at about 250° C. In other words, acrylonitrile forms ladder-shaped polyacrylonitrile (ladder-shaped PAN) from polyacrylonitrile (PAN) in a heat treatment in a temperature range of about 175° C. to about 250° C., thereby causing additional curing that further improves the cohesive force of the random copolymer. Therefore, it can be seen that the adhesive strength is reduced due to high-temperature curing.

[0045] like Figure 3 As shown in, the inventors prepared adhesive samples including 15wt% of acrylonitrile and conducted experiments with different heat treatment times. Specifically, the presence of a triple bond between carbon (C) and nitrogen (N) was analyzed by measuring the transmittance of light of different wavelengths in the sample. In experimental example (1), no heat treatment was performed, in experimental example (2), heat treatment was performed under process conditions of about 250°C for about 1 minute, and in experimental example (3), heat treatment was performed under process conditions of about 250°C for about 10 minutes.

[0046] First, it can be seen that in Experimental Example (1) and Experimental Example (2), the wavelength corresponding to the triple bond of carbon (C) and nitrogen (N) has a reduced transmittance indicating the presence of the triple bond. This result can indicate that acrylonitrile maintains the form (PAN) shown in formula (1).

[0047] In contrast, it can be seen that in Experimental Example (3), the transmittance of the sample does not change at the wavelength corresponding to the triple bond of carbon (C) and nitrogen (N). This result may indicate that acrylonitrile changes to the form shown in Formula (2) (trapezoidal PAN) through a crosslinking reaction.

[0048] Through these experiments, the inventors confirmed that acrylonitrile exhibits a cross-linking reaction in the adhesive sample constituting the adhesive layer 15 by heat treatment at a specific temperature.

[0049] Finally, in the dicing film 10 according to the present inventive concept, the adhesive strength of the adhesive layer 15 constituting the dicing film 10 can be sufficiently reduced after performing heat treatment thereon, and the semiconductor die can be easily separated from the dicing film 10. Therefore, the effect of improving the pickup performance of the semiconductor die can be expected.

[0050] Figure 4 is a graph showing changes in adhesive strength when acrylonitrile is not added to the adhesive layer of the partition film, and Figure 5 is a graph showing changes in adhesive strength when acrylonitrile is added to the adhesive layer of the dividing film.

[0051] Refer to Figure 4 and Figure 5 , it was possible to confirm the difference in adhesive strength between when acrylonitrile was not added to the adhesive layer of the dividing film and when acrylonitrile was added to the adhesive layer of the dividing film.

[0052] In the case where acrylonitrile is not added to the adhesive layer and in the case where acrylonitrile is added to the adhesive layer (see Figure 4 and Figure 5 ) In both, it can be seen that the bonding strength increases after the UV treatment is performed on the bonding layer compared to the initial bonding strength. The UV treatment can cause the acrylate polymer to be cured by the photoinitiator in the bonding layer, but due to the large amount of LED UV irradiation, the ambient temperature rises to about 150°C, which is determined to actually increase the bonding strength.

[0053] As with conventional split films, when acrylonitrile is not added to the adhesive layer (see Figure 4 ), when heat treatment is performed after UV treatment, the adhesive strength of the adhesive layer is significantly increased. This is determined to be due to the adhesion between the adhesive layer and the substrate structure (see Figure 7 Therefore, after a high temperature process such as a reflow process, the pickup performance is significantly reduced due to the high adhesive strength of the adhesive layer, and various problems such as adhesive residue may occur.

[0054] It can be seen that when acrylonitrile is added to the adhesive layer as in the split film according to the present invention (see Figure 5), the adhesive strength of the adhesive layer decreased after the heat treatment was performed after the UV treatment compared to the initial adhesive strength. This indicates that acrylonitrile is additionally cured at the process temperature of the reflow process (about 250°C), which improves the cohesion of the adhesive layer during the high-temperature heat treatment and inhibits the increase in adhesive strength even after the thermal history.

[0055] Finally, in the separation film according to the present invention, the adhesive strength of the adhesive layer constituting the separation film can be sufficiently reduced after heat treatment is performed thereon, and the semiconductor die can be easily separated from the separation film. Therefore, the inventors can know that there is an effect of improving the pickup performance of the semiconductor die.

[0056] Figure 6 is a flowchart of a method S1000 of manufacturing a semiconductor package according to an embodiment.

[0057] Reference Figure 6 , the method S1000 of manufacturing a semiconductor package may include a process sequence of a first operation S110 to a seventh operation S170 .

[0058] When specific embodiments may be implemented differently, specific process orders may be performed differently from the order described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the order described.

[0059] The method S1000 for manufacturing a semiconductor package according to the present invention may include a first operation S110 of preparing a substrate structure having a first surface bonded to a carrier substrate, a second operation S120 of bonding a second surface of the substrate structure opposite to the first surface to a dividing film, a third operation S130 of separating the carrier substrate from the substrate structure and performing a UV treatment on the separated substrate structure, a fourth operation S140 of bonding solder balls to the first surface of the substrate structure and performing a heat treatment thereon, a fifth operation S150 of separating the substrate structure into a plurality of semiconductor dies by cutting the substrate structure along dividing lines, a sixth operation S160 of peeling off and picking up the semiconductor dies from the dividing film, and a seventh operation S170 of respectively forming the semiconductor dies into semiconductor packages.

[0060] Refer to the following description Figures 7 to 16 The technical features of the first operation S110 to the seventh operation S170 will be described in detail.

[0061] Figures 7 to 16 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment.

[0062] Reference Figure 7 , a substrate structure SS formed on a carrier substrate CS may be prepared.

[0063] The carrier substrate CS may be a semiconductor substrate, a glass substrate, a ceramic substrate, or a plastic substrate. In some embodiments, a release film (not shown) may be bonded to the carrier substrate CS and components of the substrate structure SS may be sequentially formed on the release film. That is, the carrier substrate CS may be used as a supporting substrate to form the substrate structure SS.

[0064] Specifically, the substrate structure SS may include a first semiconductor chip 100 , a conductive pillar 200 around the first semiconductor chip 100 , a first wiring structure 300 under the first semiconductor chip 100 , and a second wiring structure 400 on the first semiconductor chip 100 .

[0065] The substrate structure SS may have a package-on-package (PoP) structure. Specifically, the substrate structure SS may be a fan-out semiconductor package in which the horizontal width and the horizontal area of ​​the first wiring structure 300 are greater than the horizontal width and the horizontal area of ​​the first semiconductor chip 100. In some embodiments, the substrate structure SS may be a fan-out wafer-level package (FOWLP) or a fan-out panel-level package (FOPLP).

[0066] In some embodiments, the first wiring structure 300 and the second wiring structure 400 may be formed by a redistribution process. Therefore, the first wiring structure 300 and the second wiring structure 400 may be referred to as a first redistribution structure and a second redistribution structure, respectively, or may be referred to as a lower redistribution structure and an upper redistribution structure, respectively.

[0067] The first wiring structure 300 may include a first redistribution insulation layer 310 and a plurality of first redistribution patterns 330. The first redistribution insulation layer 310 may surround the first redistribution patterns 330. In some embodiments, the first wiring structure 300 may include a plurality of first redistribution insulation layers 310 stacked.

[0068] The first redistribution pattern 330 may include a plurality of first redistribution line patterns 332 and a plurality of first redistribution vias 334. For example, the first redistribution patterns 330 may each be formed of and / or include a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy of the above metals, but the inventive concept is not limited thereto.

[0069] The first redistribution line pattern 332 may be disposed on at least one of the upper surface and the lower surface of the first redistribution insulation layer 310. For example, when the first wiring structure 300 includes a plurality of stacked first redistribution insulation layers 310, the first redistribution line pattern 332 may be disposed on the upper surface of the uppermost first redistribution insulation layer 310 and the lower surface of the lowermost first redistribution insulation layer 310, and may be located between the first redistribution insulation layers 310 adjacent to each other.

[0070] The first redistribution vias 334 may pass through the first redistribution insulation layer 310 and be connected to some of the first redistribution line patterns 332. In some embodiments, the first redistribution vias 334 may each have a tapered shape extending such that a horizontal width increases from bottom to top.

[0071] In some embodiments, some of the first redistribution line patterns 332 may be integrally formed with some of the first redistribution vias 334. For example, the first redistribution line patterns 332 and the first redistribution vias 334 contacting lower surfaces of the first redistribution line patterns 332 may be integrally formed together.

[0072] Some of the first redistribution patterns 330 disposed adjacent to the lower surface of the first wiring structure 300 may be referred to as a plurality of first lower surface connection pads 330P1, and some of the first redistribution patterns 330 disposed adjacent to the upper surface of the first wiring structure 300 may be referred to as a plurality of first upper surface connection pads 330P2. That is, the first lower surface connection pads 330P1 may be some of the first redistribution line patterns 332 disposed adjacent to the lower surface of the first wiring structure 300, and the first upper surface connection pads 330P2 may be some of the first redistribution line patterns 332 disposed adjacent to the upper surface of the first wiring structure 300.

[0073] The first upper surface connection pads 330P2 may be disposed on the upper surface of the first redistribution insulation layer 310. For example, when the first wiring structure 300 includes stacked first redistribution insulation layers 310, the first upper surface connection pads 330P2 may be disposed on the upper surface of the uppermost first redistribution insulation layer 310.

[0074] At least one first semiconductor chip 100 may be mounted on the first wiring structure 300. That is, one or more first semiconductor chips 100 may be provided. The first semiconductor chip 100 may include a semiconductor substrate 110 having an active surface and an inactive surface facing each other, a semiconductor device 112 on the active surface of the semiconductor substrate 110, and a plurality of chip pads 120 on the first semiconductor chip 100.

[0075] A plurality of chip connection members 130 may be located between the chip pad 120 of the first semiconductor chip 100 and some of the first upper surface connection pads 330P2 of the first wiring structure 300. For example, the chip connection members 130 may each be a solder ball or a microbump. The first semiconductor chip 100 and the first redistribution pattern 330 of the first wiring structure 300 may be electrically connected through the chip connection members 130. The chip connection member 130 may include an under bump metal (UBM) layer 132 disposed on the chip pad 120 and a conductive connection member 134 covering the UBM layer 132. The chip connection members 130 may each be formed of, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au) or solder and / or include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au) or solder, but the inventive concept is not limited thereto.

[0076] For example, the semiconductor substrate 110 may be formed of and / or include a semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, the semiconductor substrate 110 may be formed of and / or include a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate 110 may include a well doped with impurities as a conductive region. The semiconductor substrate 110 may have various device isolation structures, such as a shallow trench isolation (STI) structure.

[0077] A semiconductor device 112 including a plurality of individual devices of various types may be formed on an active surface of the semiconductor substrate 110. The individual devices may be electrically connected to a conductive region of the semiconductor substrate 110. The semiconductor device 112 may also include a conductive wiring or a conductive plug that electrically connects the individual devices to the conductive region of the semiconductor substrate 110. In addition, the individual devices may be electrically separated from other adjacent individual devices by insulating films, respectively.

[0078] In some embodiments, the first semiconductor chip 100 may include a logic device. For example, the first semiconductor chip 100 may be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. In other embodiments, when the substrate structure SS includes a plurality of first semiconductor chips 100, one of the first semiconductor chips 100 may be a CPU chip, a GPU chip, or an AP chip, and another of the first semiconductor chips 100 may be a memory semiconductor chip including a memory device.

[0079] For example, the memory device may be a non-volatile memory device such as a flash memory, a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In some embodiments, the memory device may be a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0080] The second wiring structure 400 may include a second redistribution insulation layer 410 and a plurality of second redistribution patterns 430. The second redistribution insulation layer 410 may surround the second redistribution patterns 430.

[0081] In some embodiments, the second wiring structure 400 may include a plurality of stacked second redistribution insulating layers 410. The second redistribution pattern 430 may include a plurality of second redistribution line patterns 432 and a plurality of second redistribution vias 434. The second redistribution pattern 430 may be formed of and / or include a metal or a metal alloy. In some embodiments, the second redistribution pattern 430 may be formed by stacking a metal or a metal alloy on a seed layer.

[0082] The second redistribution line pattern 432 may be disposed on at least one of the upper surface and the lower surface of the second redistribution insulation layer 410. For example, when the second wiring structure 400 includes a plurality of stacked second redistribution insulation layers 410, the second redistribution line pattern 432 may be disposed on the upper surface of the uppermost second redistribution insulation layer 410 and the lower surface of the lowermost second redistribution insulation layer 410, and may be located between the second redistribution insulation layers 410 adjacent to each other.

[0083] Some of the second redistribution patterns 430 disposed adjacent to the lower surface of the second wiring structure 400 may be referred to as a plurality of second lower surface connection pads 430P1, and some of the second redistribution patterns 430 disposed adjacent to the upper surface of the second wiring structure 400 may be referred to as a plurality of second upper surface connection pads 430P2. That is, the second lower surface connection pads 430P1 may be some of the second redistribution line patterns 432 disposed adjacent to the lower surface of the second wiring structure 400, and the second upper surface connection pads 430P2 may be some of the second redistribution line patterns 432 disposed adjacent to the upper surface of the second wiring structure 400. In other embodiments, the second lower surface connection pads 430P1 may be some of the second redistribution vias 434 disposed adjacent to the lower surface of the second wiring structure 400.

[0084] The second lower surface connection pads 430P1 may be disposed on the lower surface of the second redistribution insulation layer 410. For example, when the second wiring structure 400 includes stacked second redistribution insulation layers 410, the second lower surface connection pads 430P1 may be disposed on the lower surface of the lowermost second redistribution insulation layer 410.

[0085] The second upper surface connection pads 430P2 may be disposed on the upper surface of the second redistribution insulation layer 410. For example, when the second wiring structure 400 includes stacked second redistribution insulation layers 410, the second upper surface connection pads 430P2 may be disposed on the upper surface of the uppermost second redistribution insulation layer 410.

[0086] The second redistribution vias 434 may pass through the second redistribution insulating layer 410 and be connected in contact with some of the second redistribution line patterns 432. In some embodiments, some of the second redistribution line patterns 432 may be integrally formed with some of the second redistribution vias 434. For example, the second redistribution line patterns 432 and the second redistribution vias 434 in contact with the lower surfaces of the second redistribution line patterns 432 may be integrally formed together.

[0087] In some embodiments, the second redistribution vias 434 may each have a tapered shape extending such that the horizontal width decreases from top to bottom. That is, the first redistribution vias 334 and the second redistribution vias 434 extend in the same direction and may each have a shape with a decreasing horizontal width, but the inventive concept is not limited thereto.

[0088] The first redistribution insulating layer 310, the first redistribution pattern 330, the first redistribution line pattern 332, and the first redistribution via 334 may be referred to as a first insulating layer, a first wiring pattern, a first wiring line pattern, and a first wiring via, respectively. In addition, the second redistribution insulating layer 410, the second redistribution pattern 430, the second redistribution line pattern 432, and the second redistribution via 434 may be referred to as a second insulating layer, a second wiring pattern, a second wiring line pattern, and a second wiring via, respectively.

[0089] The package 250 may surround the first semiconductor chip 100 on the upper surface of the first wiring structure 300. The package 250 may fill the space between the first wiring structure 300 and the second wiring structure 400. For example, the package 250 may be a molding member including epoxy molding compound (EMC). The package 250 may further include a filler.

[0090] In some embodiments, an underfill layer 150 surrounding the chip connection member 130 may be located between the first semiconductor chip 100 and the first wiring structure 300. In some embodiments, the underfill layer 150 may fill the space between the first semiconductor chip 100 and the first wiring structure 300 and may cover a portion of the lower surface of the first semiconductor chip 100. The underfill layer 150 may be formed by, for example, a capillary underfill process and may include epoxy resin.

[0091] In some embodiments, side surfaces of the first wiring structure 300 , side surfaces of the package 250 , and side surfaces of the second wiring structure 400 may be aligned with each other in a vertical direction to be coplanar.

[0092] The plurality of conductive pillars 200 may penetrate the package 250 and electrically connect the first wiring structure 300 and the second wiring structure 400 to each other. The package 250 may surround the conductive pillars 200 .

[0093] The conductive pillar 200 may be located between the first wiring structure 300 and the second wiring structure 400 to be spaced apart from the first semiconductor chip 100 in a horizontal direction. For example, the conductive pillar 200 may be spaced apart from the first semiconductor chip 100 in a horizontal direction and may be arranged around the first semiconductor chip 100 in an outer region of the first wiring structure 300.

[0094] The conductive pillar 200 may be located between the first upper surface connection pad 330P2 and the second lower surface connection pad 430P1. The lower surface of the conductive pillar 200 may contact the first upper surface connection pad 330P2 of the first wiring structure 300 and be electrically connected to the first redistribution pattern 330, and the upper surface of the conductive pillar 200 may contact the second lower surface connection pad 430P1 of the second wiring structure 400 and be electrically connected to the second redistribution pattern 430.

[0095] The lower surface of the conductive pillar 200 may be in contact with the upper surface of the first upper surface connection pad 330P2. The upper surface of the conductive pillar 200 may be in contact with the lower surface of the second lower surface connection pad 430P1.

[0096] Reference Figure 8 , the exposed surface of the substrate structure SS may be bonded to the dividing film 10 .

[0097] The exposed surface of the substrate structure SS bonded with the carrier substrate CS may be mounted so as to be attached to the adhesive layer 15 of the dividing film 10. Figure 8As shown in , the edge portion of the adhesive layer 15 of the separation film 10 may be fixed to the lower portion of the frame 20. The frame 20 may have a circular ring shape, but the inventive concept is not limited thereto. When the substrate structure SS bonded to the carrier substrate CS is attached to the adhesive layer 15 of the separation film 10, the second wiring structure 400 formed on the substrate structure SS may be bonded to face the adhesive layer 15.

[0098] Reference Fig. 9 , the carrier substrate CS can be separated from the substrate structure SS.

[0099] In order to separate and remove the carrier substrate CS, laser P1 may be emitted to the carrier substrate CS. The emission of laser P1 may weaken the bonding force between the substrate structure SS and the carrier substrate CS, and the carrier substrate CS may be completely separated from the substrate structure SS.

[0100] In order to facilitate separation of the carrier substrate CS, an adhesive layer (not shown) may be located between the carrier substrate CS and the substrate structure SS. The adhesive layer may be in a liquid or gel form that may be easily deformed by specific heat caused by the emission of the laser P1.

[0101] Reference Fig.10 , UV light P2 can be emitted to the carrier substrate (see Fig. 9 CS) separates the exposed surface of the substrate structure SS.

[0102] UV light P2 can remove any residues that may remain on the carrier substrate (see Fig. 9 As described above, the adhesive layer (not shown) may be located on the carrier substrate (see Fig. 9 The adhesive layer may be in the form of liquid or gel between the CS and the substrate structure SS. Therefore, in order to completely separate, UV light P2 may be emitted to the exposed surface of the substrate structure SS.

[0103] As described above, due to the treatment using the UV light P2 , the adhesive strength of the adhesive layer 15 constituting the dividing film 10 increases compared to the initial adhesive strength.

[0104] Reference Fig.11 , the plurality of external connection terminals 600 may be bonded to some of the first lower surface connection pads 330P1, and the passive devices 610 may be bonded to other of the first lower surface connection pads 330P1.

[0105] External connection terminals 600 may be formed on the upper surface of the first wiring structure 300. The external connection terminals 600 may include, for example, solder balls, conductive bumps, conductive glue, ball grid array (BGA), lead grid array (LGA), pin grid array (PGA), or any combination thereof.

[0106] The passive device 610 may include at least one device selected from the group consisting of a resistor, a capacitor, an inductor, a thermistor, an oscillator, a ferrite bead, an antenna, and a varistor. For example, the passive device 610 may include a multilayer ceramic capacitor (MLCC), a low inductance chip capacitor (LICC), a pad side capacitor (LSC), an integrated passive device (IPD), etc., but the inventive concept is not limited thereto.

[0107] The reflow process may be performed to bond the external connection terminals 600 and the passive devices 610 to the first lower surface connection pads 330P1. For example, the reflow process may be a thermal treatment P3 performed in a temperature range of about 175°C to about 250°C.

[0108] After melting the solder constituting the external connection terminal 600 through a reflow process, the solder may be arranged in a spherical shape on the first lower surface connection pad 330P1 without collapsing due to surface tension. In some embodiments, an intermetallic compound may be formed at an interface between the external connection terminal 600 and the first lower surface connection pad 330P1.

[0109] As described above, due to the heat treatment P3 , the adhesive strength of the adhesive layer 15 constituting the dividing film 10 is reduced compared to the initial adhesive strength.

[0110] Reference Fig.12 , a space between the passive device 610 and the first wiring structure 300 may be filled with an underfill layer 650 .

[0111] The underfill layer 650 may surround the sidewalls of the solder bumps 630 disposed under the passive device 610 and fill the gaps between adjacent solder bumps 630. In the process of electrically connecting the passive device 610 to the solder bumps 630, a gap may be formed between the passive device 610 and the solder bumps 630. Because the gap may cause problems in the reliability of the connection between the passive device 610 and the solder bumps 630, the underfill layer 650 may be injected and cured to enhance the connection.

[0112] The passive device 610 may be more stably fixed on the solder bump 630 by the underfill layer 650. Even if the thermal expansion coefficients between the passive device 610 and the solder bump 630 are different, the passive device 610 and the solder bump 630 may not be electrically separated from each other.

[0113] Reference Fig.13 , as indicated by P4 , various components of the first wiring structure 300 including the substrate structure SS may be cut along the dividing lines DL.

[0114] Since the substrate structure SS may be a fan-out wafer level package or a fan-out panel level package, various types of material films including the first wiring structure 300 may be cut along the dividing lines DL and physically separated into individual semiconductor dies as indicated by P4. Fig.13 Only one dividing line DL is shown in FIG. 1 , but the inventive concept is not limited thereto.

[0115] Reference Fig.14 , the pressure P5 may be provided to the lower portion of the dividing film 10 to expand the surface area of ​​the dividing film 10 .

[0116] In some embodiments, a jig (not shown) may be attached to the lower portion of the dicing film 10, and the jig may be pushed upward to expand the dicing film 10. That is, a mechanical pressure P5 may be provided to the lower portion of the dicing film 10.

[0117] As the dividing film 10 is enlarged, it can be Fig.13 DL) will be the substrate structure (see Fig.13 The SS) is physically separated into a first semiconductor die SD1 and a second semiconductor die SD2. Fig.14 Only one first semiconductor die SD1 and only one second semiconductor die SD2 are shown in FIG. 1 , but the number of semiconductor dies is not limited thereto.

[0118] Reference Fig.15 , as indicated by P6 , the first semiconductor die SD1 may be picked up from the dividing film 10 by a picking-up device.

[0119] Because the adhesive strength of the adhesive layer 15 constituting the dividing film 10 is increased due to the previous heat treatment (see Fig.11 Therefore, as indicated by P6, the first semiconductor die SD1 can be easily picked up from the dividing film 10. Therefore, there is an effect of improving the pickup performance of the first semiconductor die SD1.

[0120] In some embodiments, a wet cleaning process may be performed to remove adhesive residue that may remain on the surface exposed when removing the dicing film 10 from the first semiconductor die SD1. The wet cleaning process may be performed by using an organic solvent or an inorganic solvent depending on the material constituting the adhesive layer 15 of the dicing film 10.

[0121] Reference Fig.16, the second semiconductor chip 500 may be mounted to be electrically connected to the second wiring structure 400 of the first semiconductor die SD1.

[0122] The second semiconductor chip 500 may be mounted on the second wiring structure 400 so that the plurality of upper connection pads 530 face the second wiring structure 400. The second semiconductor chip 500 may be electrically connected to the first redistribution pattern 330 of the first wiring structure 300 through the plurality of internal connection terminals 550 bonded to the upper connection pads 530, the plurality of second redistribution patterns 430, and the plurality of conductive pillars 200. In this manner, the semiconductor package 1000 may be completed.

[0123] As described above, in the method of manufacturing the semiconductor package 1000 according to the present inventive concept, the separation film (see Fig.15 10) adhesive layer (see Fig.15 15) can be sufficiently reduced in adhesive strength after heat treatment is performed thereon, and the semiconductor die can be bonded to the separation film (see Fig.15 10) is easily separated. Therefore, there is an effect of improving the pickup performance of the semiconductor die.

[0124] In addition, by using the partition film according to the present invention (see Figure 1 10) to transfer the semiconductor wafer. That is, by using a separation film (see Figure 1 10) as a transfer substrate to transfer the semiconductor wafer, it is possible to manufacture a semiconductor package without using a carrier substrate (or using a carrier substrate less frequently).

[0125] Figures 17 to 19 are diagrams illustrating other semiconductor packages manufactured by the method of manufacturing a semiconductor package according to the inventive concept.

[0126] Reference Fig.17 , the semiconductor package 1100 may include stacked semiconductor chips 740 stacked on a package substrate 701 .

[0127] The package substrate 701 may be a printed circuit board (PCB). In addition, solder bumps 703 as external connection terminals may be formed on a lower surface of the package substrate 701 .

[0128] The stacked semiconductor chip 740 may include a first semiconductor chip 710 and a plurality of second semiconductor chips 720 mounted on the first semiconductor chip 710. The second semiconductor chips 720 may be sequentially stacked in a vertical direction (Z direction) on the first semiconductor chip 710. The width of the first semiconductor chip 710 may be greater than the width of each of the second semiconductor chips 720.

[0129] although Fig.17 The stacked semiconductor chip 740 is shown to include four second semiconductor chips 720, but the present inventive concept is not limited thereto. For example, the stacked semiconductor chip 740 may include two or more second semiconductor chips 720. The first semiconductor chip 710 and the second semiconductor chip 720 may be separated by using a separation film according to the present inventive concept (see Figure 1 10) to manufacture.

[0130] The first semiconductor chip 710 may include a first pad 712a and a second pad 712b respectively located on two surfaces of the first semiconductor substrate 711. The first pad 712a and the second pad 712b may be electrically connected to each other by using a first through-hole member structure 713a. The first pad 712a may be electrically connected to the package substrate 701 by using a solder bump 705 as an external connection terminal. The active surface 711a of the first semiconductor chip 710 may be set downward. The first pad 712a may be a top pad, and the second pad 712b may be a bottom pad.

[0131] The second semiconductor chip 720 may each include a third pad 722a and a fourth pad 722b respectively located on two surfaces of the second semiconductor substrate 721. The third pad 722a and the fourth pad 722b may be electrically connected to each other by using a second through-hole member structure 723a. The third pad 722a may be electrically connected to the second semiconductor chip 720 by using an internal connection terminal 724. The internal connection terminal 724 may include an internal connection pad 724a and an internal bump 724b. The active surface 721a of each of the second semiconductor chip 720 may be set downward. The third pad 722a may be a top pad, and the fourth pad 722b may be a bottom pad.

[0132] The stacked semiconductor chip 740 may be bonded to the second semiconductor chip 720 through an adhesive layer 735. The second semiconductor chip 720 may be molded on the first semiconductor chip 710 through a mold layer 730.

[0133] Reference Fig.18 , the semiconductor package 1200 may include a plurality of stacked memory chips (HBM) 810 and a system on chip (SoC) 820 .

[0134] The stacked memory chip 810 and the system on chip 820 may be stacked on an interposer chip 830, and the interposer chip 830 may be stacked on a package substrate 840. The interposer chip 830 may be stacked on a package substrate 840 by using a segmentation film according to the inventive concept (see Figure 1 10) to manufacture.

[0135] The semiconductor package 1200 may transmit and receive signals with other external packages or electronic devices through the solder balls 801 bonded to the lower portion of the package substrate 840 .

[0136] The stacked memory chips 810 may each be implemented based on a high bandwidth memory (HBM) standard. However, the inventive concept is not limited thereto, and the stacked memory chips 810 may each be implemented based on a graphics double data rate (GDDR), a hardware management console (HMC), or a wide input / output (I / O) standard. The stacked memory chips 810 may each be implemented by using a segmentation film according to the inventive concept (see Figure 1 10) to implement.

[0137] The system on chip 820 may include at least one processor selected from an AP, a CPU, and a GPU, and a memory controller controlling the stacked memory chips 810. The system on chip 820 may transmit and receive signals to and from the corresponding stacked memory chips through the memory controller.

[0138] Reference Fig.19 , the semiconductor package 1300 may include a stacked memory chip 910 , a system on chip 920 , an interposer chip 930 , and a package substrate 940 .

[0139] The insert chip 930 can be inserted by using a separation film according to the present invention (see Figure 1 10). In addition, the stacked memory chip 910 may include a buffer die 911 and core dies 912 to 915. The stacked memory chip 910 may be manufactured by using a segmentation film according to the inventive concept (see Figure 1 10) to manufacture.

[0140] The core dies 912 to 915 may each include a memory unit storing data. The buffer die 911 may include a physical layer (PHY) 906 and a direct access area (DAB) 908. The physical layer 906 may be electrically connected to a physical layer 921 of a system on chip 920 through an interposer chip 930. The stacked memory chip 910 may receive a signal from the system on chip 920 through the physical layer 906, or may transmit a signal to the system on chip 920.

[0141] The direct access area 908 may provide an access path to test the stacked memory chips 910 without passing through the system on chip 920. The direct access area 908 may include a conductive device (e.g., a port or pin) that allows direct communication with an external test device. The test signal received by the direct access area 908 may be transmitted to the core die 912 to 915 by passing through the via structure. In order to test the core die 912 to 915, the data read from the core die 912 to 915 may be transmitted to the test device by passing through the via structure and the direct access area 908. Therefore, direct access testing may be performed on the core die 912 to 915.

[0142] The buffer die 911 and the core dies 912 to 915 may be electrically connected to each other through the through-via structures 931a and 933a and the bumps 935. The buffer die 911 and the core dies 912 to 915 may be electrically connected to each other through the through-via structures 931a and 933a and the bumps 935. Figure 1 10) to manufacture.

[0143] For example, the buffer die 911 may include a first through-via structure 931a. The core dies 912 to 915 may each include a second through-via structure 933a. The buffer die 911 may receive a signal provided to each channel through a bump 902 allocated to each channel from the system on chip 920, or may transmit a signal to the system on chip 920 through the bump 902. For example, the bump 902 may be a micro bump.

[0144] The system on chip 920 may execute an application supported by the semiconductor package 1300 by using the stacked memory chips 910. The system on chip 920 may be implemented by using a segmentation film according to the inventive concept (see Figure 1 10) to manufacture.

[0145] The system on chip 920 may control the overall operation of the stacked memory chip 910. The system on chip 920 may include a physical layer 921. The physical layer 921 may include an interface circuit that sends a signal to the physical layer 906 of the stacked memory chip 910 and receives a signal from the physical layer 906 of the stacked memory chip 910. The system on chip 920 may provide various signals to the physical layer 906 through the physical layer 921. The signal provided to the physical layer 906 may be sent to the core dies 912 to 915 through the physical layer 906 and the interface circuit passing through the via structures 931a and 933a.

[0146] The interposer chip 930 may connect the stacked memory chip 910 to the system on chip 920. The interposer chip 930 may connect the physical layer 906 of the stacked memory chip 910 to the physical layer 921 of the system on chip 920, and may provide a physical path formed by using a conductive material. Therefore, the stacked memory chip 910 and the system on chip 920 may be stacked on the interposer chip 930, and may transmit and receive signals to and from each other.

[0147] The bump 903 may be bonded to the upper portion of the package substrate 940, and the solder ball 904 may be bonded to the lower portion of the package substrate 940. For example, the bump 903 may be a flip chip bump. The interposer chip 930 may be stacked on the package substrate 940 through the bump 903. The semiconductor package 1300 may transmit signals to and receive signals from other external packages or electronic devices through the solder ball 904.

[0148] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A split film, comprising: Base layer; an intermediate layer, which is located on the base layer; as well as an adhesive layer, which is located on the intermediate layer, Wherein, the adhesive layer comprises an acrylate polymer composition containing acrylonitrile.

2. The splitting film according to claim 1, wherein: The adhesive strength of the adhesive layer increases after ultraviolet treatment is performed thereon, and the adhesive strength of the adhesive layer decreases after heat treatment is performed thereon.

3. The splitting film according to claim 2, wherein: The adhesive layer undergoes a crosslinking reaction from the following formula (1) to the following formula (2) during the heat treatment: [Formula (1)] [Formula (2)] 4. The splitting film according to claim 3, wherein: The temperature in the heat treatment is in the range of 175°C to 250°C, and According to formula (2), the adhesive strength of the adhesive layer decreases.

5. The splitting film according to claim 2, wherein: The adhesive strength of the adhesive layer after the UV treatment is greater than the initial adhesive strength of the adhesive layer, and The adhesive strength of the adhesive layer after the heat treatment is less than the initial adhesive strength of the adhesive layer.

6. The splitting film according to claim 1, wherein: The adhesive layer includes acrylonitrile in a range of 3 wt % to 50 wt %.

7. The splitting film according to claim 1, wherein: The thickness of the adhesive layer is greater than the thickness of the base layer, and The thickness of the base layer is greater than the thickness of the intermediate layer.

8. The split film according to claim 7, wherein: The adhesive layer comprises a single layer of a high temperature curable pressure sensitive adhesive, and The thickness of the adhesive layer is in the range of 30 μm to 40 μm.

9. The splitting film according to claim 8, wherein: The adhesive layer also includes a cross-linking agent and a photoinitiator.

10. The splitting film according to claim 1, wherein The base layer includes a material selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polyetheretherketone, and polyimide, and The intermediate layer includes an ultraviolet curable synthetic resin or a non-ultraviolet curable synthetic resin.

11. A pressure-sensitive adhesive comprising: An acrylate polymer composition comprising acrylonitrile in a range of 3 wt % to 50 wt %, wherein the adhesive strength of the pressure-sensitive adhesive is increased after ultraviolet treatment is performed thereon, and The adhesive strength of the pressure-sensitive adhesive decreases after heat treatment is performed thereon.

12. The pressure-sensitive adhesive according to claim 11, wherein The acrylonitrile forms trapezoidal polyacrylonitrile from polyacrylonitrile in the heat treatment at a temperature in a range of 175° C. to 250° C., and the adhesive strength of the pressure-sensitive adhesive is reduced due to high-temperature curing.

13. The pressure-sensitive adhesive according to claim 11, wherein The acrylic polymer composition includes at least one material selected from the group consisting of 2-ethylhexyl acrylate, 2-hydroxyethyl acrylate, and butyl acrylate.

14. The pressure-sensitive adhesive according to claim 11, further comprising azobisisobutyronitrile as a photoinitiator.

15. The pressure-sensitive adhesive according to claim 14, wherein The polymerization reaction of the acrylate polymer composition includes a free radical polymerization reaction using the photoinitiator.

16. A method for manufacturing a semiconductor package, the method comprising: preparing a substrate structure having a first surface bonded to a carrier substrate; bonding a second surface of the substrate structure opposite to the first surface to a dividing film; separating the carrier substrate from the substrate structure and performing ultraviolet treatment on the separated substrate structure; bonding solder balls to the first surface of the substrate structure and performing a heat treatment thereon; separating the substrate structure into a plurality of semiconductor dies by cutting the substrate structure along separation lines; peeling and picking up the semiconductor die from the separation film; as well as forming the semiconductor dies into semiconductor packages respectively, Wherein, the splitting film comprises: Base layer; an intermediate layer located on the base layer; and an adhesive layer located on the intermediate layer, and Wherein, the adhesive layer comprises an acrylate polymer composition containing acrylonitrile.

17. The method according to claim 16, wherein: The adhesive strength of the adhesive layer increases after the UV treatment, and The adhesive strength of the adhesive layer decreases after the heat treatment.

18. The method according to claim 17, wherein: The adhesive strength of the adhesive layer after the UV treatment is greater than the initial adhesive strength of the adhesive layer, and The adhesive strength of the adhesive layer after the heat treatment is less than the initial adhesive strength of the adhesive layer.

19. The method according to claim 16, wherein: The adhesive layer is formed into trapezoidal polyacrylonitrile from polyacrylonitrile at a specific temperature in the heat treatment, and the adhesive strength of the adhesive layer is reduced.

20. The method according to claim 19, wherein: A specific temperature in the heat treatment is in the range of 175°C to 250°C.

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