Connection body of mask and supporting part and manufacturing method thereof

Abstract

The invention relates to a connector of a mask and a support part and a manufacturing method thereof. The connector of the mask and the supporting part is used for a forming process of OLED pixels on a semiconductor wafer, and comprises the components of the supporting part which comprises an edge part and a grid part; and a mask connected to the support portion and including a plurality of unit portions on which a mask pattern is formed, at least a portion of the mask being disposed in a trench portion formed by sinking in the support portion.

Description

Technical Field

[0001] The present invention relates to a mask-support connection body and a manufacturing method thereof, and more particularly to a mask-support connection body used when forming pixels on a semiconductor wafer and capable of precisely forming an ultra-high-resolution mask pattern and a manufacturing method thereof. Background Art

[0002] As a technology for forming pixels in the OLED manufacturing process, the FMM (Fine Metal Mask) method is mainly used. In this method, a metal mask (Shadow Mask) in the form of a thin film is closely attached to a substrate and an organic substance is deposited at a desired position.

[0003] In the existing OLED manufacturing process, after manufacturing the mask film, the mask is welded to the OLED pixel deposition frame and used. However, it is difficult to align the large-area mask during the fixing process. In addition, during the welding and fixing process to the frame, the mask film is too thin and has a large area, so there is a problem of sagging or twisting due to the load.

[0004] In the ultra-high-definition OLED manufacturing process, even a slight alignment error of less than 1μm can cause pixel deposition failure, so it is necessary to develop technologies that can prevent deformation such as mask sagging or twisting and ensure accurate alignment.

[0005] In addition, micro displays used in VR (virtual reality) machines have recently attracted much attention. In order to present images in front of users in VR machines, the screen size of micro displays must not only be significantly smaller than existing displays, but also achieve high image quality within a tiny screen. Therefore, it is necessary to produce a mask pattern whose size is significantly smaller than the mask used in the existing ultra-high-definition OLED manufacturing process, and to perform more delicate alignment operations on the mask before the pixel deposition process. Summary of the invention

[0006] Technical issues

[0007] Therefore, the present invention is proposed to solve the problems in the prior art as described above, and aims to provide a connection body of a mask and a support portion capable of realizing ultra-high-quality pixels of a micro display and a method for manufacturing the same.

[0008] In addition, an object of the present invention is to provide a connection body of a mask and a support portion, which can improve the stability of pixel deposition by accurately aligning the mask, and a method for manufacturing the same.

[0009] However, the above technical problems are only exemplary, and the scope of the present invention is not limited thereto.

[0010] Technical Solution

[0011] The above-mentioned object of the present invention is achieved through a connector between a mask and a support portion, which is used in a process of forming an OLE pixel on a semiconductor wafer, and the connector includes: a support portion, which includes an edge portion and a grid portion; a mask, which is connected to the support portion and includes a plurality of unit portions formed with a mask pattern; at least a portion of the mask is arranged in a groove portion formed by a depression in the support portion.

[0012] The support portion and the mask have a circular shape, and the grid portion includes: a plurality of first grid portions, which are extended along a first direction and connected to the edge portion at both ends; and a plurality of second grid portions, which are extended along a second direction different from the first direction and intersect with the first grid portions and are connected to the edge portion at both ends.

[0013] The mask includes: a dummy portion connected to the edge portion; the plurality of unit portions, which are arranged at the center portion of the mask instead of at the dummy portion and include a plurality of mask patterns; a dividing portion, which is arranged at the center portion of the mask instead of at the dummy portion and is arranged between the plurality of unit portions, and the dividing portion is supported on the grid portion.

[0014] The dummy portion and the edge portion may share the same upper surface.

[0015] A dummy groove portion that is sunken may be formed on the grid portion.

[0016] A portion of the mask corresponding to the partition portion may be arranged in the dummy trench portion, so that the partition portion and the grid portion at least share a same upper surface.

[0017] The support portion is formed of a silicon wafer, the mask is formed on the silicon wafer by electroforming, and a connecting portion containing Ni and Si or a connecting portion containing Fe, Ni and Si is interposed between the support portion and the mask.

[0018] An auxiliary connecting part is sandwiched between the connecting part and the mask, and the auxiliary connecting part includes at least one of Ni, Cu, Ti, Au, Ag, Al, Sn, In, Bi, Zn, Sb, Ge, and Cd, and the thickness of the auxiliary connecting part is 0.01μm to 0.2μm.

[0019] The 100-plane or 111-plane crystal direction of the silicon wafer may be non-parallel to the length direction of the first grid portion or the second grid portion.

[0020] In addition, the above-mentioned purpose of the present invention can be achieved by a method for manufacturing a connector between a mask and a support portion, which connector is used in a process for forming an OLE pixel on a semiconductor chip, and the method includes the following steps: (a) preparing a support portion, wherein the support portion includes a first surface and a second surface opposite to the first surface and is a conductive substrate; (b) forming a groove portion by sinking the first surface of the support portion; (c) forming a mask by electroforming on the first surface of the support portion; (d) heat-treating the support portion and the mask; (e) etching the support portion on the second surface of the support portion to form an edge portion and a grid portion, wherein in the step (c), the mask is at least formed in the groove portion.

[0021] The step (b) forms a plurality of groove portions in a patterned form, and after the step (e), a portion between adjacent groove portions is provided as a mask pattern of the mask.

[0022] The step (b) may include: (b1) forming a first insulating portion on the first surface of the support portion; and (b2) etching the support portion exposed between the first insulating portions to form the groove portion.

[0023] In the step (c), the mask may be electroformed so that the upper end of the mask is higher than the height of the first surface of the support portion and lower than the height of the upper end of the first insulating portion.

[0024] A step of removing the first insulating portion is further included between the step (b) and the step (c), and the step (c) is to electroform the mask so that the upper end of the mask is higher than the height of the first surface of the support portion.

[0025] The (c) step may include: (c1) applying a first current density and forming a first mask layer containing more than 60wt% Ni on at least a portion of the lower surface and side surfaces of the groove portion; (c2) applying a second current density different from the first current density and forming a second mask layer of an FeNi alloy material containing 36wt% to 42wt% Ni on the first mask layer.

[0026] The thickness of the first mask layer may be 2% to 20% of the thickness of the second mask layer.

[0027] The method may further include: (c3) applying a first current density different from the second current density, and forming a third mask layer containing more than 60 wt % of Ni on the second mask layer, wherein the thickness of the third mask layer is 2% to 20% of the thickness of the second mask layer.

[0028] After the heat treatment in step (d), the support portion and the mask may be connected by interposing a connecting portion containing Ni and Si or a connecting portion containing Fe, Ni and Si, and the heat treatment in step (d) is performed at 100°C to 800°C.

[0029] The connection portion may be formed between at least a portion of a lower surface and a side surface of the groove portion and the mask.

[0030] In the step (b), a dummy groove portion is further formed by being sunken on the support portion corresponding to the region where the grid portion is formed. In the step (c), the mask is formed at least in the groove portion and the dummy groove portion.

[0031] Beneficial Effects

[0032] According to the present invention constructed as described above, it is possible to realize ultra-high-quality pixels of a micro display.

[0033] Furthermore, the present invention has the effect of improving the stability of pixel deposition by allowing the mask to be accurately aligned.

[0034] Furthermore, the invention has the effect that all parts of the mask maintain a uniform pressure level.

[0035] Of course, the scope of the present invention is not limited by the above-mentioned effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 FIG. 4 is a schematic diagram of a connection body between a mask and a support portion according to an embodiment of the present invention.

[0037] Figure 2 yes Figure 1 Side cross-sectional view of AA′.

[0038] Figure 3 1 is a top view and a side cross-sectional view taken along line EE′ of a mask according to an embodiment of the present invention.

[0039] Figure 4 FIG. 1 is a top view of a support portion according to an embodiment of the present invention.

[0040] Figures 5 to 11 It is a schematic diagram of the manufacturing process of the connection body between the mask and the support part according to the first embodiment of the present invention.

[0041] Figures 12 to 16 Schematic diagram of the manufacturing process of the connector between the mask and the support portion according to the second embodiment of the present invention.

[0042] Fig.17 1 is a top view of a mask according to another embodiment of the present invention and a side cross-sectional view of EE′ or FF′.

[0043] Fig.18 4 is a top view of a support portion according to another embodiment of the present invention.

[0044] Fig.19 It is a schematic diagram of a mask planarization process and a dummy trench portion of a grid portion according to an embodiment of the present invention.

[0045] Fig. 20 1 is a top view of a mask pattern and a dummy trench portion of a grid portion and a side cross-sectional view of GG′ according to an embodiment of the present invention.

[0046] Fig.21 Schematic diagram of an OLED pixel deposition device using a connector between a mask and a support portion according to an embodiment of the present invention.

[0047] [Description of Reference Numerals]

[0048] 10: Connector between mask and support

[0049] 20: Mask

[0050] 30: Support

[0051] 31: Edge

[0052] 33, 35: first grid part, second grid part

[0053] 40: Connection

[0054] 1000: OLED pixel deposition device

[0055] C, SR, DM: unit part, partition part, dummy part

[0056] H: Heat treatment

[0057] P: Mask pattern

[0058] PS: Flattening

[0059] TR, DTR: Groove part, dummy groove part DETAILED DESCRIPTION

[0060] Below, the present invention is described in detail with reference to the accompanying drawings, which are used to illustrate examples of specific embodiments that can be implemented as the present invention. These embodiments are described in detail so that those skilled in the art can fully implement the present invention. Various embodiments of the present invention should be understood to be different from each other but not mutually exclusive. For example, the specific shapes, structures and characteristics recorded herein can be implemented as other embodiments without exceeding the spirit and scope of the present invention. In addition, the position or arrangement of individual components in each disclosed embodiment should be understood to be changeable without exceeding the spirit and scope of the present invention. Therefore, the following detailed description is not intended to limit the present invention. As long as it can be properly explained, the scope of the present invention is limited only by the attached claims and all scopes equivalent thereto. Similar figure marks in the drawings refer to the same or similar functions in various aspects, and for convenience, length, area, thickness, etc. and their forms can also be exaggerated.

[0061] In the following, in order to enable those skilled in the art to easily implement the present invention, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0062] Figure 1 FIG. 1 is a schematic diagram of a connection body 10 between a mask and a support portion according to an embodiment of the present invention. Figure 2 yes Figure 1 Side cross-sectional view of AA′. Figure 3 1 is a top view and a side cross-sectional view taken along line EE′ of a mask 20 according to an embodiment of the present invention. Figure 4 FIG. 4 is a top view of a support portion 30 according to an embodiment of the present invention.

[0063] Recently, micro displays used in VR (virtual reality) devices can be used to display target substrates 1900 (see Fig.21 ) rather than a large-area substrate for pixel deposition. Since the screen of a micro display is located in front of the user's eyes, it has a screen size of about 1 to 2 inches compared to a large-area size. In addition, since it is closer to the user's eyes, it is necessary to achieve a higher resolution.

[0064] Therefore, the object of the present invention is to provide a connector 10 of a mask and a support portion and a method for manufacturing the same, wherein the connector is not used in a pixel forming process on a large-area target substrate with a side length exceeding 1000m, but is used in a pixel forming process on a semiconductor chip target substrate 1900 of the 200mm, 300mm, or 450mm level and can form pixels of ultra-high image quality.

[0065] For example, the current QHD image quality uses 500 to 600 PPI to make the pixel size reach about 30 to 50 μm. For 4K UHD and 8K UHD high image quality, they have higher resolutions of less than or equal to 860 PPI, less than or equal to 1600 PPI, etc. The microdisplay directly used in the VR machine or the microdisplay inserted into the VR machine aims at ultra-high image quality of about 2000 PPI or above, and the pixel size is about 5 to 10 μm. For semiconductor wafers and silicon wafers, by utilizing the technology developed in the semiconductor process, it is possible to perform fine and precise processes compared to glass substrates, so that they can be used as substrates for high-resolution microdisplays. The present invention is characterized in that a connector 10 of a mask and a support portion that can be formed on these semiconductor wafers is provided.

[0066] Reference Figure 1 and Figure 2 The present invention is characterized in that, in order to use the semiconductor wafer as the target substrate 1900 (refer to Fig.21 ) performs pixel deposition process, and the mask 20 has a shape corresponding to the semiconductor wafer (or silicon wafer). It should be pointed out that the shape of the mask 20 corresponding to the semiconductor wafer means that the mask 20 has the same size and shape as the semiconductor wafer, or although it has a different size and shape from the semiconductor wafer, it at least forms a coaxial shape, and even includes a state in which the mask pattern P is arranged within the shape of the semiconductor wafer. Another feature is that the mask 20 corresponding to the shape of the semiconductor wafer is integrally connected to the support portion 30 that acts as a frame, so that the mask is accurately aligned.

[0067] The mask and support part connector 10 may include a mask 20 and a support part 30. The mask 20 may be connected to one surface of the support part 30. The support part 30 may function as a frame for supporting the mask 20.

[0068] Reference Figures 1 to 3 , the mask 20 may include a unit portion C, a dividing portion SR, and a dummy portion DM. The portion of the mask 20 that is not in contact with the support portion 30 and is formed with a mask pattern P is represented as a unit portion C, the portion arranged between the unit portions C is represented as a dividing portion SR, and the portion attached to the support portion 30 is represented as a dummy portion DM. The unit portion C, the dividing portion SR, and the circular dummy portion DM are represented by different names and different figure marks according to the positions where they are formed, but the unit portion C, the dividing portion SR, and the dummy portion DM are not separate areas from each other, but have the same material and are connected as a whole. In other words, the unit portion C, the dividing portion SR, and the circular dummy portion DM are parts of the mask 20 that are formed simultaneously in the electroforming process. In the following description, the unit portion C, the dividing portion SR, and the dummy portion DM can be mixed with the mask 20.

[0069] The mask 20 is preferably made of Invar alloy or super Invar alloy. Alternatively, the mask 20 may also be made of nickel (Ni), cobalt (Co), titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), etc., or a combination or alloy thereof that can be electroformed and can form the support portion 30' (or the conductive substrate 30', see Figure 5 ) and a metal material of silicide. Alternatively, the mask 20 may also include a super-Invar alloy material containing Co of a ternary system or more. The mask 20 may be circular in shape to correspond to a circular semiconductor wafer. The mask 20 may have a size equal to or greater than that of a semiconductor wafer of 200 mm, 300 mm, 450 mm, etc.

[0070] In order to cope with large-area substrates, existing masks have shapes such as quadrilaterals and polygons. In addition, in order to correspond to the mask, the frame also has shapes such as quadrilaterals and polygons. Since the mask includes angular corners, there is a problem of stress concentration on the corners. The concentrated pressure causes only a part of the mask to be applied with different forces, which may cause the mask to be distorted or deformed, which will further lead to pixel alignment failure. In particular, in ultra-high image quality above 2000PPI, stress concentration on the mask corners should be avoided.

[0071] Therefore, the present invention is characterized in that the mask 20 is circular in shape and does not include corners. That is, the dummy portion DM of the mask 20 is circular in shape and does not include corners. Since there is no corner, the problem of different forces being applied to specific parts of the mask 20 can be solved, and the pressure can be evenly dispersed along the circular edge. Therefore, the mask 20 does not twist or deform, which helps to accurately align the pixels and has the advantage of being able to achieve a mask pattern P of more than 2000PPI. The present invention can deposit pixels of about 5 to 10μm by matching a circular semiconductor wafer (or silicon wafer) with a low thermal expansion coefficient with a circular mask 20 with evenly dispersed pressure along the edge and performing a pixel deposition process.

[0072] The unit portion C may be formed with a plurality of mask patterns P. The mask pattern P has a plurality of pixel patterns P corresponding to R, G, and B. The side of the mask pattern P may be an inclined shape, a tapered shape, or a shape in which the pattern width gradually widens from top to bottom. A large number of mask patterns P are clustered together to form a display unit portion C. The display unit portion C is a display corresponding area with a diagonal length of about 1 to 2 inches. Alternatively, the display unit portion C may also be an area corresponding to multiple displays.

[0073] The mask pattern P may have a substantially conical shape, and the pattern width may be several to more than ten μm in size, preferably about 5 to 10 μm in size (resolution of 2000 PPI or more).

[0074] The mask 20 may include a plurality of unit parts C. The plurality of unit parts C may be arranged at preset intervals in a first direction (x-axis direction) and a second direction (y-axis direction) perpendicular to the first direction. Figure 1 Twenty-one unit portions C arranged along the first direction and the second direction are illustrated, but are not limited thereto. Division portions SR may be arranged between the unit portions C. The unit portions C and the division portions SR are portions arranged at the center portion of the mask 20 other than the dummy portion DM.

[0075] The dummy part DM has a circular edge or a shape corresponding to a semiconductor wafer, and can define the appearance of the mask 20. The dummy part DM may be connected to the support part 30. Specifically, the dummy part DM may be attached to at least a portion of the edge part 31 of the support part 30. Based on the connection part 40 formed between the dummy part DM and the edge part 31, they may be attached to each other.

[0076] Reference Figure 1 , Figure 2 and Figure 4 , the support portion 30 may include an edge portion 31, a plurality of first grid portions 33, and a plurality of second grid portions 35. Although the edge portion 31, the first grid portion 33, and the second grid portion 35 are represented by different names and different reference numerals, the edge portion 31, the first grid portion 33, and the second grid portion 35 are not separate areas, but have the same material and are connected as a whole. In the following description, the edge portion 31, the first grid portion 33, and the second grid portion 35 can be used interchangeably with the support portion 30.

[0077] The support portion 30 is preferably made of silicon. More preferably, the support portion 30 may be formed of a silicon wafer and may be made of single crystal silicon. Fig.21 ) corresponding to the circular semiconductor wafer, the edge portion 31 of the support portion 30 may be in a circular shape. In order to connect the mask 20 to the upper portion, the support portion 30 may be at least larger than or equal to the shape of the mask 20.

[0078] The edge portion 31 may define the appearance of the support portion 30. The edge portion 31 may be circular in shape. As long as the electroforming of the mask 20 is convenient and the support portion 30 corresponds to the semiconductor wafer and can perform the OLED pixel process, it may also have other shapes.

[0079] A plurality of first grid portions 33 are formed to extend in a first direction, and both ends of the plurality of second grid portions 35 are connected to the edge portion 31. In addition, a plurality of second grid portions 35 are formed to extend in a second direction different from the first direction and intersect with the first grid portions 33, and both ends of the plurality of second grid portions 35 are connected to the edge portion 31. As an example, the first direction is the x-axis direction, the second direction is the y-axis direction, and the first direction and the second direction may be perpendicular to each other. The first grid portions 33 are spaced apart and arranged in parallel, and the second grid portions 35 are spaced apart and arranged in parallel. In addition, the first grid portions 33 and the second grid portions 35 are intersected, and the intersecting portions present a mesh-like free space CR. The free space CR is referred to as a unit region CR (refer to Figure 4 ).

[0080] The thickness of the support portion 30 may be greater than the thickness of the mask 20. In order to realize a mask pattern P having a resolution higher than 2000 PPI (pixel per inch), the mask 20 may be formed with a thickness of about 2 μm to 12 μm. If the thickness of the mask 20 is greater than this thickness, it may be difficult for the width of the mask pattern P having a tapered shape as a whole or the pitch of the mask pattern P to meet the resolution.

[0081] The support portion 30 has rigidity to support the mask 20 , and may be formed with a thickness of about 50 μm to 200 μm in consideration of easy formability of the edge portion 31 and the grid portions 33 and 35 , reduction of shadow effects, handleability, and the like.

[0082] As an example, the edge portion 31 and the first grid portion 33 / second grid portion 35 of the support portion 30 may have the same thickness. The thickness of the edge portion 31 , the first grid portion 33 and the second grid portion 35 may be approximately 50 μm to 200 μm by thinning the silicon wafer.

[0083] As another example, the thickness of the edge portion 31 in the support portion 30 may also be greater than the thickness of the first grid portion 33 / the second grid portion 35. The edge portion 31 plays the role of a frame on the connector 10 between the mask 20 and the support portion 30, has rigidity to support the mask 20, and in order to prevent the support portion 30 from being deformed or bent as a whole, the thickness may be greater than the first grid portion 33 and the second grid portion 35. As an example, when a silicon wafer is directly used, the thickness of the edge portion 31 may be about 700 μm to 1000 μm, and when the predetermined thickness is reduced, it may be about 500 μm to 1000 μm.

[0084] The thickness of the first grid portion 33 and the second grid portion 35 is at least enough to support the mask 20, and a unit region CR (see Figure 4), in order to prevent the organic matter 1600 from showing a shadow effect based on the thickness of the first grid portion 33 and the second grid portion 35, it is preferably greater than the thickness of the mask 20 and less than the thickness of the edge portion 31. As an example, the thickness of the first grid portion 33 and the second grid portion 35 may be about 50 μm to 200 μm.

[0085] In addition, the mask and support portion connector 10 of the present invention is characterized in that at least a portion of the mask 20 is arranged in the groove portion TR formed by the depression of the support portion 30. The groove portion TR has two side surfaces SS [refer to Figure 5 ] in the state, it can be a trench shape formed by depression. It can be understood that it also includes a step shape formed by depression in the state with only one side SS. Figure 2 The connection body 10 of the mask and the support portion: 10-1 shows an example of a groove portion TR having a lower surface 37a and a side surface 37b and a step 37. In addition, Fig. 20 (b) shows an example of the second grid portion 35 having a groove portion whose side surface is inclined like a taper.

[0086] From another point of view, it can be understood that in the connector 10 of the mask and the support portion of the present invention, the upper surface of the support portion 30 and the upper surface of the mask 20 are located on the same horizontal plane. A portion of the mask 20 is arranged in the groove portion TR formed by the depression of the support portion 30, so that the upper surfaces of the support portion 30 and the mask 20 have the same horizontal plane. In particular, referring to Figure 2 , the dummy portion DM of the mask 20 and the edge portion 31 of the support portion 30 may share the same upper surface.

[0087] As described above, the connector 10 of the mask and the support portion has the effect of more firmly anchoring the mask 20 in the groove portion TR by placing or accommodating at least a portion of the mask 20 in the groove portion TR of the support portion 30. As a result, the alignment of the mask 20 and the alignment of the mask pattern P / unit portion C can be made more accurate, thereby achieving ultra-high-quality pixels.

[0088] Re-reference Figure 2 , a connection portion 40 may be sandwiched between the mask 20 and the support portion 30. The connection portion 40 may be formed on the lower surface BS and the side surface SS of the groove portion TR [refer to Figure 5 ] between at least a portion of the support portion 30 and the mask 20. The mask 20 can be connected to the support portion 30 by sandwiching the connecting portion 40. The edge portion 31 of the support portion 30 can be connected to the dummy portion DM of the mask 20, and the first grid portion 33 and the second grid portion 35 of the support portion 30 can be connected to the partition portion SR of the mask 20. That is, the partition portion SR can be supported on the first grid portion 33 and the second grid portion 35.

[0089] According to an embodiment, the connection portion 40 may be formed on the support portion 30 in a laminated state of the mask 20 by heat treatment H (refer to Figure 8 ) is formed. At this time, the connection portion 40 can be provided as an intermetallic compound synthesized by the components of the mask 20 and the components of the support portion 30. By synthesizing the Fe and Ni components of the mask 20 and the Si component of the support portion 30, the connection portion 40 can be provided as a silicide containing Ni and Si or containing Fe, Ni and Si or containing Fe and Ni. Based on the bonding force of the intermetallic compound, the mask 20 and the support portion 30 can be connected to each other by sandwiching the connection portion 40.

[0090] In addition, according to one embodiment, in order to form the mask 20 on the support part 30 with higher adhesion, the connection part 40 may further include an adhesion layer (adhesion layer) as an adhesion medium [or an auxiliary connection part (not shown)]. As an example, when the support part 30 is a silicon wafer, compared with the state in which the mask 20 made of materials such as Invar alloy and super Invar alloy is directly bonded to the support part 30, the state in which the auxiliary connection part made of materials such as Ni and Cu is used as a medium for bonding has higher adhesion. In view of this, the auxiliary connection part may include at least one of Ni, Cu, Ti, Au, Ag, Al, Sn, In, Bi, Zn, Sb, Ge, and Cd. In order to strengthen the adhesion between the support part 30 and the mask 20 or the support part 30 and the connection part 40, the auxiliary connection part is preferably sandwiched with a relatively thin thickness. In order to prevent the electromagnetic field formed by electroforming the mask 20 on the support part 30 from being affected, the auxiliary connection part may be formed with a relatively thin thickness of 0.01 μm to 0.2 μm. Within the above thickness range, an electromagnetic field for electroforming can be used to form a channel while providing a thickness for enhancing adhesion.

[0091] The connection portion 40 may be formed on the lower surface of the mask 20 or on the side surface between the mask patterns P. Alternatively, the connection portion 40 may be partially or completely removed during the process of forming the edge portion 31 and the first grid portion 33 and the second grid portion 35 on the support portion 30. For ease of explanation, Figure 2 and Figure 3 The thickness of the connecting portion 40 is exaggerated in the figure. Compared with the thickness of the mask 20 or the width of the mask pattern P, the connecting portion 40 has a very thin thickness [less than 1 μm, preferably less than 0.1 μm]. Even if part or all of the connecting portion 40 is removed, it will hardly affect the thickness of the mask 20 or the width of the mask pattern P.

[0092] In addition, the edge of the support portion 30 is also circular like the mask 20, and there is no corner, so that the problem of applying different forces to specific parts of the support portion 30 can be solved. In addition, the pressure can be evenly dispersed along the circular edge. Therefore, the support portion 30 can help prevent distortion or deformation. Connecting a circular mask 20 to such a circular support portion 30 can have the effect of doubling the pressure dispersion. In addition, the first grid portion 33 and the second grid portion 35 of the support portion 30 are arranged at the bottom of the dividing portion SR of the mask 20, and the mask 20 is supported as a whole, thereby preventing the unit portion C and the dividing portion SR in the mask 20 with a very thin thickness from sagging. As a result, the mask 20 and the support portion 30 are not distorted, and can help to accurately align pixels, with the effect of being able to achieve a high resolution of more than 2000PPI.

[0093] In addition, refer again Figure 3 , the 100-plane crystal orientation CO or the 111-plane crystal orientation CO of the silicon wafer may not be parallel to the length direction of the first grid portion 33 and the second grid portion 35. The first grid portion 33 and the second grid portion 35 are formed along the X-axis direction or the Y-axis direction, and the 100-plane or 111-plane crystal orientation CO of the silicon wafer of the support portion 30 may have a preset angle other than 0° or 180°, and is not parallel to the X-axis or Y-axis direction (0° or 180° angle). From another point of view, the 100-plane or 111-plane crystal orientation CO of the silicon wafer may be at a preset angle other than 0° or 180° to the direction in which a plurality of unit portions C are arranged, that is, the X-axis or Y-axis direction. The possibility of a silicon wafer breaking along the 100-plane or 111-plane crystal direction CO is higher than that along other crystal directions. By arranging the unit portion C, the dividing portion SR, etc. of the mask 20 corresponding to the first grid portion 33 and the second grid portion 35 to be staggered with the crystal direction CO, it has the advantage of reducing the risk of damage to the connector 10 between the mask 20 and the support portion 30 and increasing the overall rigidity.

[0094] Figures 5 to 11 1 is a schematic diagram of the manufacturing process of the mask-support connection body 10 of the first embodiment of the present invention. Although the following diagram shows the form of the mask-support connection body 10-2 in which the mask 20 is arranged on the upper surface of the edge portion 31 as a whole, it should be noted that the manufacturing process also includes manufacturing Figure 2 The process shown is that a groove portion in the form of a step 37 is formed on the edge portion 31 and a mask-supporting portion connector 10 - 1 in the form of a mask 20 is arranged on the upper portion.

[0095] Reference Figure 5, prepare the support part 30'. In order to perform electroforming, the support part 30' may be a conductive substrate 30' made of a conductive material. In order to have conductivity and low resistance, 10 19 cm -3 The doping may be performed on the entire support portion 30' or only on the surface portion of the support portion 30'. According to one embodiment, the surface resistance of the support portion 30' may be 5×10 -4 Up to 1×10 -2 The support portion 30' can be used as a cathode electrode during the electroforming process.

[0096] Unlike metals with metal oxides on the surface and polycrystalline silicon with grain boundaries, doped single-crystal silicon has the advantage of forming a uniform electromagnetic field on the entire surface during electroforming and forming a uniform electroplating film (or mask 20) ​​due to the absence of defects. The mask 20 made of a uniform electroplating film can further improve the image quality of OLED pixels. In addition, there is no need to perform additional processes to remove and eliminate defects, which has the advantages of reducing process costs and improving production efficiency.

[0097] Then, a patterned insulating portion M1 may be formed on one side of the support portion 30'. The insulating portion M1, as a portion protruding (bump) on one side of the support portion 30', may have insulating properties in order to prevent the formation of an electroplated film (or mask 20). Therefore, the insulating portion M1 may be formed of any one of photoresist, silicon oxide, and silicon nitride. The insulating portion M1 may be formed of silicon oxide or silicon nitride on the support portion 30' by deposition or other methods, and thermal oxidation (Thermal Oxidation) and thermal nitridation (Thermal Nitiridation) methods may also be used with the support portion 30' as a substrate. Photoresist may also be formed by printing or other methods.

[0098] The width md of the insulating portion M1 may correspond to the upper width of the mask pattern P. The upper width of the mask pattern P, as the terminal portion for the organic matter 1600 to pass through during the deposition of the OLED pixel, may determine the resolution of the pixel. When aiming at ultra-high image quality of about 2000 PPI or above, the pixel size is about 5 to 10 μm, so the width md of the insulating portion M1 may also be about 5 to 10 μm. In addition, as described later, by forming the groove portion TR in the support portion 30′, the insulating portion M1 may be formed with a thinner thickness within the range for forming the groove portion TR. Considering that the groove portion TR corresponds to the thickness of the mask 20 (about 2 to 12 μm), the insulating portion M1 may be formed thinner at about 0.5 to 2 μm. Therefore, it has the advantages of being easy to form the insulating portion M1 and reducing the material.

[0099] Then, the support portion 30' may be etched EC1. The surface of the first side (or upper side) of the support portion 30' exposed between the patterns of the insulating portion M1 may be etched EC1. Dry etching or wet etching may be used to etch EC1. Wet etching has isotropic etching characteristics, while dry etching has anisotropic characteristics and has the advantage of being able to etch accurately with a desired width. Alternatively, laser etching that can perform precise etching using femtosecond or picosecond lasers may also be performed. For laser etching, the process of forming the first insulating portion M1 may be omitted.

[0100] Based on the etching process EC1, a recessed trench TR may be formed on the first surface (or upper surface) of the support portion 30'. The depth h of the trench TR may substantially correspond to the thickness of the mask 20 to be formed. As an example, the depth h of the trench TR may be about 2 to 12 μm.

[0101] A plurality of groove portions TR may be formed by patterning. The groove portion TR may be formed on the support portion 30' corresponding to the unit portion C in a manner corresponding to the mask pattern P in reverse. In other words, the portion of the unit portion C where the groove portion TR is not formed may be used as the mask pattern P later. Figure 2 As shown, a groove portion in the form of a step difference 37: 37a, 37b may be formed, a groove portion TR having two side surfaces may be formed, or no groove portion TR may be formed. No groove portion TR may be formed on the support portion 30' corresponding to the dividing portion SR, or a groove portion TR may be formed as shown in FIG. Fig.19 and Fig. 20 The dummy trench portion DTR is shown.

[0102] The groove portion TR may include a lower surface BS and a side surface SS. The side surface SS may be formed to be inclined to have a vertical or preset angle. When the wet etching EC1 is used, since the wet etching has an isotropic etching characteristic, the side surface SS may be formed to have a preset angle. That is, the side surface SS of the groove portion TR may be formed in a tapered shape. Considering the crystallization direction of the support portion 30' of the single crystal silicon material, when etching is performed, the tapered angle of the groove portion TR may be formed to correspond to the etching direction.

[0103] Reference Figure 6 , electroforming can be performed on the support portion 30' and a mask 20': 20'a can be formed. The support portion 30' is used as a cathode, and an anode (not shown) opposite thereto is prepared. The anode (not shown) can be immersed in a plating solution (not shown), and the support portion 30' can be immersed in the plating solution (not shown) in whole or in part. Since the insulating portion M1 has insulating properties, an electroplated film may not be formed on the portion corresponding to the insulating portion M1. In particular, the electroplated film is formed in the groove portion TR and forms the mask 20'. The mask 20' is formed with a thickness that fills the groove portion TR and does not exceed the upper portion of the insulating portion M1. In other words, the mask 20' can be electroformed so that the upper end of the mask 20' is higher than the height of the first surface (or upper surface) of the support portion 30' and lower than the height of the upper end of the insulating portion M1.

[0104] In addition, in order to make the mask 20' have a coefficient of thermal expansion (CTE) similar to that of the silicon material of the support part 30', its composition can be controlled. In the connector 10 of the mask and the support part, the support part 30 acts as a frame of the silicon material, and the mask 20 should have a coefficient of thermal expansion similar to that of the support part 30, so as to avoid sagging of the mask 20 on the support part 30 as a frame. In addition, the alignment error between the unit part C and the mask pattern P on the support part 30 can be minimized, that is, the change of PPA (pixel position accuracy).

[0105] In view of this, in order to make the thermal expansion coefficient of the support portion 30' made of silicon material and the mask 20' after the heat treatment H described later to be approximately (3.5±1)×10 -6 / °C, the composition of the mask 20' can be controlled. Even if the mask 20' is made of Invar alloy, it can be electroformed according to different composition ratios of Fe and Ni to control the thermal expansion coefficient to the extent that it is closest to the support part 30' made of silicon. Alternatively, in order to make the mask 20' tightly connected to the support part 30' according to the process temperature conditions, the thermal expansion coefficient of the mask 20' can also be controlled to be greater than or less than the thermal expansion coefficient of the support part 30'.

[0106] Furthermore, during the heat treatment H, etching EC2, etc. described later, the mask 20' formed by electroforming should be firmly bonded to the support portion 30' without peeling off. To this end, various solutions are conceivable.

[0107] As one solution, first, the native oxide of the support portion 30' to be electroformed can be controlled. Oxide can be formed on the surface of the support portion 30' made of silicon wafer material. Since the surface of such oxide cannot generate a uniform electromagnetic field, the electroplated film (mask 20') cannot be uniformly generated, and the adhesion between the generated electroplated film (mask 20') and the support portion 30' remains low. Therefore, the electroplating process is preferably performed after the process of removing the native oxide is performed.

[0108] As another embodiment, another film may be further formed between the plating film (mask 20') and the support portion 30' as an adhesive medium. In addition to the barrier film described below, a film or a combination of films having adhesive strength on both sides may be used.

[0109] As another solution, the surface of the support portion 30' may be pre-treated before electroforming. The electroplated film (mask 20') generated in the electroforming process may be formed on the support portion 30' with stronger adhesion by physical treatment or chemical treatment. In addition, by controlling the gold plating method in the electroforming process, the electroplated film (mask 20') may have stronger adhesion when it is formed on the support portion 30'.

[0110] In addition, refer to Figure 7 In order to make the mask 20′: 20′b have a thermal expansion coefficient similar to that of the silicon material of the support portion 30′, the mask layer 20′b may be composed of a stack of at least two electroplated layers. At this time, the first mask layer 23′ may be formed of a metal material that can form a silicide with the support portion 30′. When the first mask layer 23′ is generated by electroforming, it may be formed of a material such as Ni, Co, Ti, Cr, W, Mo, etc. that has a high adhesion to the support portion 30′. When the second mask layer 21′ is generated by electroforming, it may be formed of a material such as Invar alloy and super Invar alloy that has a small thermal expansion coefficient. Since the first mask layer and the second mask layer have different thermal expansion coefficients, respectively, the thermal expansion coefficient of the mask 20′ can be controlled by adjusting the thickness ratio of the first mask layer and the second mask layer. The thickness ratio of the first mask layer and the second mask layer can be controlled by adjusting the electroforming time.

[0111] In addition, when electroforming is performed, the mask 20′: 20′b can be formed into at least two layers with different compositions by adjusting the current density. For example, the mask 20′b may include a first mask layer 23′ of a pure Ni layer or a Ni-rich alloy layer and a second mask layer 21′ of an Invar alloy layer. First, by applying a first current density, a first mask layer 23′ can be formed on at least a portion of the lower surface BS and the side surface SS of the groove portion TR, and the first mask layer 23′ is pure Ni or an alloy layer containing more than 60wt% of Ni. Then, by applying a second current density different from the first current density, a second mask layer 21′ can be formed on the first mask layer 23′, and the second mask layer 21′ is a FeNi alloy layer (Invar layer) containing 36wt% to 42wt% of Ni. The second current density may be less than the first current density. For example, if the first current density is applied in an electroplating solution environment capable of forming an FeNi alloy, a Ni-rich layer can be electroplated, and as it is converted to the second current density, a layer with an increased Fe ratio can be electroplated.

[0112] However, the thickness of the first mask layer 23' should be less than the thickness of the second mask layer 21'. In order to align the second mask layer 21' having a lower thermal expansion coefficient, the first mask layer 23' is preferably formed to a certain extent to ensure the adhesion with the support portion 30'. In view of this, the thickness of the first mask layer 23' is preferably 2% to 20% of the thickness of the second mask layer 21'.

[0113] The Ni of the first mask 23' is more conducive to the formation of silicide by heat treatment at a relatively low temperature lower than Invar. In addition, the Ni of the first mask 23' has a good enough adhesion to Invar, so it can act as a bonding medium between the support part 30' of the silicon material and the second mask 21'. Moreover, the Ni-rich first mask 23' can be sandwiched and heat treated at a temperature lower than 400°C. Figure 8 ]Advantages of forming the connecting portion 40.

[0114] As another example, the mask 20'b may be configured such that the lower layer and the upper layer include a pure Ni layer or a Ni-rich alloy layer, and an Invar alloy layer is sandwiched in the middle layer. At this time, by applying a first current density during the electroforming process, on at least a portion of the lower surface BS and the side surface SS of the groove portion TR, pure Ni or an alloy layer containing more than 60wt% of Ni can be generated as a lower layer (first mask layer), by applying a second current density different from the first current density, a FeNi alloy layer (Invar layer) containing 36wt% to 42wt% of Ni can be generated as an intermediate layer (second mask layer), and by applying a first current density (or a third current density) different from the second current density, pure Ni or an alloy layer containing more than 60wt% of Ni can be generated as an upper layer (third mask layer). The second current density may be less than the first current density (or the third current density). The thickness of the third mask layer may correspond to the thickness of the first mask layer.

[0115] At this time, the upper layer of pure Ni or an alloy layer containing more than 60 wt% of Ni contains more Ni than the FeNi alloy layer (Invar layer) containing Fe, and therefore has the advantage of reducing the degree of oxidation during the heat treatment H process described later. In addition, in the flattening PS process described later, as the upper layer is removed first, it has the advantage of protecting the middle layer.

[0116] in addition, Figure 6 and Figure 7 Before the mask 20′: 20′a, 20′b is electroformed, an auxiliary connection portion (not shown) may be further formed on at least a portion of the groove portion TR. As an example, when the support portion 30 is a silicon wafer, compared with the state in which the mask 20 made of materials such as Invar alloy and super Invar alloy is directly bonded to the support portion 30, the state in which the connection portion 40 made of materials such as Ni and Cu is bonded as a medium has a higher bonding force. In view of this, the auxiliary connection portion may include at least one of Ni, Cu, Ti, Au, Ag, Al, Sn, In, Bi, Zn, Sb, Ge, and Cd. When the material of the auxiliary connection portion is not easy to be electroformed, it can be formed by sputtering or brazing. When the auxiliary connection portion is generated by electroforming, it can be formed of materials such as Ni, Cu, Ti, Au, Ag, and Al that have high bonding force with the support portion 30′. Alternatively, when the auxiliary connection portion is formed by sputtering or soldering, it can be formed of a material such as Sn, In, Bi, Zn, Sb, Ge, or Cd having a high adhesion to the support portion 30 ′. The auxiliary connection portion can be formed with a relatively thin thickness of 0.01 μm to 0.2 μm.

[0117] Then, refer to Figure 8, the mask 20' and the support portion 30' may be subjected to heat treatment H. Before or after the heat treatment H, a process of removing the insulating portion M1 may be performed. The heat treatment may be performed at a temperature of 100°C to 800°C. As an example, Figure 6 When the mask 20' is directly formed on the support portion 30', the heat treatment may be performed at a temperature of 300°C to 800°C. As another example, Figure 7 When the first mask layer 23' is formed between the second mask layer 21' and the support portion 30', the heat treatment H may be performed at a temperature of about 100°C to 800°C, more preferably, at a low temperature range of about 100°C to 400°C. During the heat treatment H, a preset pressure may be further applied so as to perform the heat treatment with less heat.

[0118] Generally, the thermal expansion coefficient of the Invar alloy sheet formed by electroforming is higher than that of the Invar alloy sheet formed by rolling. Therefore, the thermal expansion coefficient can be reduced by performing heat treatment on the Invar alloy sheet, and some deformation can be formed on the Invar alloy sheet during the heat treatment. If only the mask 20 that exists separately is heat treated, some deformation may occur in the mask pattern P. Therefore, if the heat treatment H is performed in a state where the support portion 30' and the mask 20' are bonded, it is possible to prevent the mask pattern P from being slightly deformed by the heat treatment.

[0119] In addition, in the present invention, the mask 20' is in a form that is adapted to be accommodated in the groove portion TR formed by the depression of the support portion 30'. If the heat treatment H is performed in this state, a special effect is presented that enables the side surface SS and the lower surface BS of the groove portion TR to block the deformation of the mask 20' in the horizontal direction. In addition, in the present invention, by accommodating the mask 20' in the groove portion TR, the contact area between the support portion 30' and the mask 20' can be further ensured, which is conducive to forming the connection portion 40 based on the heat treatment H.

[0120] In addition, the thermal expansion coefficients of the Invar thin plate and the silicon wafer produced by electroforming are almost the same, about 3 to 4 ppi. Therefore, even if the heat treatment H is performed, since the degree of thermal expansion of the mask 20' and the support portion 30' is almost the same, there is no misalignment due to expansion, and slight deformation of the mask pattern P can be prevented.

[0121] In addition, the present invention is characterized in that the mask 20' and the support part 30' are connected by heat treatment H. During the heat treatment H, a connection part 40 can be formed between the mask 20' and the support part 30'. The connection part 40 can be provided as an intermetallic compound synthesized by the components of the mask 20' and the components of the support part 30'. With the synthesis of the Fe and Ni components of the mask 20' and the Si component of the support part 30', the connection part 40 can be provided as a silicide containing Ni and Si or containing Fe, Ni and Si or containing Fe and Ni. Based on the bonding force of the intermetallic compound, the mask 20' and the support part 30' can be connected to each other by sandwiching the connection part 40.

[0122] In addition, according to one embodiment, the heat treatment H process can be performed in multiple steps. As a 2-step heat treatment, Ni2Si is formed in a low temperature region (about 250 to 350°C), and after the mask 20 is bonded to the support portion 30', it is gradually heated to a high temperature region (about 450 to 650°C) and heat treated. Since the Invar mask formed by electroforming has a microcrystalline and / or amorphous structure, if the temperature is rapidly increased during heat treatment, the Invar mask may be detached or separated from the silicon wafer support portion 30' due to volume shrinkage. Therefore, it is preferred to bond the Invar mask to the silicon wafer support portion 30' at a low temperature, and then gradually increase the temperature and perform heat treatment.

[0123] In addition, according to one embodiment, a reducing atmosphere should be maintained during the heat treatment of H. The reducing atmosphere can be an H2, Ar, or N2 atmosphere. Preferably, dry N2 gas is used to prevent oxidation of the Invar alloy mask. In order to prevent oxidation of the Invar alloy mask, the O2 concentration needs to be controlled to be less than 100 ppm. Alternatively, less than 10 -2 The heat treatment H can be performed for 30 minutes to 2 hours.

[0124] By forming a connection portion 40 (adhesive layer) such as Ni silicide or (Ni, Fe)Si silicide on the interface of the mask 20 ′ formed on the silicon wafer support portion 30 ′ by electroforming, the mask 20 ′ and the support portion 30 ′ can be connected by interposing the connection portion 40 .

[0125] In addition, in order to control the reaction of Ni, Fe-Ni and Si during the heat treatment H, a barrier film (not shown) may be formed on the support portion 30' before the mask 20' is electroformed on the support portion 30'. The barrier film can prevent the components of the electroplated film of the mask 20' (as an example, Ni, Fe-Ni) from infiltrating into the silicon support portion 30' uncontrollably. At the same time, in order to enable electroforming on the surface, the barrier film is preferably conductive. In view of this, the barrier film may include materials such as titanium nitride (TiN), titanium or titanium nitride (Ti / TiN), tungsten carbide (WC), titanium tungsten (WTi), and graphene. Thin film formation processes such as barrier film deposition can be used without restriction. The barrier film can form a uniform silicide by controlling the reaction of Fe, Ni and Si, and use appropriate adhesion to adhere the mask 20 and the connecting portion 40. In addition, the barrier film may be composed of a film or a combination of films, which provide a predetermined adhesive force or adhesion force when the mask 20' is electroformed onto the support part 30' so as to prevent the mask 20' from being separated from the support part 30'.

[0126] The thickness of the connection portion 40 (silicide thickness) can be controlled to be 10 to 300 nm by adjusting the temperature and time to connect the support portion 30 ′ and the mask 20 ′.

[0127] In addition, when the above-mentioned auxiliary connection part (not shown) is further interposed, the auxiliary connection part between the mask 20' and the support part 30' during the heat treatment H acts as a medium for connection between the mask 20' and the support part 30' by phase transformation based on melting into a liquid state and then re-solidifying into a solid state during the heat treatment. The auxiliary connection part can be used as an adhesion layer or a glue layer. From another point of view, the interface state of the mask 20', the support part 30' and the auxiliary connection part can be changed and connected by the diffusion of the metal component of the auxiliary connection part to the mask 20' and the support part 30', or conversely, by the diffusion of the components of the mask 20' and the support part 30' to the auxiliary connection part, or by the mutual diffusion of the components.

[0128] In addition, considering the connection strength between the mask 20 ′ and the support portion 30 ′, the heat treatment process may be omitted.

[0129] Then, refer to Fig. 9 , the mask 20' can be flattened PS. The flattening PS means that one side (top) of the mask 20' is mirrored and a portion of the upper part of the mask 20' is removed, thereby reducing the thickness (20'->20). The flattening PS can be performed by lapping, polishing, buffing and other methods.

[0130] After the planarization PS, the mask 20 and the support portion 30' can at least share the same upper surface. The mask 20 performs the planarization PS on the upper surface while being sunken and accommodated in the groove portion TR of the support portion 30', and can share the upper surface with the support portion 30'.

[0131] in addition, Figure 8 Heat treatment H and Fig. 9 The order of planarization PS can be reversed. First, the mask 20 ′ can be planarized PS and thinned ( 20 ′-> 20 ), and then the connection portion 40 can be generated by heat treatment H.

[0132] Then, refer to Fig.10 , the support portion 30′ may be etched EC2. Etching EC2 may be performed on the second surface (lower surface) which is the opposite surface of the first surface (upper surface) of the support portion 30′ connected to the mask 20. Etching EC2 may be performed on the portion of the support portion 30′ corresponding to the unit portion C of the mask 20. The portion corresponding to the dividing portion SR of the mask 20 may not be etched. Optionally, before etching EC2 of the support portion 30′, a thickness thinning process may be performed on the entire or central portion of the lower surface (second surface) of the support portion 30′.

[0133] After the etching EC2, the support part 30 may include an edge part 31, a first grid part 33, and a second grid part 35. In order to clearly present the edge part 31, the first grid part 33, and the second grid part 35 on the support part 30, the etching EC2 preferably adopts a dry etching method with anisotropic etching characteristics. Since the support part 30' is a silicon wafer, the existing semiconductor-related technology and MEMS (Micro Electro Mechanical Systems)-related technology can be used to etch EC2.

[0134] In order to impart etching resistance, an insulating portion M2 may be formed on the lower surface of the support portion 30' except for the portion corresponding to the unit portion C. The insulating portion M2 may be a photoresist formed by a printing method or the like, or may be formed by a method such as thermal oxidation (Thermal Oxidation) or thermal nitridation (Thermal Nitiridation) to form silicon oxide or silicon nitride that acts as a hard mask. In addition, a metal that acts as a mask may also be used in etching. The exposed portion of the lower surface of the support portion 30' that is not covered by the insulating portion M2 may be etched EC2.

[0135] In addition, in the present invention, the connection portion 40 formed between the support portion 30' and the mask 20 can have the effect of acting as a stopper in the etching EC2 process. When the etching EC2 is performed from the second surface of the support portion 30' to the first surface, the etching EC2 is no longer performed when the connection portion 40 is reached. Therefore, it has the effect of preventing the mask 20 or the mask pattern P from being damaged in the etching EC2 process.

[0136] The mask 20 is accommodated in the groove portion TR, so the mask 20 can maintain its shape during the etching EC2 process, and the portion between the adjacent groove portions TR in the support portion 30' will disappear after the etching EC2 process. The empty space can be provided as a mask pattern P of the mask 20. If the side surface SS of the groove portion TR includes an inclined shape or a tapered shape, the side surface of the mask pattern P can also have an inclined shape or a tapered shape corresponding thereto.

[0137] Secondly, refer to Fig.11 After removing the insulating portion M2 and performing subsequent processes such as cleaning, the manufacturing of the connector 10:10-2 between the mask and the support portion can be completed. The support portion 30 includes an edge portion 31, a first grid portion 33, and a second grid portion 35, and the mask 20 is connected to the support portion 30 and a connecting portion 40 is sandwiched in the middle. The unit portion C of the mask 20 does not need to be supported by the support portion 30, and the lower part is an open area, which can be used as an organic source 1600 in the OLED pixel deposition process (refer to Fig.21 )'s moving path is used.

[0138] Figures 12 to 16 FIG. 1 is a schematic diagram of a manufacturing process of a connector 10 of a mask and a support portion according to a second embodiment of the present invention.

[0139] First, if Figure 5 A support portion 30' may be prepared, and a patterned insulating portion M1 may be formed on one surface of the support portion 30'. In addition, by etching the support portion 30' EC1, a plurality of groove portions TR formed by being sunken may be formed on the first surface (or the upper surface).

[0140] Then, refer to Fig.12 , the insulating portion M2 may be removed and cleaned. In addition, a pretreatment process for electroforming may be performed. The support portion 30' is in a state where a plurality of groove portions TR are formed thereon.

[0141] Reference Fig.13 , electroforming can be performed on the support portion 30' to form a mask 20". The mask 20" can be formed to have a thickness that fills the groove portion TR and also covers other parts of the support portion 30' other than the groove portion TR. In other words, the mask 20" can be electroformed so that its upper end is higher than the height of the first surface (or upper surface) of the support portion 30'. The mask 20": 20"a can also be made of Figure 6 The electroforming method described in is formed.

[0142] As another example, refer to Fig.14 , you can also use Figure 7 The method for forming the first mask layer 23' and the second mask layer 21' described in the foregoing makes the mask 20": 20"b be formed into a stacked body having at least two electroplated layers 21", 23".

[0143] Reference Fig.15 , the mask 20 ″ and the support portion 30 ′ may be subjected to a heat treatment H. Before or after the heat treatment H, a process of removing the insulating portion M1 may be performed. Figure 8 The above-mentioned heat treatment H method can also be used. During the heat treatment H, a connection portion 40 can be formed between the mask 20 ″ and the support portion 30 ′. The connection portion 40 can be provided as an intermetallic compound synthesized from components of the mask 20 ′ and components of the support portion 30 ′.

[0144] The mask 20″ is in a state of being adaptively accommodated in the groove portion TR formed by the depression of the support portion 30′. Therefore, during the heat treatment H, the mask 20″ can be prevented from deforming in the horizontal direction, further ensuring the contact area between the support portion 30′ and the mask 20″, which is more conducive to the formation of the connecting portion 40.

[0145] Reference Fig.16 , the mask 20″ can be planarized PS. By mirror-finishing one side (upper side) of the mask 20″ and removing a portion of the upper portion of the mask 20″, the thickness can be reduced (20′->20). The portion of the mask 20″ that is higher than the upper surface of the support portion 30′ can be removed.

[0146] After the planarization PS, the mask 20 and the support portion 30' may at least share the same upper surface. The mask 20 may share the upper surface with the support portion 30' in a state where the mask 20 is sunken and accommodated in the groove portion TR of the support portion 30'.

[0147] in addition, Fig.15 Heat treatment H and Fig.16 The order of planarization PS can be reversed. First, after the mask 20 ′ is planarized PS and thinned ( 20 ′-> 20 ), the connection portion 40 can be generated by heat treatment H.

[0148] As described above, after the mask 20 is formed on the support part 30 by electroforming, the support part 30 is processed to form a frame without applying physical stretching to the mask 20, so there is no risk of misalignment of the mask. Therefore, the mask alignment is accurate and the stability of pixel deposition is improved, while achieving the effect of ultra-high quality pixels above 2000PPI.

[0149] Fig.17 1 is a top view and a side cross-sectional view of EE′ or FF′ of a mask 20 according to another embodiment of the present invention. Fig.18 FIG. 4 is a top view of a support portion 30 according to another embodiment of the present invention.

[0150] Figure 3 The edge of the mask 20 is circular, but the unit portion C including the mask pattern P may be quadrilateral. When the unit portions C are arranged along the first direction and the second direction at the approximate center of the mask 20, the distances from each unit portion C to the edge of the circular mask 20 may be different. From another point of view, the area of ​​contact between each unit portion C and the dummy portion DM may be different. Therefore, the problem of uneven pressure level may occur in each area of ​​the unit portion C and the dummy portion DM of the mask 20.

[0151] In addition, the unit portion C is formed with a mask pattern P to penetrate the mask 20, while the dummy portion DM is not formed with a through pattern, so the dummy portion DM is less deformed after being subjected to pressure, while the unit portion C will also show a greater deformation under the same pressure. In order to achieve ultra-high-quality OLED pixels of 500 to 600 PPI or more, preferably 2000 PPI or more, the connector 10 between the mask and the support portion should be finely formed and its position should not change. Therefore, it is necessary to adjust the pressure level applied to the unit portion C and the dummy portion DM to be uniform. The same applies to the unit area CR of the support portion 30 and the dummy portion unit area DCR.

[0152] Refer again Fig.17 The present invention is characterized in that the dummy part DM includes a plurality of dummy unit parts DC. The dummy unit parts DC may be arranged along a first direction (x-axis direction) of the unit part C and a second direction (y-axis direction) perpendicular to the first direction and at a preset interval. The preset interval between the dummy unit parts DC and the unit part C may correspond to the preset interval between the unit parts C and the unit parts C. A partitioning part SR may also be arranged between the dummy unit parts DC and the unit part C.

[0153] The length of at least one side of the dummy unit portion DC can correspond to the length of one side of the unit portion C. The unit portion C is quadrilateral, and the edge sides C1 and C2 of the unit portion C can be composed of perpendicular lines. If the unit portion C is a square, the lengths of C1 and C2 are the same; if it is a rectangle, the lengths of C1 and C2 are different. The dummy unit portion DC is arranged along the first direction and the second direction in the extending direction of the unit portion C. However, considering the characteristic of being arranged at the edge of the mask 20, it cannot be quadrilateral. The dummy unit portion DC can be a shape with at least some sides having curvature. From another perspective, two to four of the edge sides DCl, DC2, and DC3 of the dummy unit portion DC can be straight lines, and some sides can be curves. Fig.17 Among them, for example, two sides DC1 and DC2 of the dummy unit portion DC located in the upper left side are straight lines, and the DC3 side is composed of two straight lines and one curve. For another example, the dummy unit portion DC located on the rightmost or leftmost side and the dummy unit portion DC located on the uppermost or lowermost side are composed of straight lines with a shape approximately like ′匸′ on three sides, and the right side is composed of a curve.

[0154] In addition, a plurality of dummy patterns DP can be formed in the dummy unit portion DC. As Fig.17 shown, the shape of the dummy pattern DP can be the same as the shape of the mask pattern P. For example, it can have a shape with a slanted side, a taper shape, or a shape where the pattern width gradually widens from top to bottom. A plurality of dummy patterns DP can form a cluster to constitute a dummy unit portion DC. The dummy pattern DP can have a roughly taper shape, and the pattern width can be formed in a size from several μm to more than ten μm, preferably about 5 μm to 10 μm (resolution above 2000 PPI).

[0155] In addition, as long as the dummy pattern DP is within the range of maintaining the pressure uniformity in the entire area of the mask 20, even if it does not penetrate the mask 20 in the thickness direction, it can be formed to a predetermined depth. Moreover, as long as the dummy pattern DP is within the range of maintaining the pressure uniformity in the entire area of the mask 20, it does not have to have the same shape and size as the mask pattern P, and it can also have a shape larger than the mask pattern P and other than the taper shape. However, the more similar the shape is to the mask pattern P, the higher the uniformity of the pressure level will be.

[0156] In addition, the dummy pattern DP can also be formed in the form of cutting a predetermined area on the dummy portion DM of the mask 20. The dummy pattern DP can be not a plurality, and can also be in a continuously connected shape instead of being regularly repeated. For example, the dummy pattern DP can also be provided in the form of only retaining the unit portion C of the mask 20 and cutting off the remaining part.

[0157] Refer to Fig.18, a plurality of dummy unit regions DCR may be formed on the support portion 30. The dummy unit region DCR may be arranged along a first direction (x-axis direction) and a second direction (y-axis direction) perpendicular to the first direction and may be spaced apart from the unit region CR by a preset interval. The preset interval between the dummy unit region DCR and the unit region CR may correspond to the preset interval between the unit region CR and the unit region CR. A first grid portion 33 and a second grid portion 35 may also be arranged between the dummy unit region DCR and the unit region CR. The dummy unit region DCR plays the same role as the above-mentioned dummy unit region DC, and therefore the description of the above-mentioned dummy unit region DC is substituted.

[0158] Fig.19 It is a schematic diagram of a mask planarization process and a dummy trench portion of a grid portion according to an embodiment of the present invention. Fig. 20 1 and 2 are (a) a top view and (b) a side cross-sectional view of a mask pattern and a dummy groove portion of a grid portion according to an embodiment of the present invention.

[0159] like Fig.19 As shown in (a), Fig. 9 It is an ideal state that the upper surface of the mask 20 and the upper surface of the support portion 30 ′ completely maintain the same horizontal plane after the planarization PS process.

[0160] However, if Fig.19 As shown in (b), if polishing, buffing or other flattening PS is performed, the top of the mask 20 and the top of the support portion 30' will not have completely the same level height, and the upper portion of the mask 20 is subjected to concave twist grinding DS1, DS2 (dishing), which can be formed more concavely. At this time, the portion of the mask 20 located in the unit portion C is a portion of the groove portion TR that is narrower than the mask pattern P by a few μm, so the depth of the depression DS1 is relatively shallow. On the contrary, the portion of the mask 20 located in the dividing portion SR is not a portion for the mask pattern P but a portion for supporting the first grid portion 33 and the second grid portion 35, so it has a relatively wide width equivalent to hundreds of μm to several mm. As a result of the flattening PS for the wider width, the depth of the depression DS2 is relatively deep. If the depression DS2 is deep, the thickness of the mask 20 in the dividing portion SR becomes thinner, the rigidity becomes weaker, and it is easy to deform, which may even affect the alignment of the unit portion C.

[0161] Therefore, if Fig.19As shown in (c), a dummy groove portion DTR may be formed in the region on the support portion 30 where the first grid portion 33 and the second grid portion 35 are formed. The width of the dummy groove portion DTR may be formed to be several μm to several hundred μm, and preferably may be formed to be the same size as the groove portion TR, i.e., a narrower width of several μm. Thus, even if the planarization PS is performed, the degree of the depression can be uniformly formed on the unit portion C or the dividing portion SR, so that the dividing portion SR and the first grid portion 33 and the second grid portion 35 can share the same upper surface.

[0162] Reference Fig. 20 , Fig. 20 (b) shows a state in which the partitioning portion SR of the mask 20 is accommodated in the dummy groove portion DTR of the second grid portion 35. The partitioning portion SR is fixed to the dummy groove portion DTR, and the upper portion 35a of the second grid portion 35 can penetrate the partitioning portion SR and be anchored. Thus, the dummy groove portion DTR can provide an effect of improving adhesion with the partitioning portion SR.

[0163] Fig.21 FIG. 1 is a schematic diagram of an OLED pixel deposition apparatus 1000 using a connector 10 of a mask and a support portion according to an embodiment of the present invention.

[0164] Reference Fig.21 The OLED pixel deposition device 1000 includes: a magnetic plate 1300 accommodating a magnet 1310 and provided with a cooling water pipe 1350 ; and a deposition source supplying part 1500 supplying an organic source 1600 from the lower part of the magnetic plate 1300 .

[0165] A target substrate 1900 such as glass for depositing the organic source 1600 may be inserted between the magnetic plate 1300 and the deposition source supply unit 1500. A connector 10 of a mask and a support is arranged closely or very close to the target substrate 1900, which is used to deposit the organic source 1600 according to different pixels. The magnet 1310 generates a magnetic field, and the attractive force of the magnetic field can make the connector 10 of the mask and the support closely attached to the target substrate 1900.

[0166] The deposition source supply unit 1500 can go back and forth between the left and right paths and provide the organic source 1600. The organic source 1600 provided by the deposition source supply unit 1500 passes through the mask pattern P formed on the connector 10 of the mask and the support part and is deposited on one side of the target substrate 1900. The organic source 1600 that passes through the mask pattern P of the connector 10 of the mask and the support part and is deposited can be used as a pixel 1700 of the OLED.

[0167] The side surface of the mask pattern P is formed obliquely (in a tapered shape), so that uneven deposition of the OLED pixel 1700 caused by a shadow effect can be prevented based on the organic source 1600 passing along the oblique direction.

[0168] As described above, after the mask 20 is electroformed on the support part 30' (or the conductive substrate 30'), the present invention processes and connects the mask 20 and the support part 30' without applying physical stretching to the mask 20, and forms the support part 30 as a frame, so there is no risk of misalignment of the mask. Therefore, the mask 20 is accurately aligned and the stability of pixel deposition is improved, while achieving an effect of ultra-high quality pixels of more than 2000PPI.

[0169] As described above, the present invention lists preferred embodiments for illustration and description, but the present invention is not limited to the above embodiments. Those skilled in the art can make various modifications and changes without departing from the spirit of the present invention. The modifications and changes should be deemed to belong to the scope of the present invention and the attached claims.

Claims

1. A connector of a mask and a support portion, the connector being used in a process of forming an OLED pixel on a semiconductor wafer, comprising: a support portion, comprising an edge portion and a grid portion; a mask connected to the support portion and including a plurality of unit portions formed with a mask pattern, At least a portion of the mask is disposed in a groove portion depressed in the support portion.

2. The connector of the mask and the support portion according to claim 1, wherein: The support portion and the mask have a circular shape, The grid portion includes: a plurality of first grid portions extending along a first direction and connected to the edge portion at both ends; and a plurality of second grid portions extending along a second direction different from the first direction and intersecting with the first grid portions and connected to the edge portion at both ends.

3. The connector of the mask and the support portion according to claim 2, wherein: The mask comprises: a dummy portion connected to the edge portion; The plurality of unit portions are arranged at the central portion of the mask instead of being arranged at the dummy portion, and include a plurality of mask patterns; a dividing portion arranged at a central portion of the mask rather than at the dummy portion and arranged between the plurality of unit portions, The partitioning portion is supported on the grid portion.

4. The connection body of the mask and the support portion according to claim 3, wherein: The dummy portion and the edge portion share a same upper surface.

5. The connection body of the mask and the support portion according to claim 3, wherein: A dummy groove portion is formed on the grid portion.

6. The connection body of the mask and the support portion according to claim 5, wherein: A portion of the mask corresponding to the dividing portion is arranged in the dummy groove portion, so that the dividing portion and the grid portion at least share the same upper surface.

7. The connection body of the mask and the support portion according to claim 2, wherein: The support portion is formed of a silicon wafer, the mask is formed on the silicon wafer by electroforming, and a connecting portion containing Ni and Si or a connecting portion containing Fe, Ni and Si is interposed between the support portion and the mask.

8. The connection body of the mask and the support portion according to claim 7, wherein: An auxiliary connecting part is sandwiched between the connecting part and the mask, and the auxiliary connecting part includes at least one of Ni, Cu, Ti, Au, Ag, Al, Sn, In, Bi, Zn, Sb, Ge, and Cd, and the thickness of the auxiliary connecting part is 0.01μm to 0.2μm.

9. The connection body of the mask and the support portion according to claim 7, wherein: The 100-plane or 111-plane crystal direction of the silicon wafer is not parallel to the length direction of the first grid portion or the second grid portion.

10. A method for manufacturing a connector of a mask and a support, wherein the connector is used in a process of forming an OLED pixel on a semiconductor wafer, the method comprising the following steps: (a) preparing a support portion, wherein the support portion includes a first surface and a second surface opposite to the first surface and is a conductive substrate; (b) forming a groove portion by sinking the first surface of the support portion; (c) forming a mask on the first surface of the support portion by electroforming; (d) performing heat treatment on the support portion and the mask; (e) etching the support portion on the second surface of the support portion to form an edge portion and a grid portion, In the step (c), the mask is formed at least in the groove portion.

11. The method for manufacturing a connection body of a mask and a support portion according to claim 10, wherein: The step (b) forms a plurality of groove portions in a patterned form, and after the step (e), a portion between adjacent groove portions is provided as a mask pattern of the mask.

12. The method for manufacturing a connection body of a mask and a support portion according to claim 11, wherein: The step (b) comprises: (b1) forming a first insulating portion on the first surface of the support portion; (b2) The supporting portion exposed between the first insulating portions is etched to form the groove portion.

13. The method for manufacturing a connection body of a mask and a support portion according to claim 12, wherein: In the step (c), the mask is electroformed so that the upper end of the mask is higher than the height of the first surface of the support portion and lower than the height of the upper end of the first insulating portion.

14. The method for manufacturing a connection body of a mask and a support portion according to claim 12, wherein: The method further includes removing the first insulating portion between the step (b) and the step (c). In the step (c), the mask is electroformed so that the upper end of the mask is higher than the height of the first surface of the support portion.

15. The method for manufacturing a connection body of a mask and a support portion according to claim 10, wherein: The step (c) comprises: (c1) applying a first current density and forming a first mask layer containing more than 60 wt % of Ni on at least a portion of a lower surface and a side surface of the groove portion; (c2) applying a second current density different from the first current density, and forming a second mask layer made of a FeNi alloy containing 36 wt % to 42 wt % of Ni on the first mask layer.

16. The method for manufacturing a connection body of a mask and a support portion according to claim 15, wherein: The thickness of the first mask layer is 2% to 20% of the thickness of the second mask layer.

17. The method for manufacturing a connection body of a mask and a support portion according to claim 15, wherein: Further including: (c3) applying a first current density different from the second current density, and forming a third mask layer containing more than 60 wt % of Ni on the second mask layer, The thickness of the third mask layer is 2% to 20% of the thickness of the second mask layer.

18. The method for manufacturing a connection body of a mask and a support portion according to claim 10, wherein: After the heat treatment in step (d), the support portion and the mask are connected by interposing a connecting portion containing Ni and Si or a connecting portion containing Fe, Ni and Si. The heat treatment in step (d) is performed at 100°C to 800°C.

19. The method for manufacturing a connection body of a mask and a support portion according to claim 18, wherein: The connection portion is formed between at least a portion of a lower surface and a side surface of the groove portion and the mask.

20. The method for manufacturing a connection body of a mask and a support portion according to claim 10, wherein: In the step (b), a dummy groove portion is further formed on the support portion corresponding to the area where the grid portion is formed. In the step (c), the mask is formed at least in the groove portion and the dummy groove portion.

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