Techniques for detecting inductor disconnect conditions in voltage regulators

Abstract

Embodiments of the invention relate to techniques for detecting an inductor turn-off condition in a voltage regulator. Some examples relate to a circuit (118) that includes a plurality of input pins (134), a plurality of output pins (129), a pulse width modulation (PWM) controller (120), and an inductor disconnection detection circuit (122). The PWM controller (120) has a plurality of inputs and a plurality of outputs. The plurality of inputs of the PWM controller (120) are coupled to the plurality of input pins (134), and the plurality of outputs of the PWM controller (120) are coupled to the plurality of output pins (129). The inductor disconnection detection circuit (122) has an input coupled to a pin of the plurality of input pins (134) and has an output coupled to the PWM controller (120).

Description

Technical Field

[0001] Embodiments of the present application relate to techniques for detecting an inductor disconnect condition in a voltage regulator. Background Art

[0002] Voltage regulators (e.g., direct current (DC)-DC converters, alternating current (AC)-AC converters, etc.) and analog / digital converters (ADCs) and other components are widely used in modern electronic devices. Generally speaking, computing devices rely on voltage regulators to receive power. Voltage regulators generate a constant output voltage based on an input voltage. Summary of the invention

[0003] Some examples relate to a circuit that includes a plurality of input pins, a plurality of output pins, a pulse width modulation (PWM) controller, and an inductor disconnect detection circuit. The PWM controller has a plurality of inputs and a plurality of outputs. The plurality of inputs of the PWM controller are coupled to the plurality of input pins, and the plurality of outputs of the PWM controller are coupled to the plurality of output pins. The inductor disconnect detection circuit has an input coupled to a pin of the plurality of input pins and has an output coupled to the PWM controller.

[0004] In other examples, the voltage regulator includes a voltage input terminal and a voltage output terminal. The voltage regulator includes a power stage, a transformer, a pulse width modulation (PWM) controller, and an inductor disconnect detection circuit. The power stage has an input terminal and an output terminal, and the input terminal of the power stage is coupled to the voltage input terminal of the voltage regulator. The transformer has a primary winding and a secondary winding. The primary winding has a first terminal and a second terminal, and the secondary winding has a first terminal and a second terminal. The first terminal of the primary winding is coupled to the output terminal of the power stage, and the second terminal of the primary winding is coupled to the voltage output terminal of the voltage regulator. The PWM controller includes an input and an output. The input of the PWM controller is coupled to the transformer, and the output of the PWM controller is coupled to the input terminal of the power stage. The inductor disconnect detection circuit has an input and an output, and the input of the inductor disconnect detection circuit is coupled to the output of the power stage or to the transformer. The output of the inductor disconnect detection circuit is coupled to the PWM controller.

[0005] In addition, another example relates to a method. The method involves regulating an output voltage by a circuit during a direct current (DC)-DC conversion mode by providing an integer number N of pulse width modulation (PWM) pulses during a time period, the N PWM pulses having N respective phase offsets spaced approximately 360 / N degrees from each other during the time period. The method also involves detecting a fault condition by the circuit during a fault detection mode by providing a single PWM pulse to trigger a current signal. The method also involves providing a fault signal by the circuit in response to whether a pulse length or a pulse slope magnitude of a falling edge of the current signal exceeds a pulse length threshold or a pulse slope threshold indicated by the fault condition. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram showing an example of a trans-inductor voltage regulator (TLVR) circuit including a control circuit with an inductor disconnect detection circuit.

[0007] Figure 2 is an example schematic diagram showing a TLVR circuit and showing various pins of a power stage and a control circuit, wherein the power stage of the TLVR circuit includes an ammeter and a transistor.

[0008] Figure 3A is a timing diagram of a TLVR circuit, which illustrates an example of how a pulse width modulation (PWM) signal is used to implement DC-DC conversion and how an inductor disconnect condition is detected and used to trigger the shutdown of the PWM signal.

[0009] Figure 3B is a timing diagram of a TLVR circuit illustrating how the current amplitude of the output current may vary over time during DC-DC conversion to maintain the output voltage of the TLVR circuit at a substantially constant level.

[0010] Figure 4 is an example schematic diagram showing another TLVR circuit, in which the inductor disconnect detection circuit is implemented as a digital application specific integrated circuit (ASIC) including a counter.

[0011] Figure 5 is with Figure 4 A consistent timing diagram of the TLVR circuit.

[0012] Figure 6 is an example schematic diagram showing another TLVR circuit, in which the inductor disconnect detection circuit is implemented as a digital ASIC including a slew rate detector.

[0013] Figure 7 is with Figure 6 A consistent timing diagram of the TLVR circuit.

[0014] Figure 8is a schematic diagram showing another example of a TLVR circuit, in which the inductor disconnect detection circuit is implemented as an analog integrated circuit.

[0015] Fig. 9 is an example schematic diagram showing another TLVR circuit in which the inductor disconnect detection circuit implements executable instructions running on a microcontroller.

[0016] Fig.10 is an example flow chart showing a method for detecting an inductor disconnect condition in a voltage regulator.

[0017] Fig.11 is another example flow chart showing a method for detecting an inductor disconnect condition in a voltage regulator. DETAILED DESCRIPTION

[0018] A voltage regulator is an electrical circuit that receives an input voltage and delivers a substantially constant output voltage in response to the input voltage. A trans-inductor voltage regulator (TLVR) circuit is a type of voltage regulator. The TLVR circuit uses multiple inductors (e.g., transformers) arranged in series to store magnetic energy. The series inductors enable fast transient response for the voltage regulator. However, during operation, changes in the amount of current flowing through the inductor may cause the electromagnetic force (EMF) to change and thus cause vibrations on the inductor. These vibrations, as well as environmental conditions, may cause an electrical disconnection (e.g., "disconnection") between the inductors, which may cause device failure and / or a dangerous condition for the end user. Therefore, various examples of the present specification relate to a voltage regulator control circuit including an inductor disconnection detection circuit. The inductor disconnection detection circuit monitors a signal from the voltage regulator and reports a fault signal when an electrical disconnection occurs. For example, a fault signal may be activated when one of the inductors arranged in series is disconnected from the other inductors in the voltage regulator.

[0019] Although the voltage regulator is described herein in the form of a TLVR circuit, other voltage regulators of the present description may include other types of DC-DC converters or may even include AC-DC converters. For example, some voltage regulators of the present description may continuously step down or "step down" an input voltage to an output voltage (e.g., as described below). However, other voltage regulators of the present description may continuously step up or "step up" an input voltage to an output voltage, or may even vary between stepping up the input voltage to an output voltage and stepping down the input voltage to an output voltage at different times (so-called "buck / boost" converters).

[0020] Figure 1An electronic system 100 is depicted according to some examples. The electronic system 100 includes a voltage regulator 101 disposed between a power source 103 and a load 105. The voltage regulator 101 has a voltage input terminal 102 coupled to an output of the power source 103. The voltage regulator 101 also has a voltage output terminal 104 coupled to an input of the load 105. For example, the power source 103 may be a battery, such as a car battery, and the load 105 may be an integrated circuit, such as an engine control unit, an audio module for a vehicle, a lighting control unit, a data center server or an enterprise Ethernet switch and router, etc.

[0021] The voltage regulator 101 includes N power stages 106 and N transformers 108, where N is any positive integer. Therefore, the power stage 106 includes a first power stage 106a, a second power stage 106b, ..., and an Nth power stage 106c. Similarly, the transformer 108 includes a first transformer 108a, a second transformer 108b, ..., and an Nth transformer 108c. Each of the transformers 108 has a primary winding and a secondary winding, which are wound around the core of the transformer. Therefore, the first transformer 108a has a first primary winding 110a and a first secondary winding 112a; the second transformer 108b has a second primary winding 110b and a second secondary winding 112b, and the Nth transformer 108c has an Nth primary winding 110c and an Nth secondary winding 112c. There is also a compensation inductor 114, an output capacitor 116, and a control circuit 118. The control circuit 118 includes a PWM controller 120 and an inductor disconnect detection circuit 122 operably coupled.

[0022] The power stages 106a-106c have respective inputs 107a-107c coupled to the power supply 103, and have respective control inputs 123a-123c coupled to the control circuit 118. The power stages 106a-106c also have respective outputs 111a-111c, respectively, coupled to first terminals 109a-109c, respectively, of the primary windings 110a-110c. The primary windings 110a-110c respectively have second terminals 113a-113c, respectively, coupled to the voltage output terminal 104 of the voltage regulator. A first terminal 115a of the first secondary winding 112a is coupled to a first terminal of the compensator inductor 114. The compensator inductor 114 has a second terminal connected to the ground 130. A second terminal 117a of the first secondary winding 112a is coupled to a first terminal 115b of the second secondary winding 112b. The second terminal 117b of the second secondary winding 112b is coupled to the first terminal of the next secondary winding. The first terminal 115c of the Nth secondary winding 112c is coupled to the second terminal of the (N-1)th secondary winding, and the second terminal 117c of the Nth secondary winding 112c is connected to the ground 130. The inputs of the PWM controller 120 and / or the inductor disconnection detection circuit 122 may be coupled to the output of one or more of the power stages 106 (see, e.g., line 119a) and / or may be coupled to the primary or secondary winding of one or more of the transformers 108 (see, e.g., lines 119b, 119c). The PWM controller 120 has outputs coupled to the corresponding inputs 107a-107c of the power stages 106a-106c, respectively, via feedback paths 124.

[0023] As understood in some aspects of the present specification, in some cases, due to vibration, environmental conditions, or other conditions, the compensation inductor 114 (and / or other inductors of the transformer 108) may become electrically disconnected (e.g., as shown by the opening 150). Therefore, in some examples, the inductor disconnect detection circuit 122 monitors the output of one or more of the power stages 106 and / or the terminals of one or more of the transformers 108 to detect when an inductor disconnect condition exists. If an inductor disconnect condition exists, the inductor disconnect detection circuit 122 may activate the fault signal 131. In response to the fault signal 131 being activated, the PWM controller 120 may deactivate the PWM signal on the output pin 129, thereby deactivating the power stage 106 until the fault signal 131 is repaired. This deactivation causes the power stage to avoid allowing current to pass from the power supply 103 to the load 105. Depending on the polarity of the various switching elements, the deactivation signal may be a constant low value (e.g., a low voltage) or a constant high value (e.g., a high voltage). Additionally, the fault signal 131 may trigger an audio, visual, or other sensing sequence indicating that a fault condition has been detected. For example, a flashing light, a check engine light, some other dashboard / visual warning, a voice message, an email, a text message, or another warning may be provided to notify a user or person repairing the fault condition. Thus, by detecting a fault condition, the inductor disconnect detection circuit 122 may mitigate the impact of a potentially dangerous condition on an end user of the electronic system 100.

[0024] In some instances, the control circuit 118 is an integrated circuit, and the power stages 106a-106c are separate discrete integrated circuits. In some instances, the transformers 108a-108c may also be discrete components, and 106, 108, 114, and 118 may be arranged on a printed circuit board (PCB) or other package and may be operably coupled via conductive traces on the PCB. The feedback path 124 may be an N-bit bus or N pins, which may include N separate lines / wires extending in parallel with each other to connect the corresponding output pins 129 of the control circuit 118 to the corresponding control pins 123a-123c of the power stages 106a-106c. In other instances, the feedback path 124 may use less than N lines / wires, and the control signals may be transmitted serially on the feedback path 124 (e.g., at different frequencies or in different time windows). In other examples, the entire voltage regulator 101 may be on a single integrated circuit, or may be on separate integrated circuit dies stacked on top of each other and / or adjacent to each other in a packaged integrated circuit (e.g., a so-called three-dimensional integrated circuit package). In still other cases, Figure 1The illustrated components of may be otherwise partitioned among multiple integrated circuits and / or discrete devices, but the illustrated implementation provides a good tradeoff of cost, manufacturing reliability, and compatibility with real-world systems. Further, while a "pin" may be interpreted as an external node of an integrated circuit, in other examples, the connection points illustrated and described herein as "pins" may also be internal nodes of a packaged integrated circuit and / or die.

[0025] Figure 2 Another example of a voltage regulator 101 according to some aspects of the present specification is described. Figure 1 The same reference numerals as in Figure 2 denoted in the figure as identical or similar (functionally and / or structurally) features, and this also applies to the subsequent figures. Figure 2 Contains Figure 1 The power stages 106a - 106c , transformers 108a - 108c , and control circuit 118 are consistent. Figure 2 Further details of some components used in the power stage are also shown, but these details are not intended to limit Figure 1 range.

[0026] exist Figure 2 In an example of , the control circuit 118 includes a plurality of input pins 134 coupled to the input of the inductor disconnect detection circuit 122. Each of these input pins may be referred to as a current sense pin (CSP). These CSP pins (and / or another pin 135, which may be coupled to the voltage output terminal 104) may also be coupled to the input of the PWM controller 120. The control circuit 118 also includes a plurality of output pins 129 coupled to the output of the PWM controller 120. The inductor disconnect detection circuit 122 also has an output coupled to the input of the PWM controller 120 (see line 136), and a fault signal 131 may be sent on the output. The inductor disconnect detection circuit 122 may optionally provide the fault signal 131 on a pin 138 of the control circuit. The terms "input" and "output" for pins may also include bidirectional pins, so in some examples, an input pin may also serve as an output pin (and vice versa).

[0027] Figure 2It is also described that the power stages 106 (e.g., 106a-106c) may each include a first transistor 126 (e.g., 126a-126c) and a second transistor 128 (e.g., 128a-128c), an inverter 140 (e.g., 140a-140c), and an ammeter 142 (e.g., 142a-142c). For example, the first power stage 106a includes a first transistor 126a and a second transistor 128a, a first inverter 140a, and a first ammeter 142a; the second power stage 106b includes a first transistor 126b and a second transistor 128b, a second inverter 140b, and a second ammeter 142b; and the Nth power stage 106c includes a first transistor 126c and a second transistor 128c, an inverter 140c, and an Nth ammeter 142c. The first transistor and the second transistor each include a first terminal (e.g., source / drain), a second terminal (e.g., drain / source), and a control terminal (e.g., gate). Each inverter 140 has an input coupled to the control terminal of each power stage and coupled to the gate of the first transistor 126. The output of each inverter 140 is coupled to the gate of the second transistor 128 so that the first transistor 126 and the second transistor 128 operate in a complementary manner. The input terminal of each ammeter 142 is coupled to the output terminal of the first transistor 126 and the second transistor 128, and the output terminal of each ammeter 142 is coupled to the input of the inductor disconnect detection circuit 122.

[0028] The power stages 106a-106c allow current to pass from the power source 103 to the load 105 based on the PWM signals (PWM1, PWM2, ..., PWMN) from the PWM controller 120. The power stages 106a-106c are configured to switch at different times so that at any point in time, current flows from the power source 103 to the load 105 through a single power stage 106. Other power stages that are not active will allow current to flow from the ground 130 to the load 105. Figure 3A-3B illustrate Figure 1 or Figure 2 1. During operation, the voltage regulator 101 may change between an inductor disconnect detection mode (see times 302, 306), a DC-DC conversion mode (see time 304), and a shutdown mode (see time 308). Figure 3A-3B In the example of , the voltage regulator has N=8 power stages and N=8 transformers, so that eight PWM control signals PWM1, PWM2, ..., PWM8 drive eight phase currents (or voltages corresponding to the phase currents) 132a, 132b, ..., 132c on eight pins CSP1, CSP2, ..., CSPN, respectively. The inductor disconnection detection mode may also be referred to as a fault detection mode.

[0029] In brief, during the inductor disconnect detection mode at time 302, only a single PWM pulse 312 is provided on a single PWM output pin (e.g., PWM1). The PWM pulse 312 couples the first terminal of the first transistor (e.g., 126a) to Vin, thereby triggering a current pulse 314 on the corresponding current sense pin (e.g., CSP1). The current pulse 314 decreases after the PWM pulse 312 according to the following equation:

[0030]

[0031] Where i is the current measured by CSP1, t is the time, N is the number of phases, L C is the inductance of the compensator inductor 114, v out is the output voltage to the load 105, and L M is the inductance of the primary winding 110a.

[0032] In some cases, this inductor disconnect detection mode at time 302 may occur during a startup sequence of the control circuit 118. The inductor disconnect detection circuit 122 determines whether the measured pulse length (T1) of the falling edge of the current pulse 314 exceeds the pulse length threshold (Tth), or alternatively determines whether the measured pulse slope (m1) has a magnitude less than the pulse slope threshold (mth). The inductor disconnect detection mode at time 302 occurs when all other control signals (PWM2, PWM3, ..., PWM8) are off, which also means that there is very little current on the seven other pins (CSP2, CSP3, ..., CSPN). Therefore, there is an advantage because noise is reduced while measuring the pulse length. The pulse length threshold (Tth) and / or the pulse slope threshold (mth) are set so that if the compensation inductor 114 is "off" or disconnected, the measured pulse length exceeds the pulse length threshold (and / or the pulse slope has a slope magnitude less than the pulse slope threshold). In contrast, if the compensation inductor 114 is properly connected, the pulse length is less than the pulse length threshold (and / or the pulse slope has a slope magnitude greater than the pulse slope threshold). For example, at time 302, the current pulse 314 has a measured pulse length T1, which is measured from the peak of the current pulse 314 to the time when the current pulse 314 returns to its initial current value. Here, T1 is less than the pulse length threshold Tth, so the inductor disconnect detection circuit 122 does not activate the fault signal during time 302. Therefore, when there is no fault condition, the voltage regulator continues the DC-DC conversion mode.

[0033] In the DC-DC conversion mode at time 304, the PWM controller activates N=8 PWM pulses (PWM1-PWM8) during a certain time period (e.g., time period 316a). The N PWM pulses have N respective phase offsets that are 360 / N degrees apart from each other in each of the N time periods. During time 304 of the DC-DC conversion mode, the voltage regulator monitors the output voltage Vout. A zoomed-in window showing voltage regulation can be seen during the blocking period 310. Figure 3B At time 318 in FIG. 3 , the load circuit increases its power demand (e.g., switches on or “wakes up” from a low power / sleep state), causing Vout to decrease or “dip” for a brief period of time below the lower voltage threshold 322. In response to this decrease in Vout, the PWM controller may change the PWM control signal provided to the power stage to increase the magnitude of the phase current driven into the primary winding (see 324). Due to the mutual inductive coupling in the transformer, this increase in the phase current of the primary winding also increases the output current from the secondary winding of the transformer, thereby increasing the output voltage Vout at the voltage output terminal 104 and restoring Vout to its initial voltage level (see 326). The mutual inductive coupling between the transformers allows for a fast transient response 320, so that most of the voltage is restored in a small amount of time. Although not shown, if Vout exceeds the upper voltage threshold, the PWM controller may also “tune” the PWM control signal to reduce the phase current and correspondingly reduce the output voltage Vout. Thus, the PWM controller 120 continuously monitors the output voltage Vout and provides a PWM control signal to maintain a substantially constant output voltage even when the power demand of the load circuit varies and Vin varies. Alternatively, rather than being set to a constant output voltage, Vout may optionally track a target voltage (Vtarget), where Vtarget may vary over time based on a predetermined function and / or a time-varying control function.

[0034] At time 306, after the DC-DC conversion mode at time 304 and / or when the control circuit is started again, the inductor disconnect detection mode at time 306 is implemented again. In this time 306, the PWM pulse 312 is also provided only on a single PWM output pin (e.g., PWM1), and the PWM pulse 328 triggers the current pulse 316 (e.g., 316a-316c). Compared to time 302, during time 306, the compensation inductor is now "disconnected", which causes the pulse length (T2) on the falling edge of the current pulse 316 to exceed the pulse length threshold (Tth) according to the following equation:

[0035]

[0036] T1=T2+T y

[0037]

[0038] T th =(T1+t2) / 2

[0039] Alternatively, the pulse slope magnitude (m2) shown by 319 on the falling edge of the current pulse 316 is less than the pulse slope threshold (mth). Therefore, the inductor disconnect detection circuit 122 activates the fault signal 131 and enters the shutdown mode at time 308. During the shutdown mode, the PWM controller, which learns of the fault condition from the inductor disconnect detection circuit, continuously deactivates the PWM signal in response to the activation of the fault signal. Therefore, the PWM signal is deactivated until the fault is repaired or otherwise reset. Therefore, by activating the fault condition, the inductor disconnect detection circuit 122 can mitigate the impact of a potentially dangerous condition.

[0040] Figure 4 An example is shown in which the inductor disconnect detection circuit 122 is embodied as a digital ASIC. In this example, the inductor disconnect detection circuit 122 includes a trigger circuit 410, a counter 426, and a comparison circuit 418. The trigger circuit 410 may include a switch 420, a charge storage capacitor 422, and an operational amplifier 424. The comparison circuit 418 may include a decoder 428 and a latch 430. The counter 426 has an input coupled to the output of the trigger circuit 410, which is coupled to the output of the ammeter 142a. The comparison circuit 418 has an input coupled to the output of the counter 426. The counter 426 counts the number of clock cycles it takes for the current signal from the ammeter 142a (which may be represented as a voltage on CSP1) to decrease from a peak current value to a threshold current value. The ammeter 142a may provide the amplitude of the current. The comparison circuit 418 compares the number of clock cycles to a predetermined count threshold and triggers the fault signal 131 in response to the comparison.

[0041] The switch 420 has a first terminal, a second terminal, and a control terminal. The first terminal is connected to CSP1, and the second terminal is connected to the first terminal of the operational amplifier 424. The control signal of the switch 420 is coupled to PWM1. The charge storage capacitor 422 has a first terminal connected to the first terminal of the operational amplifier 424, and has a second terminal connected to ground. The output of the operational amplifier 424 is connected to the enable terminal or enable input of the counter 426. The counter 426 has a first terminal or clock input connected to the clock, and a second / reset terminal connected to PWM 1. The output terminal of the counter 426 is connected to the input terminal of the decoder 428. The decoder 428 also has an output node, so that at least one of the output nodes is connected to the first terminal of the latch 430. The latch 430 has a second terminal connected to PWM1, and the output of the latch 430 provides the fault signal 131.

[0042] During operation, switch 420 intermittently connects CSP1 to charge storage capacitor 422 to generate a voltage indicative of the current on CSP1. Therefore, when switch 420 is subsequently disconnected, operational amplifier 424 compares the voltage stored on charge storage capacitor 422 with the current voltage on CSP1. The voltage stored on charge storage capacitor 422 can be understood as a reference signal. When the current voltage on CSP1 is greater than the voltage stored on charge storage capacitor 422, operational amplifier 424 forces the enable terminal of counter 426 to be low, so that counter 426 is enabled. Therefore, switch 420, charge storage capacitor 422 and operational amplifier 424 are used to enable or disable counter 426. Whenever a clock pulse is received from CLK, counter 426 operates by incrementing the stored binary value. Counter 426 further has a reset pin connected to PWM1. Therefore, counter 426 is configured to measure the time between the falling edge of PWM 1 and the crossing between the current value of CSP1 and the previous value of CSP1, which is stored in charge storage capacitor 422. Decoder 428 performs a certain logic operation of "AND" among the inputs received from counter 426. This allows the decoder to indicate whether the measured count value is greater than a predetermined pulse length threshold. Latch 430 stores the result and outputs a fault signal 131 to indicate whether the measured count value is greater than the predetermined pulse length threshold. Latch 430 can be reset during each cycle by connecting the reset pin to PWM 1.

[0043] Figure 5 Contains a counter Figure 41. This timing diagram shows signals for PWM1, CSP1, CK, internal counts, and a fault signal. This timing diagram indicates times 502, 504, 506, 508, 510, 512, and 514. At 502, a rising edge of PWM1 occurs. At 504, a falling edge of a PWM pulse to PWM1 occurs. At 508, a time threshold is shown. At 510, a second rising edge of PWM1 occurs. At 512, a second falling edge to PWM1 occurs. At 514, the fault signal changes value.

[0044] When PWM1 is turned on between time 502 and 504, the CSP1 waveform shows an increasing current because the first transistor 126a is "on" during this time. At 502, the switch 420 is activated to be in a closed position for a short period of time, so that the value of CSP 1 near time 502 is stored on the charge storage capacitor 422 and provided to the positive pin of the operational amplifier 424. After 504, the CSP 1 waveform shows a decreasing current because the primary winding 110a is losing energy. Between time 502 and 504, the negative pin of the operational amplifier 424 has a rising value due to the rising CSP 1 value. The output of the operational amplifier 424 is negative from time 502 to 506 because CSP 1 between time 502 and 506 is large compared to the value of CSP 1 near time 502, so the counter is enabled. Because the counter 426 is reset when PWM1 is high, the counter begins counting CLK pulses at time 504, which is the falling edge of the pulse. Therefore, the counter 426 is allowed to count the number of pulses of PWM1 returning to its starting value at 502 to measure the time T1 as T1'. The decoder 428 provides a logical "AND" among the outputs of the counter 426 so that a specific time can be detected. This specific time may correspond to Tth. In this example, T1' is less than the threshold time Tth shown at 508, so no fault is indicated.

[0045] The second pulse occurs between 510 and 512, causing the CSP1 current to increase during this time. After 512, the CSP1 current decreases. The operational amplifier 424 compares the value of CSP1 near time 510 with the value of CSP1 between 510 and 512, and the operational amplifier 424 outputs a low value to the counter 426. This low value enables the counter 426. Once PWM1 goes low at time 512, the counter 426 starts counting because PWM1 is connected to the reset pin of the counter 426. Therefore, the counter 426 is allowed to count the CLK pulses and store the time T2 as T2'. The decoder 428 provides a threshold logic expression to the output of the counter 426 to detect whether the time T2' is equal to Tth. Once the time T2' is equal to (and / or greater than) Tth, the latch 430 receives a high signal of its set pin and outputs a fault at 514.

[0046] Figure 6 An example of an inductor disconnect detection circuit 122 implemented by slope detection is shown. In this example, there is a slew rate circuit 601 that includes a sampling circuit 602 and a comparator 606. The sampling circuit 602 has an input and an output, and the slope detection circuit 604 has an input and an output. The comparator has a positive input, a negative input, and an output. The sampling circuit 602, the slope detection circuit 604, and the comparator 606 can be implemented in hardware (e.g., an ASIC), a field programmable gate array (FPGA), or with discrete components.

[0047] The input of sampling circuit 602 is coupled to CSP1, and the output of sampling circuit 602 is coupled to the input of slope detection circuit 604. The output of slope detection circuit 604 is coupled to the positive input of comparator 606. The negative input of the comparator is connected to a reference indicating a slope threshold. The output of comparator 606 is connected to fault signal 131.

[0048] The sampling circuit 602 may sample a pair of values ​​from CSP1 at known time intervals and provide the sampled values ​​to the slope detection circuit 604. The slope detection circuit 604 may perform a calculation with the pair of values ​​to determine the slope between them. The slope detection circuit 604 may provide a voltage representing the slope magnitude to the comparator 606. The comparator 606 compares the voltage representing the slope magnitude to a slope threshold and outputs a fault when the voltage representing the slope magnitude is less than the slope threshold.

[0049] Figure 7 exhibit Figure 6 How the slope detection in can be operated. Figure 7 Waveforms showing PWM 1, CSP 1, and fault. Figure 7 There are annotations for times 702 , 704 , 708 , 710 , and 716 . Figure 7 Also shown are the measured samples 706, 712, 714 and the threshold slope mth.

[0050] At time 702, a rising edge of a first pulse to PWM 1 occurs. At time 704, a falling edge of a first pulse to PWM 1 occurs. At time 708, a rising edge of a second pulse to PWM 1 occurs. At time 710, a falling edge of a second pulse to PWM 1 occurs. At time 716, the value of the fault signal changes from 0 to 1, indicating a fault.

[0051] The measured samples 705, 706, 712, and 714 are sampled by the sampling circuit 602 and used to calculate the slope magnitude of CSP 1. The slope magnitude calculation may be accomplished by the slope detection circuit 604 receiving each pair of samples (e.g., 705 and 706, or 712 and 714), subtracting one sample of the pair from the other sample of the pair to define a difference, taking the absolute value of the difference, and then dividing the difference by the known time between the samples. The comparator 606 compares this slope magnitude with a slope threshold mth. If the calculated slope magnitude is less than the slope threshold mth, the comparator 606 outputs a fault. For example, a fault is detected at 716 because the slope magnitude of CSP 1 calculated from the measured samples 712 and 714 is less than mth.

[0052] Figure 8 An example is shown in which the inductor disconnect detection circuit 122 has an analog implementation. The circuit 122 has a first switch 806, a second switch 808, a capacitor 810, and a comparator 804. The first switch 806 may have a first terminal connected to CSP1, a second terminal connected to the first terminal of the second switch 808, and a control terminal. The second terminal of the first switch 806 is also coupled to the first terminal of the capacitor 810 and the first terminal of the comparator 804. The second switch 808 may have a second terminal connected to ground. The capacitor 810 may have a second terminal connected to ground. The comparator 804 may have a second terminal connected to a threshold voltage (Vth) and an output connected to a fault terminal.

[0053] During operation, the first switch 806 is closed to connect CSP1 to the capacitor 810. After the first switch 806 is closed, the capacitor 810 begins to accumulate charge. After a certain period of time, the first switch 806 is opened and the second switch 808 is closed to discharge the capacitor 810. If the capacitor 810 accumulates a voltage greater than Vth during the time that the first switch 806 is closed, the comparator may change the output value from low to high or from high to low, indicating a fault. The control of the first switch 806 and the second switch 808 is configured to measure a combination of voltage from the CSP1 terminal and time.

[0054] Fig. 9 Another example of an inductor disconnect detection circuit 122 is shown. In this example, the inductor disconnect detection circuit may have a microcontroller 900. The microcontroller may have an analog / digital converter (ADC) 902, a processor 904, a memory 906, a PWM driver 908, and a clock 910 (CLK). The microcontroller may have a first terminal connected to CSP 1, a second terminal connected to the fault, and a plurality of PWM output terminals for controlling transistors 126a-126c and transistors 128a-128c. The microcontroller may include processor executable instructions 912, such as software, firmware, or hard-coded instructions, which measure a value from CSP 1, count the number of clock cycles, and report a fault depending on a condition involving counting the number of clock cycles and / or measuring the slope magnitude of the current signal. Alternatively, the instructions 912 may measure the slope magnitude of CSP1 and compare it to a slope threshold. Furthermore, because the microcontroller controls the PWM signals: PWM 1, PWM 2, PWM N, the microcontroller can change the pulse width or frequency of the PWM signals depending on whether a fault is detected.

[0055] Fig.10 A flow chart showing a method implemented by a microcontroller. At step 1002, the microcontroller measures CSP1 and stores the value in a first variable. At step 1004, the microcontroller turns PWM1 high. At step 1006, the microcontroller turns PWM1 low. At step 1008, the microcontroller counts the time that CSP1 decreases to the value stored in the first variable, and at step 1010, the microcontroller may trigger a fault based on a calculation involving the time.

[0056] Fig.11 A flow chart of a method implemented by a control circuit is shown. In step 1102, the control circuit regulates the output voltage by providing an integer number N of pulse width modulation (PWM) pulses during a time period, the N PWM pulses having N respective phase offsets spaced approximately 360 / N degrees from each other during the time period. In step 1104, the control circuit detects a fault condition during a fault detection mode by providing a single PWM pulse to trigger a current signal. In step 1106, the control circuit provides a fault signal in response to whether a pulse length of a pulse slope magnitude of a falling edge of the current signal exceeds a pulse length threshold or a pulse slope threshold.

[0057] The method is described and described as a series of actions or events above, but the described order of such actions or events is not restrictive. For example, in addition to the actions or events described and / or described herein, some actions may occur in different orders and / or simultaneously with other actions or events. In addition, some described actions or events are optional, to implement one or more aspects or embodiments of this specification. In addition, one or more of the actions or events described herein may be performed in one or more separate actions and / or stages. In some embodiments, the method described above may be implemented in a computer-readable medium using instructions stored in a memory.

[0058] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0059] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or through a combination thereof.

[0060] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to interconnects or their ends between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components.

[0061] Circuits or devices described herein as including certain components may alternatively be adapted to be coupled to those components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0062] Although the use of specific transistors is illustrated and / or described herein, other transistors (or equivalent switching devices) may be used instead with little or no change to the remaining circuitry. For example, metal oxide silicon FETs ("MOSFETs") (e.g., n-channel MOSFETs (nMOSFETs), or p-channel MOSFETs (pMOSFETs)), bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0063] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0064] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / -10% of the value, or if the value is zero, a reasonable range of values ​​around zero. Modifications may be made in the described examples, and other implementations are possible, within the scope of the claims.

Claims

1. A circuit comprising: Multiple input pins; Multiple output pins; a pulse width modulation (PWM) controller having a plurality of inputs and a plurality of outputs, the plurality of inputs of the PWM controller being coupled to the plurality of input pins and the plurality of outputs being coupled to the plurality of output pins; as well as An inductor disconnect detection circuit has an input coupled to a pin of the plurality of input pins and has an output coupled to the PWM controller.

2. The circuit of claim 1 , wherein the plurality of PWM signals on the plurality of output pins are deactivated in response to a pulse length or a pulse slope magnitude of a falling edge of the waveform on the pin exceeding a pulse length threshold or a pulse slope threshold.

3. The circuit of claim 2 , wherein the PWM controller is configured to operate in a DC-DC conversion mode and an inductor disconnect detection mode, wherein each of the plurality of PWM signals is switched during the DC-DC conversion mode, and less than all of the plurality of PWM signals are switched during the inductor disconnect detection mode.

4. The circuit of claim 1 , wherein the inductor disconnect detection circuit is configured to selectively activate a fault signal in response to a pulse length or a pulse slope magnitude of a falling edge of the waveform on the pin exceeding a pulse length threshold or a pulse slope threshold. 5 . The circuit of claim 4 , wherein the PWM controller is configured to deactivate the PWM signal on the output pin in response to activation of the fault signal.

6. The circuit of claim 1 , wherein the inductor disconnect detection circuit comprises: a trigger circuit having an input and an output; The input of the trigger circuit is coupled to the pin; a counter having a clock input, an enable input, and an output; the enable input coupled to the output of the trigger circuit; as well as A decoder has an input and an output coupled, the input of the decoder coupled to the output of the counter, and the output of the decoder coupled to the PWM controller.

7. The circuit according to claim 6, wherein the input of the trigger circuit is a first input, and the trigger circuit is configured to receive a current amplitude on the first input; wherein the counter is configured to increment a count value at the output of the counter when the current amplitude is greater than a reference signal; and The decoder is configured to output a fault signal when the count value exceeds a pulse length threshold.

8. The circuit of claim 1 , wherein the inductor disconnect detection circuit comprises: a slew rate circuit having an input and an output, the input of the slew rate circuit being coupled to the pin; as well as A comparison circuit has an input and an output, the input of the comparison circuit being coupled to the output of the slew rate circuit and the output of the comparison circuit being coupled to the PWM controller.

9. The circuit of claim 1 , wherein the PWM controller is configured to operate in a DC-DC conversion mode and an inductor disconnect detection mode, wherein during the DC-DC conversion mode, the PWM controller provides an integer number N of PWM pulses on the plurality of output pins during N time periods, respectively, the N PWM pulses having a phase offset of approximately 360 / N degrees from each other in each time period; and During the inductor disconnection detection mode, PWM pulses are provided only on a single PWM output pin, and the PWM pulses trigger a current signal, and a fault signal is triggered based on whether the pulse length or pulse slope magnitude of a falling edge of the current signal exceeds a pulse length threshold or a pulse slope threshold.

10. A voltage regulator comprising a voltage input terminal and a voltage output terminal, the voltage regulator comprising: a power stage having an input terminal and an output terminal, the input terminal of the power stage being coupled to the voltage input terminal of the voltage regulator; a transformer comprising a primary winding and a secondary winding, the primary winding having a first terminal and a second terminal, and the secondary winding having a first terminal and a second terminal, the first terminal of the primary winding being coupled to the output terminal of the power stage, the second terminal of the primary winding being coupled to the voltage output terminal of the voltage regulator; a pulse width modulation (PWM) controller comprising an input and an output, the input of the PWM controller being coupled to the transformer and the output of the PWM controller being coupled to the input terminal of the power stage; as well as An inductor disconnect detection circuit has an input and an output, wherein the input of the inductor disconnect detection circuit is coupled to the output of the power stage or to the transformer, and the output of the inductor disconnect detection circuit is coupled to the PWM controller.

11. The voltage regulator of claim 10, wherein the power stage further comprises: An ammeter includes an input terminal and an output terminal, wherein the input terminal of the ammeter is coupled to the output terminal of the power stage, and the output terminal of the ammeter is coupled to the input of the inductor disconnect detection circuit.

12. The voltage regulator of claim 11 , wherein the inductor disconnect detection circuit comprises: a counter having an input coupled to the output of the ammeter, the counter configured to count a number of clock cycles in which the current signal from the ammeter decreases from a peak current value to a threshold current value; as well as A comparison circuit is coupled to the output of the counter, the comparison circuit being configured to compare the number of clock cycles to a predetermined count threshold and to trigger a fault signal in response to the comparison.

13. The voltage regulator of claim 11 , wherein the inductor disconnect detection circuit comprises: a slew rate circuit having an input coupled to the output of the current meter, the slew rate circuit configured to determine a magnitude of a slope of a current signal from the current meter between a peak current value and a threshold current value; as well as A comparison circuit is configured to compare the slope magnitude to a slope threshold and trigger a fault signal in response to the comparison.

14. The voltage regulator of claim 10, wherein the inductor disconnect detection circuit comprises: a first switch having a first terminal, a second terminal and a control terminal, the first terminal of the first switch being coupled to the output of the power stage, a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the second terminal of the first switch, and A comparator includes a first terminal, a second terminal, and an output terminal, wherein the first terminal of the comparator is coupled to the second terminal of the capacitor, and the output terminal of the comparator is coupled to the PWM controller.

15. The voltage regulator of claim 10, wherein the power stage is a first power stage, the primary winding is a first primary winding, the secondary winding is a first secondary winding, and the transformer is a first transformer, the voltage regulator further comprising: a second power stage comprising an input terminal and an output terminal, the input terminal of the second power stage being coupled to the input terminal of the first power stage; as well as A second transformer comprising a second primary winding and a second secondary winding, the second primary winding having a first terminal and a second terminal, and the second secondary winding having a first terminal and a second terminal, the first terminal of the second primary winding being coupled to the output terminal of the second power stage, and the second terminal of the second primary winding being coupled to the second terminal of the first primary winding.

16. The voltage regulator of claim 15, wherein the second terminal of the first secondary winding is coupled to the first terminal of the second secondary winding, and the voltage regulator further comprises: A compensator inductor has a first terminal coupled to the first terminal of the first secondary winding.

17. A method comprising: regulating the output voltage by the circuit during a direct current (DC)-to-DC conversion mode by providing an integer number N of pulse width modulation (PWM) pulses during a time period, the N PWM pulses having N respective phase offsets spaced approximately 360 / N degrees from one another during the time period; detecting a fault condition by the circuit during a fault detection mode by providing a single PWM pulse to trigger a current signal; as well as A fault signal is provided by the circuit in response to whether a pulse length or a pulse slope magnitude of a falling edge of the current signal exceeds a pulse length threshold or a pulse slope threshold indicated by the fault condition.

18. The method of claim 17, wherein the N PWM pulses are received at N pins of an integrated circuit, respectively, and wherein the single PWM pulse is provided on only one of the N pins of the integrated circuit.

19. The method of claim 17, wherein detecting the fault condition comprises: counting the number of clock cycles in which the falling edge of the current signal decreases from a peak current value to a threshold current value; as well as The fault signal is activated by comparing the number of clock cycles to a predetermined count threshold.

20. The method of claim 17, wherein detecting the fault condition comprises: determining a magnitude of a slope of the falling edge of the current signal; as well as The fault signal is activated by comparing the slope magnitude to a slope threshold.

Images