Pixel structure

Abstract

A pixel structure comprises a substrate, a shading layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conducting layer, a third insulating layer and a second conducting layer. A crosstalk problem between different signals can be reduced by dividing the light shielding layer into a plurality of portions separated from each other.

Description

Technical Field

[0001] The invention relates to a pixel structure. Background Art

[0002] Contrast ratio (CR) refers to the ratio of the brightest image (e.g., brightness of L255) to the darkest image (e.g., brightness of L0). A high contrast ratio means that the image can be more vivid, the black is deeper, and the white is brighter, thereby improving the viewing effect and user experience. This is especially important when displaying a detailed image or using it in a strong light environment.

[0003] In order to improve the contrast value of the LCD panel, a light shielding layer is usually set in the pixel structure. However, the light shielding layer is prone to cause crosstalk between different signals, which not only affects the picture quality, but also may cause color distortion or other display anomalies. Summary of the invention

[0004] The object of the present invention is to provide a pixel structure which can reduce the crosstalk problem between different signals.

[0005] At least one embodiment of the present invention provides a pixel structure, which includes a substrate, a light shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer and a second conductive layer. The light shielding layer is located on the substrate and includes a semiconductor layer light shielding portion, a first data line light shielding portion, a second data line light shielding portion and a third data line light shielding portion separated from each other. The first insulating layer is located on the light shielding layer. The semiconductor layer is located on the first insulating layer and at least partially overlaps the semiconductor layer light shielding portion. The second insulating layer is located on the semiconductor layer. The first conductive layer is located on the second insulating layer and includes a scan line extending along a first direction. The scan line partially overlaps the semiconductor layer. The third insulating layer is located on the first conductive layer. The second conductive layer is located on the third insulating layer and includes a first source / drain, a second source / drain and a data line. The first source / drain and the second source / drain are connected to the semiconductor layer. The data line is connected to the first source / drain and includes a first extension portion, a second extension portion and a bending portion. The first extension portion extends along the second direction and overlaps the first data line light shielding portion. The second extension portion extends along the third direction and overlaps the second data line light shielding portion. The bending portion connects the first extension portion and the second extension portion and overlaps the third data line light shielding portion.

[0006] At least one embodiment of the present invention provides a pixel structure, including a substrate, a light shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer and a second conductive layer. The light shielding layer is located on the substrate and includes a semiconductor layer light shielding portion, a first conductive hole light shielding portion and a second conductive hole light shielding portion separated from each other. The first insulating layer is located on the light shielding layer. The semiconductor layer is located on the first insulating layer and at least partially overlaps the semiconductor layer light shielding portion. The second insulating layer is located on the semiconductor layer. The first conductive layer is located on the second insulating layer and includes a scan line extending along a first direction. The scan line partially overlaps the semiconductor layer. The third insulating layer is located on the first conductive layer. The second conductive layer is located on the third insulating layer and includes a first source / drain, a second source / drain and a data line. The first source / drain and the second source / drain are connected to the semiconductor layer. The contact surface between the first source / drain and the semiconductor layer overlaps the first conductive hole light shielding portion. The contact surface between the second source / drain and the semiconductor layer overlaps the second conductive hole light shielding portion. The data line connects the first source / drain.

[0007] Based on the above, the crosstalk problem between different signals can be reduced by dividing the light shielding layer into a plurality of parts separated from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a schematic top view of a pixel structure according to the first embodiment of the present invention.

[0009] Figure 1B It is along Figure 1A A schematic cross-sectional view of line AA' and line BB'.

[0010] Figure 2 is a schematic top view of a pixel structure according to a second embodiment of the present invention.

[0011] Figure 3 is a schematic top view of a pixel structure according to a third embodiment of the present invention.

[0012] Figure 4 is a schematic top view of a pixel structure according to a fourth embodiment of the present invention.

[0013] Figure 5A as well as Figure 5B A schematic top view of a method for testing the crosstalk rate of a liquid crystal display panel according to some embodiments of the present invention is shown.

[0014] The reference numerals are as follows:

[0015] 10A, 10B, 10C, 10D: Pixel structure

[0016] 100:Substrate

[0017] 110: Light shielding layer

[0018] 112a: first data line light shielding portion

[0019] 112b: second data line light shielding portion

[0020] 112c: third data line light shielding portion

[0021] 112as,114as,114bs,118as,118bs,152s,172s,174s,176s: Side

[0022] 114a: first conductive hole light shielding portion

[0023] 114b: second conductive hole light shielding portion

[0024] 116: Semiconductor layer light shielding part

[0025] 118a: first scanning line light shielding portion

[0026] 118b: second scanning line light shielding portion

[0027] 120: first insulating layer

[0028] 130: Semiconductor layer

[0029] 140: Second insulation layer

[0030] 150: first conductive layer

[0031] 152: Scan Line

[0032] 160: The third insulating layer

[0033] 170: second conductive layer

[0034] 172: first source / drain

[0035] 172h: first conductive hole

[0036] 174: Second source / drain

[0037] 174h: second conductive hole

[0038] 176: Data cable

[0039] 176a: first extension

[0040] 176b: Second extension

[0041] 176c: bending part

[0042] 180: Fourth insulation layer

[0043] 190: Pixel electrode layer

[0044] 192: Pixel electrode

[0045] AP,BP:point

[0046] a1,a2,a3,a4,a5,a6,a7,b1,b2,b3,x1,x2,x3: distance

[0047] D1: Outer area

[0048] D2: Central Area

[0049] DA: Display Area

[0050] DL: Length

[0051] DR1: First Direction

[0052] DR2: Second direction

[0053] DR3: Third direction

[0054] DR4: Fourth Direction

[0055] DV: driving circuit

[0056] PA: Peripheral area

[0057] PL:Liquid crystal display panel

[0058] W1: Width

[0059] Y1: Spacing

[0060] Y2: Length DETAILED DESCRIPTION

[0061] Figure 1A is a schematic top view of a pixel structure 10A according to the first embodiment of the present invention. Figure 1B It is along Figure 1A Please refer to the cross-sectional diagram of the line A-A' and the line B-B'. Figure 1A The pixel structure 10A includes a substrate 100, a light shielding layer 110, a first insulating layer 120, a semiconductor layer 130, a second insulating layer 140, a first conductive layer 150, a third insulating layer 160 and a second conductive layer 170. In this embodiment, the pixel structure 10A further includes a fourth insulating layer 180 and a pixel electrode layer 190.

[0062] The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylenenaphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

[0063] The light shielding layer 110 is located on the substrate 100. In some embodiments, the light shielding layer 110 directly contacts the top surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer, a water and gas barrier layer or other structures are further included between the light shielding layer 110 and the substrate 100.

[0064] The light shielding layer 110 includes a plurality of parts separated from each other. Specifically, the light shielding layer 110 includes a plurality of data line light shielding parts (including a first data line light shielding part 112a, a plurality of second data line light shielding parts 112b, and a third data line light shielding part 112c), a plurality of scan line light shielding parts (including a first scan line light shielding part 118a and a second scan line light shielding part 118b), a plurality of semiconductor layer light shielding parts 116, a plurality of first conductive hole light shielding parts 114a, and a plurality of second conductive hole light shielding parts 114b. In some embodiments, the above-mentioned light shielding parts separated from each other are all floating. In other words, each of the first data line light shielding portion 112a, multiple second data line light shielding portions 112b and the third data line light shielding portion 112c, the first scan line light shielding portion 118a, the second scan line light shielding portion 118b, the semiconductor layer light shielding portion 116, the first conductive hole light shielding portion 114a and the second conductive hole light shielding portion 114b is not directly connected to other signal sources.

[0065] The light shielding layer 110 has a single-layer structure or a multi-layer structure. In some embodiments, the material of the light shielding layer 110 includes molybdenum, chromium, tungsten, black resin, other suitable materials or a combination of the above materials.

[0066] The first insulating layer 120 is located on the light-shielding layer 110, and covers the data line light-shielding portion (including the first data line light-shielding portion 112a, the second data line light-shielding portion 112b and the third data line light-shielding portion 112c), the scan line light-shielding portion (including the first scan line light-shielding portion 118a and the second scan line light-shielding portion 118b), the semiconductor layer light-shielding portion 116, the first conductive hole light-shielding portion 114a and the second conductive hole light-shielding portion 114b.

[0067] In some embodiments, the material of the first insulating layer 120 includes an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or a stacked layer of at least two of the above materials), an organic material, other suitable materials, or a combination thereof.

[0068] The semiconductor layer 130 is located on the first insulating layer 120. Each semiconductor layer 130 at least partially overlaps with the corresponding semiconductor layer light shielding portion 116. For example, each semiconductor layer 130 partially overlaps with the corresponding semiconductor layer light shielding portion 116 in the normal direction of the top surface of the substrate 100. Through such a configuration, it is possible to prevent ambient light from the back of the substrate 100 from irradiating the semiconductor layer 130, thereby causing leakage problems of the thin film transistor.

[0069] The semiconductor layer 130 has a single-layer structure or a multi-layer structure. In some embodiments, the semiconductor layer 130 includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above materials) or other suitable materials or a combination of the above materials.

[0070] The second insulating layer 140 is located on the semiconductor layer 130. In some embodiments, the material of the second insulating layer 140 includes an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials or a stacked layer of at least two of the above materials), an organic material or other suitable materials or a combination thereof.

[0071] The first conductive layer 150 is located on the second insulating layer 140 and includes a plurality of scan lines 152 extending along the first direction DR1. Each scan line 152 partially overlaps with the corresponding plurality of semiconductor layers 130. The portion of the scan line 152 overlapping with the semiconductor layer 130 may also be referred to as a gate of a thin film transistor.

[0072] The first conductive layer 150 has a single-layer structure or a multi-layer structure. In some embodiments, the material of the first conductive layer 150 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, their alloys, their metal oxides, their metal nitrides, or their combinations or other conductive materials.

[0073] The scan line light shielding portion (including the first scan line light shielding portion 118a and the second scan line light shielding portion 118b) in the light shielding layer 110 overlaps the scan line 152 in the first conductive layer 150 in the normal direction of the top surface of the substrate 100. For example, the first scan line light shielding portion 118a and the second scan line light shielding portion 118b are arranged along the first direction DR1 and overlap a corresponding scan line 152. The first scan line light shielding portion 118a and the second scan line light shielding portion 118b are separated from each other, and the semiconductor layer light shielding portion 116 is located between the first scan line light shielding portion 118a and the second scan line light shielding portion 118b.

[0074] In some embodiments, in the first direction DR1, a distance b1 between the semiconductor layer light shielding portion 116 and the first scan line light shielding portion 118a and a distance b2 between the semiconductor layer light shielding portion 116 and the second scan line light shielding portion 118b are greater than 0 micrometers and less than or equal to 10 micrometers.

[0075] In the present embodiment, by separating the semiconductor layer light shielding portion 116 from the first scan line light shielding portion 118a and the second scan line light shielding portion 118b, the crosstalk problem between different signals can be reduced. Specifically, the first scan line light shielding portion 118a and the second scan line light shielding portion 118b overlap the scan line 152 in the normal direction of the top surface of the substrate 100 but do not overlap the semiconductor layer 130. As a result, the first scan line light shielding portion 118a and the second scan line light shielding portion 118b are almost only coupled with the signal on the scan line 152, avoiding them from being coupled with the signal on the scan line 152 and the signal on the semiconductor layer 130 at the same time. If the first scan line light shielding portion 118a and the second scan line light shielding portion 118b are coupled with the signal on the scan line 152 and the signal on the semiconductor layer 130 at the same time, the signal on the scan line 152 and the signal on the semiconductor layer 130 may have a crosstalk problem.

[0076] In some embodiments, the width of the first scan line light shielding portion 118a and the second scan line light shielding portion 118b is greater than or equal to the width of the scan line 152, thereby improving their shielding capabilities for the scan line 152. In some embodiments, the distance between the side 118as of the vertical projection pattern of the first scan line light shielding portion 118a on the substrate 100 and the side 152s of the vertical projection pattern of the scan line 152 on the substrate 100 is greater than or equal to 0 and less than or equal to 10 microns, and the side 118bs of the second scan line light shielding portion 118b and the scan line 152 also have a similar configuration.

[0077] The third insulating layer 160 is located on the first conductive layer 150. In some embodiments, the material of the third insulating layer 160 includes an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials or a stacked layer of at least two of the above materials), an organic material or other suitable materials or a combination thereof.

[0078] The second conductive layer 170 is located on the third insulating layer 160 and includes a first source / drain 172, a second source / drain 174, and a data line 176. The first source / drain 172 and the second source / drain 174 are connected to the semiconductor layer 130. For example, the first source / drain 172 and the second source / drain 174 extend through the second insulating layer 140 and the third insulating layer 160 to connect to the corresponding semiconductor layer 130. The portion of the first source / drain 172 extending through the second insulating layer 140 and the third insulating layer 160 may be referred to as a first conductive hole 172h, and the portion of the second source / drain 174 extending through the second insulating layer 140 and the third insulating layer 160 may be referred to as a second conductive hole 174h. The contact surface between the first source / drain 172 (or the first conductive hole 172h) and the semiconductor layer 130 overlaps the first conductive hole light shielding portion 114a. The contact surface between the second source / drain 174 (or the second conductive hole 174 h ) and the semiconductor layer 130 overlaps the second conductive hole light shielding portion 114 b .

[0079] In some embodiments, the first conductive hole light shielding portion 114a and the second conductive hole light shielding portion 114b are arranged along the first direction DR1. In some embodiments, in the first direction DR1, the distance b3 between the first conductive hole light shielding portion 114a and the second conductive hole light shielding portion 114b is greater than 0 micrometers and less than or equal to 10 micrometers.

[0080] In some embodiments, in a direction perpendicular to the first direction DR1 (for example, the fourth direction DR4 in the figure), the distance a3 between the semiconductor layer light shading portion 116 and the first conductive hole light shading portion 114a, the distance a2 between the semiconductor layer light shading portion 116 and the second conductive hole light shading portion 114b, and the distance a1 between the second conductive hole light shading portion 114b and the first scan line light shading portion 118a are greater than 0 microns and less than or equal to 10 microns.

[0081] In this embodiment, by making the first conductive hole light shielding portion 114 a and the second conductive hole light shielding portion 114 b independent of each other and separated from other light shielding portions in the light shielding layer 110 , the crosstalk problem between different signals can be reduced.

[0082] In some embodiments, a distance x2 between at least one side 114as of a vertical projection pattern of the first conductive hole light shielding portion 114a on the substrate 100 and at least one side 172s of a vertical projection pattern of the first source / drain 172 on the substrate 100 is greater than or equal to 0 and less than or equal to 10 micrometers. The first conductive hole light shielding portion 114a extends beyond at least one side 172s, which is beneficial to improving the shielding ability of the first conductive hole light shielding portion 114a to the first source / drain 172.

[0083] In some embodiments, a distance x3 between at least one side 114bs of a vertical projection pattern of the second conductive hole light shielding portion 114b on the substrate 100 and at least one side 174s of a vertical projection pattern of the second source / drain 174 on the substrate 100 is greater than or equal to 0 and less than or equal to 10 micrometers. The second conductive hole light shielding portion 114b extends beyond at least one side 174s, which is beneficial to improving the shielding ability of the second conductive hole light shielding portion 114b to the second source / drain 174.

[0084] The data line 176 is connected to the first source / drain 172. In the present embodiment, the data line 176 is connected to the first source / drain 172 as a whole. In some embodiments, the data line 176 includes a first extension portion 176a, a second extension portion 176b, and a bending portion 176c. The first extension portion 176a extends along the second direction DR2; the second extension portion 176b extends along a third direction DR3 that is not parallel to the second direction DR2; and the bending portion 176c connects the first extension portion 176a and the second extension portion 176b. In some embodiments, a plurality of first extension portions 176a and a plurality of second extension portions 176b are alternately arranged so that the data line 176 as a whole extends along the fourth direction DR4.

[0085] The first extending portion 176a, the second extending portion 176b, and the bending portion 176c overlap the first data line light shielding portion 112a, the second data line light shielding portion 112b, and the third data line light shielding portion 112c, respectively.

[0086] In some embodiments, in the fourth direction DR4, the distance a5 between the first conductive hole light shielding portion 114a and the first data line light shielding portion 112a, the distance a6 between the first data line light shielding portion 112a and the third data line light shielding portion 112c, the distance a7 between the third data line light shielding portion 112c and the second data line light shielding portion 112b, and the distance a4 between the second data line light shielding portion 112b and another semiconductor layer light shielding portion 116 are greater than 0 microns and less than or equal to 10 microns.

[0087] In this embodiment, the crosstalk problem between different signals can be reduced by separating the first conductive hole light shielding portion 114a, the first data line light shielding portion 112a, the second data line light shielding portion 112b, the third data line light shielding portion 112c and the semiconductor layer light shielding portion 116. Specifically, the light shielding portions located in different areas may be coupled with different signal lines. Therefore, by using multiple light shielding portions corresponding to the same data line 176, it is possible to prevent the signals on the above-mentioned different signal lines (for example, signals on different scanning lines 152) from interfering with each other through the light shielding portions.

[0088] For example, the first data line light shielding portion 112a, the second data line light shielding portion 112b, and the third data line light shielding portion 112c overlap the data line 176 in the normal direction of the top surface of the substrate 100 but do not overlap the scan line 152. Therefore, the first data line light shielding portion 112a, the second data line light shielding portion 112b, and the third data line light shielding portion 112c are almost only coupled with the signal on the data line 176, avoiding coupling with the signal on the data line 176 and the signal on the scan line 152 at the same time.

[0089] In some embodiments, the width of the first data line light shielding portion 112a, the width of the second data line light shielding portion 112b, and the width of the third data line light shielding portion 112c are respectively greater than or equal to the width of the first extension portion 176a, the width of the second extension portion 176b, and the width of the bending portion 176c, thereby improving their shielding capabilities for the data line 176. In some embodiments, the distance x1 between the side 112as of the vertical projection pattern of the first data line light shielding portion 112a on the substrate 100 and the side 176s of the vertical projection pattern of the data line 176 on the substrate 100 is greater than or equal to 0 and less than or equal to 10 microns, and the second data line light shielding portion 112b and the third data line light shielding portion 112c have similar configurations.

[0090] In some embodiments, the spacing between two adjacent scan lines 152 is Y1, where the spacing Y1 can also be referred to as the length of a sub-pixel. In some embodiments, the length Y2 of the third data line light shielding portion 176c in the direction perpendicular to the first direction DR1 (i.e., the fourth direction DR4) is greater than or equal to 2 micrometers and less than or equal to 0.9 times Y1.

[0091] The fourth insulating layer 180 is located on the second conductive layer 170. In some embodiments, the material of the fourth insulating layer 180 includes an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials or a stacked layer of at least two of the above materials), an organic material or other suitable materials or a combination thereof.

[0092] The pixel electrode layer 190 is located on the fourth insulating layer 180 and includes a plurality of pixel electrodes 192. Each pixel electrode 192 is electrically connected to a corresponding second source / drain 174.

[0093] In some embodiments, liquid crystal molecules (not shown) are further included above the pixel electrode 192 , and the directions of the liquid crystal molecules can be controlled by the electric field between the common electrode (not shown) and the pixel electrode 192 .

[0094] Figure 2 1 is a schematic top view of a pixel structure 10B according to the second embodiment of the present invention. It must be noted here that: Figure 2 The implementation examples are used Figure 1A and Figure 1B The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0095] Figure 2 The pixel structure 10B and Figure 1A The difference between the pixel structure 10A and the pixel structure 10B is that in the pixel structure 10B, the light shielding layer 110 does not include a scan line light shielding portion (eg, a first scan line light shielding portion 118a and a second scan line light shielding portion 118b).

[0096] Figure 3 is a top view schematic diagram of a pixel structure 10C according to the third embodiment of the present invention. It must be noted here that: Figure 3 The implementation examples are used Figure 1A and Figure 1B The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0097] Figure 3 The pixel structure 10C and Figure 1A The difference between the pixel structure 10A and the pixel structure 10C is that in the pixel structure 10C, the light shielding layer 110 does not include the first scan line light shielding portion 118a, the second scan line light shielding portion 118b, the first data line light shielding portion 112a, the second data line light shielding portion 112b and the third data line light shielding portion 112c.

[0098] Figure 4 FIG. 1 is a schematic top view of a pixel structure 10D according to a fourth embodiment of the present invention. It must be noted that: Figure 4 The implementation examples are used Figure 1A and Figure 1BThe component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0099] Figure 4 The pixel structure of 10D and Figure 1A The difference between the pixel structure 10A and the pixel structure 10D is that in the pixel structure 10D, the light shielding layer 110 does not include the first scan line light shielding portion 118a, the second scan line light shielding portion 118b, the first conductive hole light shielding portion 114a and the second conductive hole light shielding portion 114b.

[0100] The pixel structure of the first embodiment (reference Figure 1A ) of the liquid crystal display device. Figure 2 ) of the liquid crystal display device. Figure 3 ) of the liquid crystal display device. Figure 4 ) of the liquid crystal display device.

[0101] The contrast ratio and crosstalk ratio of the liquid crystal display device including the pixel structure of the comparative example are measured. In the comparative example, the pixel structure in the liquid crystal display device is similar to the pixel structure of the first to fourth embodiments, except that the light shielding layer of the pixel structure of the comparative example only includes a semiconductor layer light shielding portion and no other light shielding portions. The contrast ratio and crosstalk ratio of the liquid crystal display device corresponding to the comparative example and the first to fourth embodiments are shown in Table 1.

[0102] Table 1

[0103]

[0104] In Table 1, the central contrast value refers to the contrast value of the liquid crystal display panel at the main viewing angle. The ID 19 contrast value refers to taking four points on the liquid crystal display panel, comparing the contrast values ​​of these four points and selecting the smallest value. The above four points are respectively located at a tilt angle (theta angle) of 42.5 degrees and an azimuth angle (phi angle) of 156.6 degrees, a tilt angle of 42.5 degrees and an azimuth angle of 23.5 degrees, a tilt angle of 40.6 degrees and an azimuth angle of 191.9 degrees, and a tilt angle of 40.6 degrees and an azimuth angle of 348.2 degrees.

[0105] The calculation method of the crosstalk rate in Table 1 can be combined with Figure 5A as well as Figure 5BThe liquid crystal display panel PL includes a display area DA and a peripheral area PA. The display area DA includes a plurality of pixel structures (eg, a plurality of Figures 1A to 4 The display area DA has a length DL, and the length DL is, for example, a straight line distance from one side of the display area DA close to the driving circuit DV to the other side of the display area DA away from the driving circuit DV. The peripheral area PA includes the driving circuit DV (such as a chip, a gate driving circuit, etc.).

[0106] Select a point AP and a point BP on the liquid crystal display panel PL, where point AP is located at a position 1 / 8 of the length DL below the top of the center line of the display area DA, and point BP is located at a position 1 / 8 of the length DL above the bottom of the center line of the display area DA. First, adjust the brightness of the entire display area DA of the liquid crystal display panel PL to L128, and measure the actual brightness of point AP and point BP, such as Figure 5A The actual brightness of point AP at this time is AP', and the actual brightness of point BP at this time is BP'. Next, the brightness of the peripheral area D1 of the display area DA is adjusted to L128, and the brightness of the central area D2 of the display area DA is adjusted to L256, and the actual brightness of point AP and point BP is measured, as shown in FIG. Figure 5B As shown. The actual brightness of point AP at this time is AP", and the actual brightness of point B at this time is BP". The width W1 of the peripheral area D1 is approximately 1 / 4 of the length DL.

[0107] The crosstalk rate at point AP is Abs(AP'-AP") / AP', and the crosstalk rate at point BP is Abs(BP'-BP") / BP', where Abs represents an absolute value. The larger of the two is the crosstalk rate shown in Table 1.

[0108] It can be seen from Table 1 that providing other shading portions in the shading layer except for the semiconductor layer shading portion can effectively improve the central contrast value and the ID 19 contrast value. In addition, since the shading portions in the shading layer in the first to fourth embodiments are separated from each other, it is beneficial to avoid the increase of the crosstalk rate, so that the crosstalk rate is maintained below 1%.

Claims

1. A pixel structure, comprising: a substrate; A light shielding layer is located on the substrate and includes a semiconductor layer light shielding portion, a first data line light shielding portion, a second data line light shielding portion and a third data line light shielding portion which are separated from each other; a first insulating layer, located on the light shielding layer; a semiconductor layer, located on the first insulating layer and at least partially overlapping the light shielding portion of the semiconductor layer; a second insulating layer, located on the semiconductor layer; A first conductive layer, located on the second insulating layer, and comprising: a scan line extending along a first direction and partially overlapping the semiconductor layer; a third insulating layer, located on the first conductive layer; and a second conductive layer, located on the third insulating layer, and comprising: a first source / drain and a second source / drain connected to the semiconductor layer; and A data line connected to the first source / drain and comprising: A first extending portion extending along a second direction and overlapping the first data line light shielding portion; a second extending portion extending along a third direction and overlapping the second data line light shielding portion; and A bending portion connects the first extending portion and the second extending portion and overlaps the third data line light shielding portion. 2 . The pixel structure as claimed in claim 1 , wherein a width of the first data line light shielding portion is greater than or equal to a width of the first extending portion, and a width of the second data line light shielding portion is greater than or equal to a width of the second extending portion.

3. The pixel structure as described in claim 1, wherein the light-shielding layer further includes a first conductive hole light-shielding portion and a second conductive hole light-shielding portion, wherein the contact surface between the first source / drain and the semiconductor layer overlaps with the first conductive hole light-shielding portion, and the contact surface between the second source / drain and the semiconductor layer overlaps with the second conductive hole light-shielding portion.

4. The pixel structure as described in claim 1, wherein the first conductive layer includes a plurality of scanning lines extending along the first direction, wherein the spacing between two adjacent ones of the plurality of scanning lines is Y1, and the length of the third data line light shielding portion in a direction perpendicular to the first direction is greater than or equal to 2 microns and less than or equal to 0.9 times Y1. 5 . The pixel structure as claimed in claim 1 , wherein a distance between the first data line light shielding portion and the third data line light shielding portion and a distance between the second data line light shielding portion and the third data line light shielding portion are greater than 0 micrometers and less than or equal to 10 micrometers.

6. A pixel structure comprising: a substrate; A light shielding layer is located on the substrate and includes a semiconductor layer light shielding portion, a first conductive hole light shielding portion and a second conductive hole light shielding portion which are separated from each other; a first insulating layer, located on the light shielding layer; A semiconductor layer, located on the first insulating layer and at least partially in the light shielding portion of the semiconductor layer; a second insulating layer, located on the semiconductor layer; A first conductive layer, located on the second insulating layer, and comprising: a scan line extending along a first direction and partially overlapping the semiconductor layer; a third insulating layer, located on the first conductive layer; and a second conductive layer, located on the third insulating layer, and comprising: A first source / drain connected to the semiconductor layer, wherein a contact surface between the first source / drain and the semiconductor layer overlaps the first conductive hole light shielding portion; a second source / drain connected to the semiconductor layer, wherein a contact surface between the second source / drain and the semiconductor layer overlaps the second conductive hole light shielding portion; and A data line is connected to the first source / drain. 7 . The pixel structure as claimed in claim 6 , wherein the light shielding layer further comprises a first scan line light shielding portion and a second scan line light shielding portion overlapping the scan line, wherein the first scan line light shielding portion is separated from the second scan line light shielding portion.

8. The pixel structure as described in claim 7, wherein the semiconductor layer light-shielding portion is located between the first scan line light-shielding portion and the second scan line light-shielding portion, wherein in the first direction, the distance between the semiconductor layer light-shielding portion and the first scan line light-shielding portion, the distance between the semiconductor layer light-shielding portion and the second scan line light-shielding portion, and the distance between the first conductive hole light-shielding portion and the second conductive hole light-shielding portion are greater than 0 microns and less than or equal to 10 microns.

9. The pixel structure as described in claim 7, wherein in a direction perpendicular to the first direction, the distance between the semiconductor layer light-shielding portion and the first conductive hole light-shielding portion, the distance between the semiconductor layer light-shielding portion and the second conductive hole light-shielding portion, and the distance between the second conductive hole light-shielding portion and the first scan line light-shielding portion are greater than 0 microns and less than or equal to 10 microns. 10 . The pixel structure as claimed in claim 7 , wherein the width of the first scan line light shielding portion and the second scan line light shielding portion is greater than or equal to the width of the scan line.

11. A pixel structure as described in claim 7, wherein the distance between the side of the vertical projection pattern of the first scan line shading portion on the substrate and the side of the vertical projection pattern of the scan line on the substrate is greater than or equal to 0 and less than or equal to 10 microns, wherein the distance between at least one side of the vertical projection pattern of the first conductive hole shading portion on the substrate and at least one side of the vertical projection pattern of the first source / drain on the substrate is greater than or equal to 0 and less than or equal to 10 microns, wherein the distance between at least one side of the vertical projection pattern of the second conductive hole shading portion on the substrate and at least one side of the vertical projection pattern of the second source / drain on the substrate is greater than or equal to 0 and less than or equal to 10 microns.

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