Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, and belongs to the technical field of liquid crystal displayers, the array substrate comprises a substrate, the substrate comprises a display area and a non-display area, the display area comprises a plurality of sub-pixel areas, the non-display area comprises a test circuit, and the test circuit is configured to perform an electrical test on the plurality of sub-pixel areas; the sub-pixel area comprises a first thin film transistor, a pixel electrode layer and a first via hole, and the pixel electrode layer is connected with the first thin film transistor through the first via hole; the test circuit comprises a metal pad, a first signal line, a second signal line and a second via hole, the second via hole is located between the first signal line and the second signal line, one end of the first signal line is connected with the metal pad, the other end of the first signal line is connected with the second signal line through the second via hole, and an electrical conduction path is arranged between the second signal line and the first thin film transistor; wherein at least one first via hole is filled with a first filler, and at least one second via hole is filled with a second filler.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) The first thin film transistor liquid crystal display includes two substrates arranged opposite to each other and a liquid crystal located between the two substrates; in actual use, it is necessary to apply an alignment liquid PI, which forms an alignment layer, and the alignment layer can align the liquid crystal. However, current liquid crystal displays have problems with poor display, such as display abnormalities (one or more rows of gate line signals are disconnected) or display mura at low grayscale. Summary of the invention

[0003] Based on the background technology, the present disclosure proposes an array substrate and a display panel.

[0004] In a first aspect of the present disclosure, an array substrate is provided, comprising:

[0005] A substrate, comprising a display area and a non-display area, wherein the display area comprises a plurality of sub-pixel areas, and the non-display area comprises a test circuit, wherein the test circuit is configured to perform an electrical test on the plurality of sub-pixel areas;

[0006] The sub-pixel area includes a first thin film transistor, a pixel electrode layer and a first via hole, and the pixel electrode layer is connected to the first thin film transistor through the first via hole;

[0007] The test circuit includes a metal pad, a first signal line, a second signal line, and a second via hole, wherein the second via hole is located between the first signal line and the second signal line, one end of the first signal line is connected to the metal pad, and the other end of the first signal line is connected to the second signal line through the second via hole, and an electrical conduction path is provided between the second signal line and the first thin film transistor;

[0008] At least one of the first via holes is filled with a first filler, and at least one of the second via holes is filled with a second filler.

[0009] In an exemplary embodiment, a thickness of a portion of the first filler located in the first via hole is greater than or equal to a depth of the first via hole.

[0010] In an exemplary embodiment, in the thickness direction of the substrate, the distance from the surface of the first filler facing away from the substrate to the substrate is greater than the distance from the surface of the pixel electrode layer facing away from the substrate to the substrate.

[0011] In an exemplary embodiment, an orthographic projection of the first filler on the substrate covers an orthographic projection of the first via on the substrate.

[0012] In an exemplary embodiment, the pixel area includes an opening area, and an orthographic projection of the first filler on the substrate does not overlap with an orthographic projection of the opening area on the substrate.

[0013] In an exemplary embodiment, a plurality of the sub-pixel regions are arranged in an array, and an orthographic projection of the first filler on the substrate covers an orthographic projection of at least two adjacent first via holes in a row direction on the substrate.

[0014] In an exemplary embodiment, in the sub-pixel region, the first thin film transistor and the pixel electrode layer further include: an organic planar layer located on a side of the first thin film transistor away from the substrate, a common electrode layer located on a side of the organic planar layer away from the substrate, and a passivation layer located on a side of the common electrode layer away from the substrate; wherein,

[0015] The first via hole includes a first sub-via hole located in the organic planar layer and a second sub-via hole located in the passivation layer, and an orthographic projection of the first filler on the substrate covers the orthographic projections of the first sub-via hole and the second sub-via hole on the substrate.

[0016] In an exemplary embodiment, the orthographic projection of the first sub-via on the substrate covers the orthographic projection of the second sub-via on the substrate;

[0017] The distance between the outer contour of the orthographic projection of the first filler on the substrate and the outer contour of the orthographic projection of the first sub-via on the substrate is 2-3 μm.

[0018] In an exemplary embodiment, in the non-display area, the first signal line and the second signal line further include: an organic planar layer and a passivation layer located on a side of the organic planar layer away from the substrate; wherein

[0019] The second via hole includes a third sub-via hole located in the organic planar layer and a fourth sub-via hole located in the passivation layer, and the orthographic projection of the second insulating layer on the substrate covers the orthographic projections of the third sub-via hole and the fourth sub-via hole on the substrate.

[0020] In an exemplary embodiment, the orthographic projection of the third sub-via on the substrate covers the orthographic projection of the fourth sub-via on the substrate;

[0021] Wherein, a distance between an outer contour of an orthographic projection of the second insulating layer on the substrate and an outer contour of an orthographic projection of the third sub-via on the substrate is greater than 5 μm.

[0022] In an exemplary embodiment, in the thickness direction of the substrate, the distance between the surface of the first filler facing away from the substrate and the substrate is greater than the distance between the surface of the second filler facing away from the substrate and the substrate.

[0023] In an exemplary embodiment, a plurality of the first via holes are filled with the first filler;

[0024] The plurality of first fillers correspond to two different heights, where the height is the distance between the surface of the first filler facing away from the substrate and the substrate in the thickness direction of the substrate.

[0025] According to a second aspect of the present disclosure, a display panel is provided, comprising a first substrate and a second substrate arranged opposite to each other, wherein a liquid crystal is arranged between the second substrate and the first substrate;

[0026] Wherein, the first substrate is configured as the array substrate described in any exemplary embodiment of the first aspect.

[0027] In an exemplary embodiment, a plurality of support pillars are dispersed between the first substrate and the second substrate;

[0028] Wherein, at least one of the supporting pillars includes a first filler filling the first via hole.

[0029] In an exemplary embodiment, the support column includes a first support column located on one side of the first substrate, and a second support column located on one side of the second substrate, the first support column and the second support column are in contact with each other, and the orthographic projections of the first support column and the second support column on the substrate overlap;

[0030] Wherein, at least one of the first support columns includes the first filler

[0031] The above-mentioned array substrate and display panel can fill the first via hole in the display area and the second via hole in the non-display area. For example, the hole area located in the display area AA can be filled, so that when coating PI, the thickness uniformity of the alignment layer of the film thickness can be improved; for another example, the hole area located in the non-display area FAA can be filled with a dense film layer, so as to avoid the problem of water vapor intruding into the hole area and corroding the metal wire under the hole area, and the second signal line under the second via hole can be protected, thereby ensuring the normal screen detection.

[0032] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0034] Figure 1 The cross-sectional structure diagram of the hole area of ​​the display area AA in the related art is shown;

[0035] Figure 2 A top view of the hole area of ​​the non-display area FAA in the related art is shown;

[0036] Figure 3 A schematic diagram showing an abnormal H-line display of a display in the related art is shown;

[0037] Figure 4 A schematic top view of an array substrate in an embodiment of the present disclosure is shown;

[0038] Figure 5 A wiring diagram of an array substrate in an embodiment of the present disclosure is shown;

[0039] Figure 6-Figure 8 Schematic diagrams of cross-sectional structures of three pixel regions in the embodiments of the present disclosure are shown respectively;

[0040] Fig. 9 — Fig.11 Schematic diagrams of top views of three pixel regions in the embodiments of the present disclosure are shown respectively;

[0041] Fig.12 An electron microscope image of the array substrate at the first via hole observed under a microscope is shown;

[0042] Fig.13 — Fig.14 Two schematic cross-sectional structures of the non-display area of ​​the embodiments of the present disclosure are respectively shown;

[0043] Fig.15 A schematic diagram showing the layout design of the non-display area of ​​an embodiment of the present disclosure is shown;

[0044] Fig.16 Shows Fig.15 An enlarged schematic diagram of a part of the area;

[0045] Fig.17 A schematic diagram showing the wiring design of the non-display area of ​​an embodiment of the present disclosure is shown;

[0046] Fig.18 A schematic diagram showing the layout of the second filler in the non-display area of ​​an embodiment of the present disclosure;

[0047] Figure 19-21 Schematic diagrams of cross-sectional structures of three display panels in the embodiments of the present disclosure are shown respectively. DETAILED DESCRIPTION

[0048] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0049] In this specification, "electrically connected" and "coupled" include the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0050] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0051] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0052] The "same layer" in the embodiments of the present application refers to the relationship between multiple film layers formed by the same material after the same step (e.g., a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. The polygons in this specification are not strictly defined, and can be approximate triangles, parallelograms, trapezoids, pentagons or hexagons, etc., and there may be some small deformations caused by tolerances.

[0053] In the embodiment of the present application, since the source and drain of the transistor are symmetrical, the source and drain can be interchanged. In the embodiment of the present application, one of the source and drain of the transistor can also be called the first electrode, and the other of the source and drain can be called the second electrode.

[0054] In the related art, there are inevitably multiple hole areas on the array substrate of the two substrates. The hole areas can be regarded as low-lying areas on the array substrate. It is precisely because of the influence of these low-lying areas that the liquid crystal display has a poor display problem. Please refer to Figure 1 , Figure 2 , Figure 3 As shown, Figure 1 FIG. 4 shows a cross-sectional structure diagram of the hole area of ​​the display area AA in the related art, Figure 2 FIG. 1 shows a top view of the hole area of ​​the non-display area FAA in the related art. Figure 3 A schematic diagram showing an abnormal H-line display of a display in the related art is shown.

[0055] like Figure 1 As shown, the display area includes: a substrate 100', a first metal layer 200' located on the side of the substrate 100' facing away from the substrate, a first passivation layer 300' located on the side of the first metal layer 200' facing away from the substrate, an organic layer 400' located on the side of the first passivation layer facing away from the substrate, a second passivation layer 500' located on the side of the organic layer facing away from the substrate, a second metal layer 600' located on the side of the second passivation layer facing away from the substrate, and a PI layer 700' located on the side of the second metal layer facing away from the substrate.

[0056] When the alignment liquid is coated, PI will gather around the hole area H1 due to the surface tension of the alignment liquid, so that the thickness of the alignment layer PI formed around the hole area H1 is relatively high, resulting in PI mura on the screen at low grayscale (32 or 64 grayscale).

[0057] like Figure 2 As shown, the display is generally provided with a screen detection circuit (Cell test circuit). The screen detection circuit will have multiple signal lines, and there will also be a hole area H2 at the signal line. When performing screen detection, water vapor invades the hole area H2, which is easy to corrode the metal layer below the hole area, for example, corroding the wiring connected to the gate line GL of the display area below. In this case, when a GOA (Gate Driven on Array) is provided in the non-display area, if the signal line is connected to the clock signal end of the GOA, a certain clock signal line will be corroded, thus causing a circuit break between the clock signal line and the corresponding GOA. When driving the display, the signal on the corroded clock signal line cannot drive the GOA, thereby causing multiple lines of signals to be short-circuited. As shown in FIG. Figure 2As shown in the figure, the downward corrosion can also invade the pad and corrode the pad. For example, in a display panel with 8CLK design, there will be a signal disconnection in every 8 rows, resulting in the following macroscopic phenomenon: Figure 3 The panel H-line shown is abnormal.

[0058] In view of this, the present disclosure proposes that the hole area of ​​the display area AA (hereinafter referred to as the first via hole 11 in the embodiment) and the hole area of ​​the non-display area FAA (hereinafter referred to as the second via hole 12 in the embodiment) can be filled. For example, the hole area located in the display area AA can be filled, so that when coating PI, the thickness uniformity of the alignment layer of the film thickness can be improved; for another example, the hole area located in the non-display area FAA can be filled with a dense film layer, so as to avoid the problem of water vapor intruding into the hole area and corroding the metal wires located under the hole area, and the signal lines in the hole area can be protected, thereby ensuring the normal screen detection.

[0059] Below, an array substrate and a display panel provided by an embodiment of the present disclosure are exemplarily described with reference to the accompanying drawings.

[0060] Reference Figures 4 to 8 As shown, this embodiment provides an array substrate, which may include a substrate 10 , and a display area AA and a non-display area FAA located on one side of the substrate 10 .

[0061] The display area AA includes a plurality of pixel areas, the pixel area includes a first thin film transistor Q1, a pixel electrode 102 layer and a first via hole 11, and the pixel electrode 102 layer is connected to the first thin film transistor Q1 through the first via hole 11;

[0062] Wherein, the non-display area FAA includes a test circuit, which can be configured to perform electrical tests on a plurality of sub-pixel areas;

[0063] The test circuit may include a metal pad 131, a second via 12, a first signal line 15, and a second signal line 16. The second via 12 is located between the first signal line 15 and the second signal line 16. One end of the first signal line 15 is connected to the metal pad 131, and the other end is connected to the second signal line 16 through the second via 12. An electrical conduction path is provided between the second signal line 16 and the first thin film transistor Q1.

[0064] At least one first via hole 11 is filled with a first filler 111 , and at least one second via hole 12 is filled with a second filler 121 .

[0065] The array substrate in this embodiment can be used as a driving substrate of a liquid crystal display, and a pixel driving circuit is arranged on the array substrate. Figure 5As shown, the array substrate may include a display area AA and a non-display area FAA, and the display area AA includes a plurality of pixel areas, the plurality of pixel areas are arranged in an array, one pixel area corresponds to one sub-pixel, and each pixel area may include a pixel driving circuit, and the pixel driving circuit may include a first thin film transistor Q1. Specifically, the display area AA may include a plurality of gate lines GL and a plurality of data lines DL, and the area formed by the intersection of the plurality of gate lines GL and the plurality of data lines DL is the pixel area, the gate line GL is used to provide a start signal to the first thin film transistor Q1 to start the first thin film transistor Q1, and can be used to provide a cut-off signal to the first thin film transistor Q1 to cut off the first thin film transistor Q1, and the data line DL is used to input a data voltage to the first thin film transistor Q1, and the data voltage can be loaded into the pixel electrode 102 connected to the first thin film transistor Q1, so as to drive the liquid crystal in the liquid crystal display to deflect, and then display the picture.

[0066] Among them, a test circuit can be set in the non-display area FAA, and the electrical test performed on the sub-pixel area by the test circuit can be the above-mentioned screen lighting detection. For example, the screen lighting detection can detect which sub-pixel areas have pixel driving circuit faults, and whether the gate line GL and the data line DL have faults such as breakage and short circuit.

[0067] The test circuit may include a plurality of metal pads 131 and signal lines connected between the metal pads 131 and the first thin film transistor Q1 in the pixel region, wherein the signal lines include a first signal line 15 and a second signal line 16, wherein an electrical conduction path exists between the second signal line 16 and the first thin film transistor Q1. Figure 6 As shown, Figure 6 The wiring diagram of the test circuit is shown. The non-display area FAA may include a GOA circuit. The GOA circuit includes multiple shift registers. One shift register may be connected to one or more gate lines GL in the display area AA. The input end of the shift register is used to connect to a clock signal line of the timing controller. The clock signal line may output an electrical signal of alternating effective level and invalid level to the shift register, so that the shift register may output a start signal and a stop signal to the gate line GL. For example, when the signal input to the shift register by the clock signal line is a valid level signal, the shift register outputs a start signal to the gate line GL, thereby starting the first thin film transistor Q1 in a row of pixel areas; when the signal input to the shift register by the clock signal line is an invalid level signal, the shift register outputs a stop signal to the gate line GL, thereby turning off the first thin film transistor Q1 in a row of pixel areas.

[0068] In one example, Figure 5As shown, generally, multiple clock signal lines can be pre-fabricated on the array substrate. Later, when the timing controller is bound, the clock signal line can be electrically connected to the corresponding pin of the timing controller. In this way, the clock signal line can be used as the second signal line 16. One second signal line 16 can correspond to a metal pad 131. The first signal line 15 is connected between the metal pad 131 and the second signal line 16. Therefore, when the screen is detected, the probe contacts the metal pad 131 to input an effective level signal to the first signal line 15, and then the first thin film transistor Q1 in the multi-row pixel area can be turned on, thereby lighting up the entire screen. Therefore, in this embodiment, the first signal line 15 can be connected between the metal pad 131 and the second signal line 16, and the second signal line 16 is connected to the shift register, and the shift register is connected to the gate 20 of the first thin film transistor Q1, so that the electrical conduction between the first thin film transistor Q1 is realized through the shift register. In this way, the electrical conduction path can be understood as the following path: second signal line 16-shift register-gate line GL-first thin film transistor Q1.

[0069] In one example, Figure 5 As shown, one or more data lines DL may also correspond to a metal pad 132, and the first signal line 15 is connected between the metal pad 132 and the data line DL, so that a data voltage signal sufficient to light up the sub-pixel can be input to the data line DL through the metal pad 131. In this way, an effective level signal is input to the metal pad 131 connected to the second signal line 16 to turn on the first thin film transistor Q1 of the multi-row pixel area, and a data voltage signal is input to the metal pad 131 connected to the data line DL, so that the data voltage is input to the first thin film transistor Q1 in the multi-row pixel area to light up the screen.

[0070] Of course, the above example only illustrates the connection method between the metal pad 131 and the first thin film transistor Q1. In some other examples, the test circuit may also include a source control switch connected to each data line DL. The source control switch may use a third thin film transistor. The metal pad 131 may be connected to the source of the source control switch through a signal line. The drain of the source control switch is connected to the data line DL, and the gate 20 of the source control switch is connected to another metal pad 131. Using this example, the screen can be lit up row by row or column by column.

[0071] In some examples, the second signal line 16 may be disposed in the same layer as the gate line GL, the gate line GL may be disposed in the same layer as the source and drain of the first thin film transistor Q1, or the gate line GL may be disposed in the same layer as the gate 20 of the first thin film transistor Q1. In this way, the second signal line 16 may be disposed in the same layer as the gate 20 of the first thin film transistor Q1, or may be disposed in the same layer as the source and drain of the first thin film transistor Q1.

[0072] In this embodiment, the array substrate can be an array substrate of an advanced superdimensional field switching technology ADS (Advanced SuperDimension Switch) liquid crystal display. In this case, the common electrode 81 and the pixel electrode 102 are both located on the array substrate; or, the array substrate can be an array substrate of a TN type liquid crystal display. In this case, the common electrode 81 is located on a color film substrate arranged opposite to the array substrate, and the array substrate includes the pixel electrode 102.

[0073] The via hole (first via hole 11 and second via hole 12 ) filling design provided in this embodiment is applicable to both of the above two array substrates.

[0074] In some examples, such as Figure 7 As shown, a common electrode line 82 may also be included. The common electrode line 82 may be located at a side of the common electrode 81 facing away from the substrate and connected to the common electrode 81 .

[0075] The connection may be an electrical connection.

[0076] like Figure 6 As shown, a cross-sectional structure diagram of an array substrate of an ADS / HADS (super-advanced hyper-dimensional field switching technology) liquid crystal display is shown, Figure 6 As shown, in the sub-pixel area, a first thin film transistor Q1, an organic planarizing layer 70, a common electrode 81 layer, a passivation layer 90 and a pixel electrode 102 layer are sequentially arranged in the thickness direction of the substrate 10. Specifically, the first thin film transistor Q1 may sequentially include a gate electrode 20 located on one side of the substrate 10, a gate insulating layer (31, 32) located on the side of the gate electrode 20 facing away from the substrate 10, a semiconductor layer 40 located on the side of the gate insulating layer (31, 32) facing away from the substrate 10, a source and drain electrode layer located on the side of the semiconductor layer 40 facing away from the substrate 10, and an insulating layer (31, 32) located on the side of the source and drain electrode layer facing away from the substrate 10.

[0077] Among them, Figure 6 As shown, the gate insulating layer (31, 32) may include a first gate insulating layer 31 and a second gate insulating layer 32 located on the side of the first gate insulating layer 31 away from the substrate 10, the source-drain layer may include a source electrode 52 and a drain electrode 51, the source electrode 52 and the drain electrode 51 are both electrically connected to the semiconductor layer, and there is no overlap between the two; the gate insulating layer (31, 32) may include a first insulating layer 31 and a second insulating layer 32, the first insulating layer 31 may be an inorganic material, the second insulating layer 32 may be an organic material, or the first insulating layer 31 may be an organic material, and the second insulating layer 32 may be an inorganic material.

[0078] Among them, the organic planar layer 70 and the passivation layer 90 can cover the entire surface of the substrate 10, that is, the organic planar layer 70 and the passivation layer 90 exist in both the display area AA and the non-display area FAA; specifically, each sub-pixel area can be formed with a first via hole 11, the first via hole 11 penetrates the passivation layer and the organic planar layer in the thickness direction of the substrate, and the pixel electrode 102 layer is connected to the source electrode 52 or the drain electrode 51 in the source-drain electrode layer through the first via hole 11. It should be noted that the pixel electrode 102 layer can include a plurality of pixel electrodes 102, thereby, a planar electric field can be formed between the plurality of pixel electrodes 102.

[0079] Among them, Figure 6 As shown, a first interlayer dielectric layer 61 and a second interlayer dielectric layer 62 may be further included between the organic planar layer 70 and the source-drain electrode layer.

[0080] like Figure 6 As shown, a first metal layer 101 is formed on the hole wall of the first via hole 11. The material of the first metal layer 101 can be the same as the material of the pixel electrode 102 layer, or can be different from the material of the pixel electrode 102 layer. In the case of different materials, the impedance between the pixel electrode 102 and the thin film transistor can be balanced by the first metal layer 101. Exemplarily, the material of the first metal layer 101 can be the same as the material of the pixel electrode 102, such as indium tin oxide ITO.

[0081] like Fig.10 As shown, in the non-display area FAA, a second via 12 may be included, and the second via 12 may be located in the organic planarization layer 70 and the passivation layer 90, wherein the first signal line 15 in the test circuit may be located on the side of the passivation layer 90 of the non-display area FAA away from the substrate 10, and the first signal line 15 is connected to the second signal line 16 below through the second via 12, and the second signal line 16 may be arranged in the same layer as the source and drain layer of the first thin film transistor Q1.

[0082] Among them, a second metal layer 103 is formed on the hole wall of the second via hole 12, and the second metal layer 103 is connected to the first signal line 15 and the second signal line 16 respectively. The material of the second metal layer 103 can be the same as that of the first signal line 15. In this way, when the first signal line 15 is formed, the second metal layer 103 in the second via hole 12 can be formed at the same time.

[0083] In some examples, the depth of the first via hole 11 and the depth of the second via hole 12 may be different. For example, the depth of the first via hole 11 may be smaller than the depth of the second via hole 12 , or the depth of the first via hole 11 may be greater than the depth of the second via hole 12 .

[0084] In this embodiment, the first via hole 11 may be filled with a first filler 111, and the second via hole 12 may be filled with a second filler 121. In some examples, the first filler 111 may be an insulating material, and the second filler 121 may be an insulating material. In this example, the first filler 111 and the second filler 121 are insulating materials.

[0085] In some examples, the thickness of the insulating material layer formed in the first via 11 may be slightly smaller than the depth of the first via 11, for example, the difference between the thickness of the first filler 111 and the depth of the first via 11 may be 0.1 μm, wherein a slope may be formed at the hole wall of the first filler 111 close to the first via 11, so that although the thickness of the first filler 111 is smaller than the depth of the first via 11, the slope may reverse the flow of PI, thereby reducing the aggregation of PI around the via 11 and facilitating the uniform flow of PI.

[0086] In some other examples, the thickness of the insulating material layer formed in the first via 11 may be at least equal to the depth of the first via 11, thereby filling the first via 11 so that when the PI liquid is coated, the PI liquid can flow evenly, avoiding the problem of PI liquid gathering around the via.

[0087] In some examples, the thickness of the second filler 121 can be less than the depth of the second via 12, or greater than the depth of the second via 12, or equal to the depth of the second via 12, so as to prevent water vapor from invading from the second via 12 to the second signal line 16 below through the second filler 121, corroding the second signal line 16 and causing display failure.

[0088] In some examples, the material filling the first via 11 and the material filling the second via 12 may be the same, so that the filling of the first via 11 and the filling of the second via 12 may be completed simultaneously in one process. In some other examples, the material filling the first via 11 and the material filling the second via 12 may be different, for example, the density of the insulating material filling the second via 12 may be greater than the density of the insulating material filling the first via 11, so that the second filler 121 has a higher waterproof performance, and can achieve better protection for the second signal line 16 under the second via 12.

[0089] The first filler 111 may be a transparent insulating material, or may be an opaque insulating material.

[0090] In some examples, the first filler 111 may be formed of an organic material, so that the leveling property of the organic material can be used to form a flat surface at the first via hole 11, thereby facilitating uniform diffusion of the PI liquid. In some examples, the first filler 111 may also be formed of an inorganic material.

[0091] In some other examples, the first filler 111 may be a composite of an organic material and an inorganic material. Exemplarily, the first filler 111 may include an inorganic material layer and an organic material layer, and the inorganic material layer may be located on the side of the organic material layer close to the substrate 10, that is, the inorganic material layer may be first filled in the first via 11, and then the organic material layer may be formed on the inorganic material layer, so that the leveling property of the organic material layer may be utilized to form a flat surface at the first via 11, and the inorganic material is close to the first metal layer 101 in the first via 11, so as to protect the electrical characteristics between the first metal layer 101 and the first thin film transistor Q1.

[0092] In some examples, the second filler 121 may be an inorganic material. The inorganic material has higher stability and density and can resist corrosion by water and oxygen, thereby protecting the second signal line 16 located thereunder.

[0093] In some examples, in the thickness direction of the substrate 10 , the distances between the surfaces of the first filler 111 and the second filler 121 facing away from the substrate 10 and the substrate 10 may be the same or different, which may be referred to as a vertical distance in some cases.

[0094] For example, in the thickness direction of the substrate 10, the distance between the surface of the first filler 111 facing away from the substrate 10 and the substrate 10 may be greater than the distance between the surface of the second filler 121 facing away from the substrate 10 and the substrate 10. In this case, the thickness of the first filler 111 may be greater than the thickness of the second filler 121. For example, the thickness of the first filler 111 may be 1.9 μm to 3.6 μm, and the thickness of the second filler 121 may be 1.8 μm to 3 μm.

[0095] In some examples, the first filler 111 may completely cover the first via hole 11 , and the second filler 121 may completely cover the second via hole 12 , so that the protection of the metal line under the second via hole 12 can be enhanced.

[0096] Please combine Figure 7 As shown, in some exemplary embodiments, the orthographic projection of the first filler 111 on the substrate 10 may cover the orthographic projection of the first via hole 11 on the substrate 10 .

[0097] In an example of this embodiment, the orthographic projection of the first filler 111 on the substrate 10 covers the orthographic projection of the first via hole 11 on the substrate 10, which may mean that the orthographic projection of the first filler 111 on the substrate 10 may coincide with the orthographic projection of the first via hole 11 on the substrate 10, or the orthographic projection of the first via hole 11 on the substrate 10 falls within the orthographic projection of the first filler 111 on the substrate 10. In the case of coincidence, the height of the first filler 111 is at least located at the opening of the first via hole 11, so that the surfaces of the first filler 111 and the passivation layer 90 are roughly flush to improve the diffusion uniformity of the PI liquid.

[0098] In some embodiments, the thickness of the portion of the first filler 111 located in the first via hole 11 may be greater than or equal to the depth of the first via hole 11 .

[0099] For example, the first filler 111 may just fill up the first via hole 11. Figure 8 As shown, the thickness of the first filler 111 in the first via hole 11 is equal to the depth of the first via hole 11, so that the first filler 111 just fills the first via hole 11, so that the surface of the first filler 111 and the passivation layer 90 are roughly flush, and a flat surface is formed at the first via hole 11. For example, the depth of the first via hole 11 is 1.6μm to 1.8μm, and the thickness of the first filler 111 in the first via hole 11 is 1.6μm to 1.8μm, which is consistent with the depth of the first via hole 11. In this case, the orthographic projection of the first filler 111 on the substrate 10 can coincide with the orthographic projection of the first via hole 11 on the substrate 10. In this way, when the PI liquid is coated, the uniformity of the PI liquid coating can be improved, and the PI liquid can be prevented from gathering around the first via hole 11.

[0100] Specifically, the depth of the first via hole 11 may be 1.6 μm, 1.7 μm, or 1.8 μm.

[0101] As another example, the thickness of the first filler 111 in the first via hole 11 may be greater than the depth of the first via hole 11. Figure 7 and Fig. 9 As shown, the depth of the first via hole 11 is 1.6 μm to 1.8 μm, and the thickness of the first filler 111 in the first via hole 11 may be 1.7 μm to 3.6 μm. In this case, the orthographic projection of the first filler 111 on the substrate 10 may coincide with the orthographic projection of the first via hole 11 on the substrate 10, or the orthographic projection of the first via hole 11 on the substrate 10 falls within the orthographic projection of the first filler 111 on the substrate 10. When the thickness of the first filler 111 in the first via hole 11 is greater than the depth of the first via hole 11, the first filler 111 not only fills the first via hole 11, but also may be higher than the opening of the first via hole 11, for example, at least higher than the surface of the passivation layer 90.

[0102] Specifically, the depth of the first via hole 11 may be 1.6 μm, 1.7 μm, or 1.8 μm, and the thickness of the first filler 111 may be 1.7 μm, 1.8 μm, 1.9 μm, 2 μm, 2.3 μm, 2.6 μm, 2.8 μm, 3 μm, 3.2 μm, 1.4 μm, or 3.6 μm.

[0103] The portion of the first filler 111 in the first via hole 11 may refer to a portion where the orthographic projection of the first filler 111 on the substrate overlaps with the orthographic projection of the first via hole 11 on the substrate, for example, Figure 8 As shown, it may be a partial area 1111 where the orthographic projection of the first filler 111 on the substrate overlaps with the orthographic projection of the first via hole 11 on the substrate.

[0104] In an example, when the thickness of the first filler 111 at the first via hole 11 is greater than the depth of the first via hole 11, the minimum distance from the surface of the first filler 111 facing away from the substrate 10 to the substrate 10 may be greater than the minimum distance from the surface of the pixel electrode 102 layer facing away from the substrate 10 to the substrate 10. In this example, Figure 7 As shown, the height of the first filler 111 on the substrate 10 may be greater than the height of the pixel electrode 102 layer on the substrate 10 .

[0105] Exemplarily, the difference between the minimum distance between the surface of the first filler 111 facing away from the substrate 10 and the minimum distance between the surface of the pixel electrode 102 layer facing away from the substrate 10 and the substrate 10 can be 0.1μm to 1.8μm, that is, the height of the first filler 111 on the substrate 10 is 0.1μm to 1.8μm greater than the height of the pixel electrode 102 layer on the substrate 10, for example, can be 0.1μm, 0.2μm, 0.5μm, 0.8μm, 1μm, 1.2μm, 1.4μm, or 1.8μm greater.

[0106] Among them, the higher the height of the first filler 111 on the substrate 10, the more it can be used as a supporting column of the liquid crystal display. For example, when the height of the first filler 111 on the substrate 10 is 1.6μm to 1.8μm greater than the height of the pixel electrode 102 layer on the substrate 10, the first filler 111 can be used as a supporting column formed on the array substrate, and the supporting column can play a role in supporting the space between the array substrate and the color filter substrate when the array substrate and the color filter substrate are aligned.

[0107] In another example, when the thickness of the first filler 111 is greater than the depth of the first via hole 11, the minimum distance from the surface of the first filler 111 facing away from the substrate 10 to the substrate 10 may be less than or equal to the minimum distance from the surface of the pixel electrode 102 layer facing away from the substrate 10 to the substrate 10. Fig. 9 As shown, the height of the first filler 111 on the substrate 10 can be less than or equal to the height of the pixel electrode 102 layer on the substrate 10. In this way, the first filler 111 can be flush with the pixel electrode 102 layer, thereby avoiding the step difference originally existing between the first via hole 11 and the pixel electrode 102 layer. In this way, when the PI liquid is applied, the uniformity of the flow of the PI liquid near the pixel electrode 102 can be further improved, thereby enhancing the alignment consistency of the liquid crystal near the pixel electrode 102 to improve the display quality.

[0108] In some embodiments, each pixel region may include an opening region and a non-opening region, wherein the orthographic projection of the pixel electrode 102 on the substrate 10 may cover the opening region, and a pixel driving circuit may be disposed in the non-opening region, such as the first thin film transistor Q1 being located in the non-opening region. When the array substrate and the color filter substrate are assembled, the non-opening region may overlap with the black matrix layer on the color filter substrate, so that the non-opening region is shielded by the black matrix layer to prevent the metal device in the non-opening region from reflecting light.

[0109] In some embodiments, the material of the first filler 111 may be a transparent material, so that even if part of the first filler 111 intrudes into the opening area, for example, the orthographic projection of the first filler 111 on the substrate 10 may overlap with the orthographic projection of the pixel electrode 102 layer on the substrate 10, but even if the overlap does not affect the passage of light, it can reduce the preparation requirements, thereby reducing the process difficulty. In some embodiments, the first filler 111 may be an opaque material, so that the first filler 111 can protect the first thin film transistor Q1 below, and prevent the semiconductor layer of the first thin film transistor Q1 from being irradiated by light and affecting its electrical characteristics.

[0110] In one example of this embodiment, Fig. 9 As shown, no matter the material of the first filler 111 is a transparent material or a non-transparent material, the orthographic projection of the first filler 111 on the substrate 10 may not overlap with the orthographic projection of the opening area on the substrate 10. In this example, the first filler 111 does not invade the opening area, so that on the one hand, the aperture ratio of the pixel area can be guaranteed, and on the other hand, the material usage of the first filler 111 can be saved.

[0111] In some embodiments, Fig. 9As shown, each pixel region includes a first via hole 11, and the first via holes 11 in each pixel region can be filled with an independent first insulating layer (31, 32), thereby saving materials.

[0112] In some other embodiments, each pixel region includes a first via hole 11, and the first via holes 11 in two or more adjacent pixel regions in the row direction may be filled with the same first filler 111. For example, Fig.10 As shown, two adjacent first via holes 11 in the row direction are filled with the same first filler 111. In this case, the orthographic projection of the first filler 111 on the substrate 10 covers the orthographic projection of the two adjacent first via holes 11 in the row direction on the substrate 10.

[0113] In some other embodiments, the orthographic projection of the first filler 111 on the substrate 10 can also cover the orthographic projections of multiple first vias 11 located in the same row on the substrate 10, so that a first filler 111 is formed in each row of pixel areas. In this case, the first filler 111 can be regarded as an insulating band extending in the row direction. In this case, the process can be saved.

[0114] Of course, in some other examples, the orthographic projection of the first filler 111 on the substrate 10 may cover the orthographic projections of three adjacent first via holes 11 on the substrate 10 or the orthographic projections of four adjacent first via holes 11 on the substrate 10 in the same row.

[0115] In some examples, the plurality of first fillers 111 correspond to two different heights, where the height is the distance between the surface of the first filler 111 facing away from the substrate 10 and the substrate 10 in the thickness direction of the substrate 10. In this way, the heights of the plurality of first fillers 111 on the substrate 10 are not completely the same.

[0116] For example, the distance between the surface of a portion of the first filler 111 facing away from the substrate 10 and the substrate 10 is a first distance, and the distance between the surface of a portion of the first filler 111 facing away from the substrate 10 and the substrate 10 is a second distance; wherein the first distance may be greater than the second distance, the first distance may be the same as the main support column used in the liquid crystal display, and the second distance may be the same as the auxiliary support column used in the liquid crystal display.

[0117] In some embodiments, Figure 7As shown, in the case where the array substrate is an array substrate of an ADS type liquid crystal display, the first thin film transistor Q1 in the sub-pixel area and the pixel electrode 102 layer also include: an organic planar layer 70 located on the side of the first thin film transistor Q1 away from the substrate 10, a common electrode 81 layer located on the side of the organic planar layer 70 away from the substrate 10, and a passivation layer 90 located on the side of the common electrode 81 layer away from the substrate 10; wherein the first via 11 is located in the organic planar layer 70 and the passivation layer 90, then the first via 11 may include a first sub-via 11a located in the organic planar layer 70, and a second sub-via 11b located in the passivation layer 90, wherein the orthographic projection of the first filler 111 on the substrate 10 may cover the orthographic projections of the first sub-via 11a and the second sub-via 11b on the substrate 10.

[0118] In this embodiment, the orthographic projection of the first sub-via 11a on the substrate 10 overlaps with the orthographic projection of the second sub-via 11b on the substrate 10. For example, Figure 6 and Fig.10 As shown, the orthographic projection of the first sub-via 11a on the substrate 10 can cover the orthographic projection of the second sub-via 11b on the substrate 10. In this case, the orthographic projection of the first filler 111 on the substrate 10 can cover the orthographic projection of the first sub-via 11a on the substrate 10. In this way, the orthographic projection of the first filler 111 on the substrate 10 also covers the orthographic projection of the second sub-via 11b on the substrate 10.

[0119] In another example, the orthographic projection of the first sub-via 11a on the substrate 10 may partially overlap with the orthographic projection of the second sub-via 11b on the substrate 10. In this case, the orthographic projection of the first filler 111 on the substrate 10 may cover the orthographic projections of the first sub-via 11a and the second sub-via 11b on the substrate 10.

[0120] In one example, Fig.10 As shown, the aperture of the first sub-via hole 11a may be larger than that of the second sub-via hole 11b. The formation process of the first sub-via hole 11a and the second sub-via hole 11b may refer to the relevant technology and will not be elaborated herein.

[0121] In a further example of this embodiment, the orthographic projection of the first sub-via 11a on the substrate 10 covers the orthographic projection of the second sub-via 11b on the substrate 10. The distance between the outer contour of the orthographic projection of the first filler 111 on the substrate 10 and the outer contour of the orthographic projection of the first sub-via 11a on the substrate 10 is 2-3 μm.

[0122] Please combine Fig.11 As shown, Fig.11 Shows Fig.10 An enlarged schematic diagram of the top plan view shown in Fig.11As shown, the orthographic projection of the first sub-via 11a on the substrate 10 covers the orthographic projection of the second sub-via 11b on the substrate 10, the orthographic projection of the first filler 111 on the substrate 10 covers the orthographic projection of the first sub-via 11a on the substrate 10, and the minimum distance between the boundary of the first filler 111 and the boundary of the first sub-via 11a can be 2 to 3 μm.

[0123] For example, in the row direction, the minimum distance L between the boundary of the first filler 111 and the boundary of the first sub-via 11a may be greater than the minimum distance W between the boundary of the first filler 111 and the boundary of the first sub-via 11a in the column direction. For example, in the row direction, the minimum distance L between the boundary of the first filler 111 and the boundary of the first sub-via 11a may be 2.4 μm, and in the column direction, the minimum distance W between the boundary of the first filler 111 and the boundary of the first sub-via 11a may be 2 μm; for another example, in the row direction, the minimum distance between the boundary of the first filler 111 and the boundary of the first sub-via 11a may be 3 μm, and in the column direction, the minimum distance between the boundary of the first filler 111 and the boundary of the first sub-via 11a may be 2.5 μm.

[0124] In this way, the first filler 111 in one pixel region can be prevented from invading another pixel region adjacent in the column direction.

[0125] As another example, Fig.11 As shown, in the row direction, the minimum distance L between the boundary of the first filler 111 and the boundary of the first sub-via hole 11a may be smaller than the minimum distance W between the boundary of the first filler 111 and the boundary of the first sub-via hole 11a in the column direction. For example, the minimum distance L between the boundary of the first filler 111 and the boundary of the first sub-via hole 11a may be 2.4 μm, and in the column direction, the minimum distance W between the boundary of the first filler 111 and the boundary of the first sub-via hole 11a may be 3.5 μm.

[0126] The minimum distance W between the boundary of the first filler 111 and the boundary of the first sub-via 11a may have different sizes at different locations. For example, on the first side of the first sub-via 11a, the minimum distance W between the boundary of the first filler 111 and the boundary of the first sub-via 11a may be 3.5 μm, and on the second side of the first sub-via 11a, the minimum distance W between the boundary of the first filler 111 and the boundary of the first sub-via 11a may be 4.2 μm.

[0127] In some embodiments, when the orthographic projection of the first filler 111 on the substrate 10 covers two adjacent first vias, the length of the orthographic projection of the first filler 111 on the substrate 10 can be 50 μm and the width can be 16 μm, where the length refers to the dimension in the row direction and the width can be the dimension in the column direction.

[0128] In some embodiments, the shape of the orthographic projection of the first filler 111 on the substrate may be a polygon, a circle, an ellipse, or other symmetrical or asymmetrical shapes. Fig.12 As shown, an electron microscope image of the array substrate at the first via hole is shown under a microscope. Fig.12 As shown, the first filler 111 ( Fig.12 The bump in the middle is a shape with a large middle area and gradually smaller areas on both sides, which may not invade the pixel opening area. In one example, the orthographic projection of the first filler 111 on the substrate may not overlap with the orthographic projection of the pixel electrode 102 on the substrate.

[0129] In some embodiments, the non-display area FAA may also include a second thin film transistor Q2 located on one side of the substrate 10, an organic planar layer 70, and a passivation layer 90 located on the side of the organic planar layer 70 away from the substrate 10 between the first signal line 15 and the second signal line 16. That is, the organic planar layer 70 and the passivation layer 90 may cover the entire surface of the substrate 10, and the organic planar layer 70 in the display area AA and the display area AA are formed in one process, and the passivation layer 90 in the display area AA and the display area AA are formed in one process.

[0130] Among them, the second via 12 of the non-display area FAA can be located in the organic planar layer 70 and the passivation layer 90, which may include a third sub-via 12a located in the organic planar layer 70 and a fourth sub-via 12b located in the passivation layer 90, wherein the orthographic projection of the second insulating layer (31, 32) on the substrate 10 covers the orthographic projection of the third sub-via 12a and the fourth sub-via 12b on the substrate 10.

[0131] Specifically, Fig.15 As shown, the orthographic projection of the third sub-via hole 12 a on the substrate 10 may cover the orthographic projection of the fourth sub-via hole 12 b on the substrate 10 .

[0132] In one example of this embodiment, Fig.15 As shown, the orthographic projection of the third sub-via 12a on the substrate 10 covers the orthographic projection of the fourth sub-via 12b on the substrate 10; wherein the distance between the outer contour of the orthographic projection of the second insulating layer (31, 32) on the substrate 10 and the outer contour of the orthographic projection of the third sub-via 12a on the substrate 10 is greater than 5 μm.

[0133] In one example, the orthographic projection of the second insulating layer ( 31 , 32 ) on the substrate 10 may have a length of 150 μm and a width of 50 μm.

[0134] like Fig.17 As shown, the plurality of first signal lines 15 can be arranged in an array in the non-display area FAA, wherein the orthographic projections of the first signal lines 15 and the second signal lines 16 on the substrate can cross, such as being orthogonal; the ends of the plurality of first signal lines 15 connected to the metal pads 131 are arranged in a zigzag shape on the substrate 10, thereby facilitating the connection between the second signal lines 16 and the metal pads 131. In this way, Fig.18 As shown, the second filler can be arranged in a zigzag pattern on the substrate.

[0135] In some embodiments, Fig.14 As shown, the test circuit further includes a second thin film transistor Q2, the second thin film transistor Q2 is located on a side of the organic planar layer 70 close to the substrate 10, the second signal line 16 is arranged on the same layer as the gate 20 of the second thin film transistor Q2, and the second thin film transistor Q2 further includes a gate insulating layer (31, 32) located between the organic planar layer 70 and the gate 20;

[0136] The second via hole 12 further includes a fifth sub-via hole 12c located in the gate insulating layer (31, 32), and the orthographic projection of the fifth sub-via hole 12c on the substrate 10 does not overlap with the orthographic projection of the fourth sub-via hole 12b on the substrate 10;

[0137] The orthographic projection of the second filler 121 on the substrate 10 also covers the orthographic projection of the fifth sub-via hole 12 c on the substrate 10 .

[0138] In this embodiment, the second thin film transistor Q2 can be a thin film transistor in a shift register, and the second signal line 16 can be connected to the signal input terminal in the shift register. In addition, the second signal line 16 can be arranged in the same layer as the gate 20 of the second thin film transistor Q2, or can be arranged in the same layer as the source and drain of the second thin film transistor Q2.

[0139] Among them, Fig.15 and Fig.16 As shown, taking the second signal line 16 and the gate 20 of the second thin film transistor Q2 in the same layer as an example, the second via 12 may include a fifth sub-via 12c located on the gate insulating layer (31, 32) in addition to the fourth sub-via 12b located on the passivation layer 90, wherein the orthographic projection of the fifth sub-via 12c on the substrate 10 may also be located within the orthographic projection of the third sub-via 12a on the substrate 10. In particular, a plurality of fourth sub-vias 12b and a plurality of fifth sub-vias 12c may be included within the orthographic projection of one third sub-via 12a, and the fourth sub-via 12b and the fifth via may be arranged alternately without overlapping each other.

[0140] The signal line can be connected to the metal line (such as the data line DL) located at the source and drain layer through the fourth sub-via 12b, and can be connected to the metal line (such as the clock signal line connected to the shift register) located at the gate layer 20 through the fifth sub-via 12c.

[0141] The connection referred to in this embodiment may be an electrical connection.

[0142] The orthographic projection of the second filler 121 on the substrate 10 can cover the orthographic projection of the third sub-via 12 a on the substrate 10 , so that the fourth sub-via 12 b and the fifth sub-via 12 c can be covered by the second filler 121 at the same time.

[0143] like Fig.16 As shown, in some embodiments, the orthographic projection of a second filler 121 on the substrate 10 may overlap with the orthographic projections of two adjacent signal lines on the substrate 10. Alternatively, in some other embodiments, the orthographic projection of a second filler 121 on the substrate 10 only overlaps with the orthographic projection of the current signal line on the substrate 10, but does not overlap with other signal lines. The current signal line refers to the first signal line 15 where the second via 12 covered by the second filler 121 is located.

[0144] In some embodiments, Fig.13 As shown, the vertical distance between the surface of the second filler 121 facing away from the substrate 10 and the substrate 10 can be the same as the vertical distance between the surface of the first signal line 15 facing away from the substrate 10 and the substrate 10. In this way, a flat surface can be formed in the non-display area FAA, which is helpful for the subsequent binding of components such as the timing controller and the display driver chip.

[0145] In some embodiments, a display panel is also provided. Fig.19 As shown in FIG. , a schematic diagram of a cross-sectional structure of a display panel is shown. Fig.19 As shown, the first substrate 100 and the second substrate 200 may be included. The first substrate 100 and the second substrate 200 are arranged opposite to each other, and the liquid crystal 300 may be arranged between the first substrate 100 and the second substrate 200.

[0146] The first substrate 100 is configured as the array substrate described in any of the above embodiments.

[0147] Among them, the display panel can be an ADS type display panel, which includes a common electrode 81 and a pixel electrode 102 on one side of the array substrate; or, the display panel can also be a TN display panel, which includes a pixel electrode 102 on one side of the first substrate and a common electrode 81 on a side of the second substrate close to the first substrate, and a vertical electric field is formed between the pixel electrode 102 and the common electrode 81.

[0148] like Fig.19 As shown, a first alignment layer 120 is disposed on a side of the first substrate close to the second substrate, and a second alignment layer 120 is also disposed on a side of the second substrate close to the first substrate. The first alignment layer 120 may be located on a side of the pixel electrode 102 layer away from the substrate 10, that is, the first alignment layer 120 is located on the outermost layer of the array substrate close to the second substrate, and similarly, the second alignment layer 120 is also located on the outermost layer of the second substrate close to the first substrate.

[0149] The second substrate may include a transparent substrate, a black matrix layer 22 located on one side of the transparent substrate, the black matrix layer 22 includes a plurality of opening areas, a color filter layer 23 is arranged in the opening area, the color filter layer 23 may include a green color filter layer 23, a red color filter layer 23 and a blue color filter layer 23, and the orthographic projection of each color filter layer 23 on the array substrate may cover the pixel electrode 102 on the array substrate. The orthographic projection of the black matrix layer 22 on the array substrate may cover the gate line GL, the data line DL and the first thin film transistor Q1 on the array substrate, and has no overlap with the opening area in the pixel area.

[0150] In some embodiments, a plurality of supporting pillars are further distributed on the first substrate and the second substrate, and the plurality of supporting pillars are used to support the first substrate and the second substrate.

[0151] Since the first via hole 11 is filled with the first filler 111 , the first filler 111 may serve as a support column. Exemplarily, there is at least one support column including the first filler 111 .

[0152] For example, Fig.19 As shown, a plurality of support columns can be formed by the first filler 111. In this way, the support columns can be made without any additional process. After the first filler 111 is made, the support columns are formed. In this case, the thickness of the first filler 111 can be increased. For example, the vertical distance between the surface of the first filler 111 facing away from the substrate 10 and the substrate 10 can be greater than the vertical distance between the surface of the pixel electrode 102 layer facing away from the substrate 10 and the substrate 10, which can be 1.6 μm to 1.8 μm. In this way, the first filler 111 has a size of 1.6 μm to 1.8 μm in the thickness direction of the substrate 10 for supporting the first substrate and the second substrate.

[0153] In some examples, such as Fig. 20As shown, the plurality of support columns between the first substrate and the second substrate may include a main support column and an auxiliary support column, and the size of the main support column in the normal direction of the substrate 10 may be greater than the size of the auxiliary support column in the normal direction of the substrate 10, that is, the height of the main support column on the substrate 10 is greater than the height of the auxiliary support column on the substrate 10. The main support column and the auxiliary support column may both be composed of the first filler 111, or either of the main support column and the auxiliary support column may be composed of the first filler 111.

[0154] like Fig. 20 As shown, the first filler 111a serves as a main support column, and the first filler 111b serves as a main auxiliary support column.

[0155] In some examples, such as Fig.21 As shown, the support column may include a first support column located on one side of the first substrate, and a second support column 24 located on one side of the second substrate, the first support column and the second support column 24 are in contact with each other, and the first support column and the second support column 24 overlap in their orthographic projections on the substrate 10; wherein at least one first support column includes a first filler 111.

[0156] like Fig.21 As shown, the first support column and the second support column adopt a top-to-top design, that is, the side of the first support column facing away from the substrate 10 contacts the side of the second support column close to the substrate 10, so that support between the first substrate and the second substrate is provided by the first support column and the second support column 24. In this way, the size of the first support column on the first substrate in the thickness direction of the substrate 10 can be reduced, wherein the plurality of first support columns can be formed by the first filler 111.

[0157] In this embodiment, the design of the first support column and the second support column is adopted to prevent the support column from sliding under the action of external force and scratching the AAPI liquid in the display area, resulting in poor mura display, and can improve the support effect on the first substrate and the second substrate.

[0158] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0159] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0160] The above is a detailed introduction to an array substrate and a display panel provided by the present disclosure. Specific examples are used in this article to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present disclosure, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

[0161] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0162] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

[0163] References herein to "one embodiment," "embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. In addition, please note that examples of the term "in one embodiment" do not necessarily all refer to the same embodiment.

[0164] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0165] In the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0166] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An array substrate, characterized in that: include: A substrate, comprising a display area and a non-display area, wherein the display area comprises a plurality of sub-pixel areas, and the non-display area comprises a test circuit, wherein the test circuit is configured to perform an electrical test on the plurality of sub-pixel areas; The sub-pixel area includes a first thin film transistor, a pixel electrode layer and a first via hole, and the pixel electrode layer is connected to the first thin film transistor through the first via hole; The test circuit includes a metal pad, a first signal line, a second signal line, and a second via hole, wherein the second via hole is located between the first signal line and the second signal line, one end of the first signal line is connected to the metal pad, and the other end of the first signal line is connected to the second signal line through the second via hole, and an electrical conduction path is provided between the second signal line and the first thin film transistor; At least one of the first via holes is filled with a first filler, and at least one of the second via holes is filled with a second filler.

2. The array substrate according to claim 1, characterized in that: A thickness of a portion of the first filler located in the first via hole is greater than or equal to a depth of the first via hole.

3. The array substrate according to claim 1, characterized in that: In the thickness direction of the substrate, a distance from a surface of the first filler facing away from the substrate to the substrate is greater than a distance from a surface of the pixel electrode layer facing away from the substrate to the substrate.

4. The array substrate according to claim 1, characterized in that: The orthographic projection of the first filler on the substrate covers the orthographic projection of the first via on the substrate.

5. The array substrate according to claim 1, characterized in that: The pixel area includes an opening area, and an orthographic projection of the first filler on the substrate has no overlap with an orthographic projection of the opening area on the substrate.

6. The array substrate according to claim 1, characterized in that: The multiple sub-pixel areas are arranged in an array, and the orthographic projection of the first filler on the substrate covers the orthographic projections of at least two adjacent first via holes in the row direction on the substrate.

7. The array substrate according to claim 1, characterized in that: In the sub-pixel region, the first thin film transistor and the pixel electrode layer further include: an organic planar layer located on a side of the first thin film transistor away from the substrate, a common electrode layer located on a side of the organic planar layer away from the substrate, and a passivation layer located on a side of the common electrode layer away from the substrate; wherein, The first via hole includes a first sub-via hole located in the organic planar layer and a second sub-via hole located in the passivation layer, and an orthographic projection of the first filler on the substrate covers the orthographic projections of the first sub-via hole and the second sub-via hole on the substrate.

8. The array substrate according to claim 7, characterized in that: The orthographic projection of the first sub-via on the substrate covers the orthographic projection of the second sub-via on the substrate; The distance between the outer contour of the orthographic projection of the first filler on the substrate and the outer contour of the orthographic projection of the first sub-via on the substrate is 2-3 μm.

9. The array substrate according to claim 1, characterized in that: In the non-display area, the first signal line and the second signal line further include: an organic planar layer and a passivation layer located on a side of the organic planar layer away from the substrate; wherein The second via hole includes a third sub-via hole located in the organic planar layer and a fourth sub-via hole located in the passivation layer, and the orthographic projection of the second insulating layer on the substrate covers the orthographic projections of the third sub-via hole and the fourth sub-via hole on the substrate.

10. The array substrate according to claim 9, characterized in that: The orthographic projection of the third sub-via on the substrate covers the orthographic projection of the fourth sub-via on the substrate; Wherein, a distance between an outer contour of an orthographic projection of the second insulating layer on the substrate and an outer contour of an orthographic projection of the third sub-via on the substrate is greater than 5 μm.

11. The array substrate according to claim 1, characterized in that: In the thickness direction of the substrate, a distance between a surface of the first filler facing away from the substrate and the substrate is greater than a distance between a surface of the second filler facing away from the substrate and the substrate.

12. The array substrate according to claim 1, characterized in that: The first filler is filled into the plurality of the first via holes; The plurality of first fillers correspond to two different heights, where the height is the distance between the surface of the first filler facing away from the substrate and the substrate in the thickness direction of the substrate.

13. A display panel, characterized in that: It comprises a first substrate and a second substrate arranged opposite to each other, and liquid crystal is arranged between the second substrate and the first substrate; Wherein, the first substrate is configured as an array substrate as described in any one of claims 1-12.

14. The display panel according to claim 13, characterized in that: dispersing a plurality of support posts between the first substrate and the second substrate; Wherein, at least one of the supporting pillars includes a first filler filling the first via hole.

15. The display panel according to claim 14, characterized in that: The support column comprises a first support column located at one side of the first substrate, and a second support column located at one side of the second substrate, the first support column and the second support column are in contact with each other, and the orthographic projections of the first support column and the second support column on the substrate overlap; Wherein, at least one of the first support columns includes the first filler.

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