Method, system, device and equipment for real-time bidirectional data transmission between chips

Abstract

The embodiment of the invention provides a method, a system, a device and equipment for real-time bidirectional data transmission between chips. In the embodiment of the invention, the system comprises a first data sending module, a first data receiving module, a first signal selection module, a second data sending module, a second data receiving module and a second signal selection module, the first data sending module comprises a first output end used for sending data to the first signal selection module and a second output end used for sending data to the second data sending module, and the second output end of the first data sending module sends the data to the second signal selection module when sending the data to the second data sending module. The receiving module is also used for receiving data from the second data sending module; the first signal selection module comprises a first input end used for receiving data output by the first output end of the first data sending module and a second data end used for receiving data output by the second output end of the first data sending module.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, system, device and equipment for real-time bidirectional data transmission between chips. Background Art

[0002] D2D (Die-to-Die) communication technology generally refers to a communication method for direct communication between two chips. At present, when chip A sends data to chip B through the same chip interface, i.e., simplex mode, chip B often cannot send data to chip A. This situation leads to a certain limit on the amount of data transmitted between chip A and chip B in a unit time period, which in turn affects the data transmission rate between chip A and chip B. Therefore, how to improve the existing data transmission method between chips, thereby increasing the data transmission rate, still needs to provide further solutions. Summary of the invention

[0003] Multiple aspects of the present application provide a method, system, device and apparatus for real-time bidirectional data transmission between chips, for improving the data transmission rate.

[0004] The embodiment of the present application provides a real-time bidirectional data transmission system between chips, including: the system includes a first data sending module, a first data receiving module, a first signal selection module, a second data sending module, a second data receiving module and a second signal selection module, wherein: the first data sending module includes a first output end for sending data to the second signal selection module, and a second output end for sending data to the second data sending module, and the second output end of the first data sending module is also used to receive data from the second data sending module when sending data to the second data sending module; the first signal selection module includes a first input end for receiving data output from the first output end of the first data sending module, and a second input end for receiving data from the first data receiving module. The second data sending module includes a first output end for sending data to the first signal selection module, and a second output end for sending data to the first data sending module, and the second output end of the second data sending module is also used to receive data from the first data sending module when sending data to the first data sending module; the second signal selection module includes a first input end for receiving data output from the first output end of the second data sending module, a second input end for receiving data output from the second output end of the second data sending module, and an output end for outputting data to the second data receiving module.

[0005] An embodiment of the present application also provides an electronic device, wherein the memory includes a real-time two-way data transmission system.

[0006] An embodiment of the present application also provides a data transmission device, which includes a real-time two-way data transmission system.

[0007] An embodiment of the present application also provides a chip, which includes a real-time bidirectional data transmission system.

[0008] An embodiment of the present application also provides an integrated circuit, which includes a real-time bidirectional data transmission system.

[0009] An embodiment of the present application also provides a real-time bidirectional data transmission method between chips, which is applied to a real-time bidirectional data transmission system, and includes: determining, through the first selector, data sent by a first data sending module; when it is determined through the first selector that the data sent by the first data sending module is a first specified value, selecting the first comparator to judge the output data from the first sending end to obtain the data sent by the second sending end; and, when it is determined through the first selector that the data sent by the first data sending module is a second specified value, selecting the second comparator to judge the output data from the first sending end to obtain the data sent by the second sending end.

[0010] An embodiment of the present application also provides a real-time bidirectional data transmission device between chips, including: a determination module, used to determine the data sent by the first data sending module through the first selector; a selection module, used to select the first comparator to judge the output data from the first sending end when the data sent by the first data sending module is determined to be a first specified value through the first selector, so as to obtain the data sent by the second sending end; and when the data sent by the first data sending module is determined to be a second specified value through the first selector, select the second comparator to judge the output data from the first sending end, so as to obtain the data sent by the second sending end.

[0011] The real-time bidirectional data transmission system between chips provided in the embodiment of the present application includes a first data sending module, a first data receiving module, a first signal selection module, a second data sending module, a second data receiving module and a second signal selection module. Since the first data sending module includes a first output end for sending data to the second signal selection module and a second output end for sending data to the second data sending module, and the second output end of the first data sending module is also used to receive data from the second data sending module when sending data to the second data sending module, it is possible to realize that the first data sending module and the second data sending module send data to each other at the same time, thereby effectively improving the data transmission rate. Moreover, the data sent by the first data sending module can be acquired by the first signal selection module, and the first signal selection module also includes a second input end for receiving data output from the second output end of the first data sending module, that is, the first signal selection module can simultaneously acquire the data sent from the first data sending module and the composite data of the data sent by the first data sending module and the second data sending module, so that the data sent by the first data sending module can be accurately acquired based on the data sent by the first data sending module and the composite data of the data sent by the first data sending module and the second data sending module. Similarly, the second signal selection module can also simultaneously obtain the data sent from the second data sending module and the composite data of the data sent by the first data sending module and the second data sending module, so that the data sent by the second data sending module can be accurately obtained based on the data sent by the second data sending module and the composite data of the data sent by the first data sending module and the second data sending module. This achieves the purpose of accurately obtaining the data sent by the other party when the first data sending module and the second data sending module send data to each other at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0013] Figure 1 A schematic diagram of a real-time bidirectional data transmission system between chips provided by an exemplary embodiment of the present application;

[0014] Figure 2 A schematic diagram of two data transmission links in a real-time bidirectional data transmission system between chips provided by an exemplary embodiment of the present application;

[0015] Figure 3 A method for synchronizing a real-time bidirectional data transmission system between chips provided in an embodiment of the present application Figure 2A schematic diagram of the structure of a bit delay device for signals transmitted by two data transmission links shown;

[0016] Figure 4 A schematic diagram of a waveform of data sent by TX1 and TX2 and a waveform of composite data sent by TX1 and TX2 in a real-time bidirectional data transmission system between chips provided in an embodiment of the present application;

[0017] Figure 5 A schematic diagram of extracting a data waveform sent by TX2 from a waveform of composite data sent by TX1 and TX2 in a real-time bidirectional data transmission system between chips provided by an embodiment of the present application;

[0018] Figure 6 A schematic diagram of the structure of an electronic device / chiplet / chip / integrated circuit provided in an embodiment of the present application;

[0019] Figure 7 A schematic diagram of an implementation flow of a method for real-time bidirectional data transmission between chips provided by an exemplary embodiment of the present application;

[0020] Figure 8 A schematic structural diagram of a real-time bidirectional data transmission device between chips provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0022] First, the terms involved in one or more embodiments of the present application are explained.

[0023] D2D: Die-to-Die, an inter-chip interface, is used to provide a data interface between two chips assembled in the same package. The chip-to-chip interface uses a very short channel to connect the two chips in the package to achieve higher power efficiency and bandwidth efficiency, which exceeds the level achieved by the traditional chip-to-chip interface.

[0024] Comparator: Comparing two or more data items to determine whether they are equal, or to determine the size relationship and arrangement order between them is called comparison. The circuit or device that can achieve this comparison function is called a comparator. A comparator is a circuit that compares an analog voltage signal with a reference voltage. The two inputs of the comparator are analog signals, and the output is a binary signal 0 or 1. When the difference in input voltage increases or decreases and the positive and negative signs remain unchanged, its output remains constant.

[0025] Full Duplex: Full Duplex is a term for communication transmission. Communication allows data to be transmitted in two directions at the same time. It is equivalent to the combination of two simplex communication modes in terms of capability. Full Duplex means that signals can be transmitted in both directions at the same time (instantaneously) (A→B and B→A). It means that A→B and B→A are transmitted at the same time, which is instantaneous synchronization.

[0026] Simplex: The English name is Simplex Communication. The data transmission in simplex mode is one-way. One of the two communicating parties is fixed as the sender and the other is fixed as the receiver. Information can only be transmitted in one direction using one transmission line.

[0027] Network bandwidth: Network bandwidth refers to the amount of data that can be transmitted per unit time (usually 1 second). A network is similar to a highway. The larger the bandwidth, the more lanes a highway has, and the greater its traffic capacity.

[0028] Bandwidth rate: Broadband rate refers to the maximum theoretical rate that can be achieved technically, generally the upload and download speed. The higher the rate, the faster the upload and download.

[0029] Buffer: In the computer field, buffer refers to the buffer register, which is divided into two types: input buffer and output buffer. The former is used to temporarily store the data sent by the peripheral so that the processor can take it away; the latter is used to temporarily store the data sent by the processor to the peripheral. With the CNC buffer, the high-speed CPU and the slow-speed peripheral can be coordinated and buffered to achieve synchronization of data transmission.

[0030] As described in the background technology, in order to improve the data transmission efficiency of the existing simplex mode in D2D, the related technology proposes a bidirectional data transmission method, specifically, there are two data sending ends on the same data transmission link, including a first data sending end and a second data sending end, wherein the first data sending end normally sends data to the second data sending end, and the code type of the data sent by the second data sending end to the first data sending end is opposite to the data code type sent by the first data sending end. Obviously, although this data transmission method also realizes real-time bidirectional data transmission, it is equivalent to that in the same time period, only the data sent by one data sending end is useful. Moreover, the second data sending end will also cause additional power consumption when transmitting data while the first data sending end is sending data.

[0031] To this end, an embodiment of the present application provides a real-time bidirectional data transmission system between chips, the system comprising a first data sending module, a first data receiving module, a first signal selection module, a second data sending module, a second data receiving module and a second signal selection module, the first data sending module comprising a first output end for sending data to the second signal selection module, and a second output end for sending data to the second data sending module, and the second output end of the first data sending module is also used to receive data from the second data sending module when sending data to the second data sending module.

[0032] Since the second output end of the first data sending module is also used to receive data from the second data sending module when sending data to the second data sending module, the first data sending module and the second data sending module can simultaneously send data to each other, thereby effectively improving the data transmission rate. Moreover, the data sent by the first data sending module can be acquired by the first signal selection module, and the first signal selection module also includes a second input end for receiving data output from the second output end of the first data sending module, that is, the first signal selection module can simultaneously acquire the data sent from the first data sending module and the composite data of the data sent by the first data sending module and the second data sending module, so that the data sent by the first data sending module can be accurately acquired based on the data sent by the first data sending module and the composite data of the data sent by the first data sending module and the second data sending module. Similarly, the second signal selection module can also simultaneously acquire the data sent by the second data sending module and the composite data of the data sent by the first data sending module and the second data sending module, so that the data sent by the second data sending module can be accurately acquired based on the data sent by the second data sending module and the composite data of the data sent by the first data sending module and the second data sending module. Thereby, when the first data sending module and the second data sending module send data to each other at the same time, the purpose of accurately acquiring the data sent by the other party is achieved.

[0033] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0034] Figure 1 FIG. 1 is a schematic diagram of a real-time bidirectional data transmission system 100 for inter-chip communication provided by an exemplary embodiment of the present application. Figure 1 As shown, the system may include a first data sending module 110, a first data receiving module 130, a first signal selecting module 120, a second data sending module 210, a second data receiving module 230 and a second signal selecting module 220, wherein:

[0035] The first data sending module 110 includes a first output terminal for sending data to the first signal selecting module 120, and a second output terminal for sending data to the second data sending module 210. When sending data to the second data sending module 210, the second output terminal of the first data sending module 110 is also used to receive data from the second data sending module 110;

[0036] The first signal selection module 120 includes a first input terminal for receiving data output from a first output terminal of the first data sending module 110, a second input terminal for receiving data output from a second output terminal of the first data sending module 110, and an output terminal for outputting data to the first data receiving module 130;

[0037] The second data sending module 210 includes a first output terminal for sending data to the second signal selecting module 220, and a second output terminal for sending data to the first data sending module 110. When sending data to the first data sending module 110, the second output terminal of the second data sending module 210 is also used to receive data from the first data sending module 110;

[0038] The second signal selection module 220 includes a first input terminal for receiving data output from the first output terminal of the second data sending module 210, a second input terminal for receiving data output from the second output terminal of the second data sending module 210, and an output terminal for outputting data to the second data receiving module 230.

[0039] In some exemplary embodiments, the real-time bidirectional data transmission system between chips further includes a first data control module C1 and a second data control module C2;

[0040] The first data sending module 110 includes a first data receiving terminal T1 for receiving data from the first data control module C1, and a first sending terminal TX1 for sending data from the first data control module C1;

[0041] The second data sending module 210 includes a second data receiving terminal T2 for receiving data from the second data control module C2, and a second sending terminal TX2 for sending data from the second data control module C2.

[0042] The data sent by the first data sending module 110 to the second data sending module 210 is from the first data control module C1, and the data sent by the second data sending module 210 to the first data sending module 110 is from the second data control module C2. After receiving the data from the first data control module C1, the first data receiving end T1 sends the data to the first transmitting end TX1, and the first transmitting end TX1 sends the data to the second transmitting end TX2. After receiving the data from the second data control module C2, the second data receiving end T2 sends the data to the second transmitting end TX2, and the second transmitting end TX2 sends the data to the first transmitting end TX1.

[0043] In some exemplary embodiments, the first signal selection module 120 includes a first comparator 11, a second comparator 12 and a first selector 1, and the second signal selection module 220 includes a third comparator 21, a fourth comparator 22 and a second selector 2, wherein:

[0044] The first selector 1 includes a first input terminal for receiving data output from the first data receiving terminal T1, a second input terminal for receiving output data of the first comparator 11, and a third input terminal for receiving output data of the second comparator 12, and an output terminal for outputting data to the first data receiving module 130;

[0045] The first comparator 11 includes an input terminal for receiving data output from the first transmitting terminal TX1, and an output terminal for outputting a comparison result to the first selector 1, and the second comparator 12 includes an input terminal for receiving data output from the first transmitting terminal TX1, and an output terminal for outputting a comparison result to the first selector 1;

[0046] The second selector 2 includes a first input terminal for receiving data output from the second data receiving terminal T2, a second input terminal for receiving output data of the third comparator 21, and a third input terminal for receiving output data of the fourth comparator 22, and an output terminal for outputting data to the second data receiving module 230;

[0047] The third comparator 21 includes an input terminal for receiving data output from the second transmitting terminal TX2, and an output terminal for outputting the comparison result to the second selector 2. The fourth comparator 22 includes an input terminal for receiving data output from the second transmitting terminal TX2, and an output terminal for outputting the comparison result to the second selector 2.

[0048] Among them, the reference comparison values ​​of the first comparator and the second comparator are different, the reference comparison value of the first comparator is 1, and the reference comparison value of the second comparator is 0. The reference comparison values ​​of the third comparator and the fourth comparator are also different, the reference comparison value of the third comparator is 1, and the reference comparison value of the fourth comparator is 0.

[0049] It should be understood that since the data sent by the first transmitting end TX1 and the data sent by the second transmitting end TX2 are both transmitted using a transmission link between TX1 and TX2, when the first transmitting end TX1 and the second transmitting end TX2 simultaneously send data to the opposite end, a superimposed data will be generated on the transmission link between TX1 and TX2. In order to accurately obtain the data sent by the opposite end from the first data receiving module 130 and the second data receiving module 230, the embodiment of the present application can select a matching comparator based on the data sent by the first data sending module 110 and the second data sending module 210, respectively, and eliminate the local data from the superimposed data generated on the transmission link between TX1 and TX2, thereby obtaining the data sent by the opposite end.

[0050] The data sent by the first data sending module 110 and the second data sending module 210 can be obtained through the first input terminal of the first selector 1 for receiving data output from the first data receiving terminal T1, and through the first input terminal of the second selector 2 for receiving data output from the second data receiving terminal T2.

[0051] Specifically, the first selector can select a comparator that matches the data of each bit output by the first data receiving end T1 from the first comparator and the second comparator based on the data output by the first data receiving end T1 received by its first input end, and eliminate the data sent by the first transmitting end TX1 from the data output by the first transmitting end TX1 (that is, the superimposed data of the data sent by the first transmitting end TX1 and the data sent by the second transmitting end TX2 on the transmission link between TX1 and TX2), so that the first data receiving module 130 obtains the data sent by the second transmitting end TX2.

[0052] The second selector can select a comparator that matches the data of each bit output by the second data receiving terminal T2 from the third comparator and the fourth comparator according to the data output by the second data receiving terminal T2 received by its first input terminal, and eliminate the data sent by the second transmitting terminal TX2 from the data output by the second transmitting terminal TX2 (i.e., the superimposed data of the data sent by the first transmitting terminal TX1 and the data sent by the second transmitting terminal TX2 on the transmission link between TX1 and TX2), so that the second data receiving module 230 obtains the data sent by the first transmitting terminal TX1.

[0053] In some exemplary embodiments, in order to achieve synchronization of signals received by the first input terminal and the second input terminal of the first selector 1, and synchronization of signals received by the first input terminal and the second data terminal of the second selector 2, thereby avoiding the problem that glitches appear in the signals received by the first selector 1 and the second selector 2 and thus affect the quality of the eye diagram, the real-time bidirectional data transmission system between chips also includes a first bit delay module BDL1 and a second bit delay module BDL2, the output end of the first bit delay module BDL1 is connected to the first input terminal of the first selector 1, and is used to synchronize the signals received by the first input terminal and the second input terminal of the first selector 1;

[0054] The output end of the second bit delay module BDL2 is connected to the second input end of the second selector 2 for synchronizing the signal received by the first input end and the second data end of the second selector 2 .

[0055] Figure 2 A schematic diagram of two data transmission links in a real-time bidirectional data transmission system between chips provided for an exemplary embodiment of the present application. Among them, data transmission link ① is used to transmit the data received by the first data receiving terminal T1 to the selector 1, so that the selector 1 can determine the data content sent by the local end, i.e., the first data sending module 110, and data transmission link ② is used to transmit the data received by the first data receiving terminal T1 to the first sending terminal TX1, the first comparator 11 or the second comparator 12 in sequence, and finally to the selector 1. Since the first transmitting end TX1 receives the data sent by the first data receiving end T1 and the data sent by the second transmitting end TX2 at the same time, the data transmitted to the comparator 11 or the comparator 12 in the data transmission link ② is the superposition data of the data sent by the first transmitting end TX1 and the second transmitting end TX2. In order to ensure that the first selector 1 can accurately obtain the data sent by the opposite end, that is, the second transmitting end TX2, from the superposition data of the data sent by the first transmitting end TX1 and the second transmitting end TX2 while receiving the data of the local end, the embodiment of the present application adds a first delay module BDL1 to the data transmission link ① with a shorter data transmission distance, so that the data transmitted on the data transmission link ① and the data transmission link ② arrive at the selector 1 at the same time. Similarly, a second delay module BDL2 is also added between the second selector 2 and the second data receiving end T2 to synchronize the signals received by the first input end and the second data end of the second selector 2.

[0056] Figure 3 A method for synchronizing a real-time bidirectional data transmission system between chips provided in an embodiment of the present application Figure 2The schematic diagram of the structure of the bit delay device for the signal transmitted by the two data transmission links shown. Wherein, D1~D4 are four bit delay devices. As an example, the delay time period of each bit delay device can be the same, for example, all are 1ps. The signal can be selected to be output from any one of ①~④ as needed. When the signal is selected to be output from ①, the delay time period reached is 1ps, when the signal is selected to be output from ②, the delay time period reached is 2ps, when the signal is selected to be output from ③, the delay time period reached is 3ps, and when the signal is selected to be output from ④, the delay time period reached is 4ps. As for which output the first bit delay module BDL1 and the second bit delay module BDL2 select the signal from, it can be determined specifically according to simulation, as long as the synchronization of the signals received by the first input terminal and the second input terminal of the first selector 1 and the synchronization of the signals received by the first input terminal and the second data terminal of the second selector 2 can be achieved.

[0057] As another example, Figure 3 The number of the four bit delay devices D1 to D4 shown and the delay time period of each bit delay device can also be set according to the requirements of the delay adjustment accuracy and the delay adjustment range. For example, if the delay adjustment range is 100ps and the delay adjustment accuracy is 1ps, if the bit delay device with a delay time period of 1ps is used to construct the bit delay module, 100 1ps bit delay devices are required to be connected in series, which makes the bit delay module more complicated. In view of this, the embodiment of the present application can select bit delay devices with different delay time periods to construct the bit delay module. As an example, the number of D1 to D4 can be expanded to 10, that is, expanded to D1 to D10, and the delay time periods of these bit delay devices may not be exactly the same, such as the delay time period of D1 to D4 is 1ps, the delay time period of D5 is 5ps, the delay time period of D6 and D7 is 10ps, the delay time period of D8 and D9 is 20ps, and the delay time period of D10 is 30ps. In this way, D1+D2+D3+…+D10=100ps, which satisfies the adjustment range of 100ps, the minimum adjustment unit is 1ps, and also satisfies the delay adjustment accuracy of 1ps. Compared with the bit delay module composed of 100 1ps bit delay devices connected in series, the number of delay devices in the bit delay module is greatly reduced, which is convenient for adjustment and simplifies the structure of the bit delay module.

[0058] In some exemplary embodiments, the first selector 1 selects the first comparator 11 to judge the data output from the second output terminal of the first data sending module 110 when determining that the input data of the first input terminal of the first selector 1 is the first specified value, and selects the second comparator to judge the data output from the second output terminal of the first data sending module 210 when determining that the input data of the first input terminal of the first selector 1 is the second specified value;

[0059] When the second selector 2 determines that the input data of the first input terminal of the second selector 2 is the first specified value, the data output from the second output terminal of the second data sending module 210 is judged by the third comparator 21; and when the second selector 2 determines that the input data of the first input terminal of the second selector 2 is the second specified value, the data output from the second output terminal of the second data sending module 210 is judged by the fourth comparator 22.

[0060] Figure 4 A schematic diagram of the waveform of the data sent by TX1 and TX2 and the waveform of the composite data sent by TX1 and TX2 in the real-time bidirectional data transmission system between chips provided in the embodiment of the present application. Figure 4 It can be seen that the data sent by the first transmitting end TX1 is 10100, the data sent by the second transmitting end TX2 is 01101, and the data after the data sent by the first transmitting end TX1 and the second transmitting end TX2 are superimposed is 10100. Figure 5 A schematic diagram of extracting a data waveform sent by TX2 from a waveform of composite data sent by TX1 and TX2 in a real-time bidirectional data transmission system provided in an embodiment of the present application. For the first selector 1, the data 10100 sent by the first transmitting end TX1 can be obtained through the first input end of the first selector 1, and the data after the superposition of the data sent by the first transmitting end TX1 and the second transmitting end TX2 can be obtained through the second input end of the first signal selection module 120.

[0061] In some exemplary embodiments, the first designated value is 1 and the second designated value is 0. When the first selector 1 determines that the input data of the first input terminal of the first selector 1 is the first designated value 1, the first comparator 11 with the comparison reference value of 1 is selected to judge the data output from the second output terminal of the first data sending module 110, and the first bit value is 0. When the first selector 1 determines that the input data of the first input terminal of the first selector 1 is the second designated value 0, the second comparator 12 with the comparison reference value of 0 is selected to judge the data output from the second output terminal of the first data sending module 110, and the second bit value is 1, and so on, until the data sent by the second sending terminal TX2 is obtained to be 01101.

[0062] When the second selector 2 determines that the input data of the first input terminal of the second selector 2 is the second specified value 0, the fourth comparator 22 with the comparison reference value of 0 is selected to judge the data output from the second output terminal of the second data sending module to obtain the first bit value 1. When the second selector 2 determines that the input data of the first input terminal of the second selector 2 is the first specified value 1, the third comparator 21 with the comparison reference value of 1 is selected to judge the data output from the second output terminal of the second data sending module 210 to obtain the second bit value 0, and so on, until the data sent by the first sending terminal TX1 is obtained to be 10100.

[0063] In some exemplary embodiments, in order to make up for the difference in data processing rates of different data processing modules, the embodiments of the present application respectively add data buffer modules for data caching between the first data receiving terminal T1 and the first transmitting terminal TX1, between the second data receiving terminal T2 and the second transmitting terminal TX2, between the first receiving terminal R1 and the first signal selection module 120, and between the second receiving terminal R2 and the second signal selection module 220. Specifically, the first data transmitting module 110 further includes a first data buffer module Ca1, the output end of the first data buffer module Ca is connected to the input end of the first data transmitting terminal TX1, and is used to cache data to be sent to the first data transmitting terminal TX1;

[0064] The first data receiving module 130 further includes a second data buffer module Ca2 and a first receiving terminal R1. The input terminal of the second data buffer module Ca2 is connected to the output terminal of the first signal selection module 120, and is used to cache the output data of the first signal selection module 120. The output terminal of the second data buffer module Ca2 is connected to the first receiving terminal R1. The first receiving terminal R1 is used to send the output data of the second data buffer module Ca2 to the first data control module C1.

[0065] The second data sending module 210 further includes a third data buffer module Ca3, the output end of the third data buffer module Ca3 is connected to the input end of the second data sending end TX2, and is used to cache the data to be sent to the first data sending end TX2;

[0066] The second data receiving module 230 also includes a fourth data buffer module Ca4 and a second receiving end R2. The input end of the fourth data buffer module Ca4 is connected to the output end of the second signal selector 220 for caching the output data of the second signal selector 220. The output end of the fourth data buffer module Ca4 is connected to the second receiving end R2. The second receiving end R2 is used to send the output data of the fourth data buffer module Ca4 to the second data control module C2.

[0067] The first data buffer module Ca1 and the third data buffer module Ca3 are input buffers, used to temporarily buffer the data sent by the first data control module C1 or the second data control module C2, so that the first transmitting end TX1 and the second transmitting end TX2 can take away the data sent by the first data control module C1 or the second data control module C2. The second data buffer module Ca2 and the fourth data buffer module Ca4 are output buffers, used to temporarily store the data sent to the first data control module C1 or the second data control module C2.

[0068] Obviously, the real-time bidirectional data transmission system between chips provided by the embodiment of the present application is different from the duplex mode. The real-time bidirectional data transmission system between chips only adds a module for eliminating the influence of the data sent by the local end on the basis of the simplex mode, that is, Figure 1 The first signal selection module 120 and the second signal selection module 220 shown in the figure do not need to add an additional transmission link between the first transmitting end TX1 and the second transmitting end TX2, which can not only realize real-time two-way data transmission, but also reduce the power consumption and winding area of ​​the entire system.

[0069] The real-time bidirectional data transmission system between chips provided in the embodiment of the present application includes a first data sending module, a first data receiving module, a first signal selection module, a second data sending module, a second data receiving module and a second signal selection module. Since the first data sending module includes a first output end for sending data to the second signal selection module and a second output end for sending data to the second data sending module, and the second output end of the first data sending module is also used to receive data from the second data sending module when sending data to the second data sending module, it is possible to realize that the first data sending module and the second data sending module send data to each other at the same time, thereby effectively improving the data transmission rate. Moreover, the data sent by the first data sending module can be acquired by the first signal selection module, and the first signal selection module also includes a second input end for receiving data output from the second output end of the first data sending module, that is, the first signal selection module can simultaneously acquire the data sent from the first data sending module and the composite data of the data sent by the first data sending module and the second data sending module, so that the data sent by the first data sending module can be accurately acquired based on the data sent by the first data sending module and the composite data of the data sent by the first data sending module and the second data sending module. Similarly, the second signal selection module can also simultaneously obtain the data sent from the second data sending module and the composite data of the data sent by the first data sending module and the second data sending module, so that the data sent by the second data sending module can be accurately obtained based on the data sent by the second data sending module and the composite data of the data sent by the first data sending module and the second data sending module. This achieves the purpose of accurately obtaining the data sent by the other party when the first data sending module and the second data sending module send data to each other at the same time.

[0070] Figure 6 A schematic diagram of the structure of an electronic device / chiplet / chip / integrated circuit 600 provided in an exemplary embodiment of the present application. The electronic device / chiplet / chip / integrated circuit includes Figure 1 A system 100 for real-time bidirectional data transmission between chips is shown.

[0071] The English name of the core particle is chiplet, which refers to a pre-manufactured chip (die) with specific functions that can be combined and integrated. Specifically, the function of a single SOC chip is split into many small chips (chiplet die), and then advanced packaging technology (2.5D / 3D / Fanout, etc.) is used to reassemble them into a large and complex system in one package, thereby reducing the total cost of the chip.

[0072] Figure 6The electronic device shown may be a device including a core for a real-time bidirectional data transmission system between chips, such as a server, a high-performance terminal device, an automatic driving device, etc. applied to a data center network.

[0073] about Figure 6 The specific implementation of the electronic device / chiplet / chip / integrated circuit shown has been described in detail in the embodiment of the clock phase adjustment system, and will not be elaborated here.

[0074] Figure 7 A flowchart of a real-time bidirectional data transmission method between chips provided by an exemplary embodiment of the present application is provided. The real-time bidirectional data transmission method is applied to Figure 1 to Figure 5 The real-time bidirectional data transmission system between chips is shown. Figure 7 As shown, the method may include:

[0075] Step 710: Determine data sent by the first data sending module through a first selector.

[0076] Step 720, when it is determined by the first selector that the data sent by the first data sending module is a first specified value, select the first comparator to judge the output data from the first sending end to obtain the data sent by the second sending end; and when it is determined by the first selector that the data sent by the first data sending module is a second specified value, select the second comparator to judge the output data from the first sending end to obtain the data sent by the second sending end.

[0077] Optionally, when the data sent by the first data sending module is determined to be a first specified value by the first selector, selecting the first comparator to judge the output data from the first sending end to obtain the data sent by the second sending end includes:

[0078] When the data sent by the first data sending module is determined to be a first specified value by the first selector, a first comparator matching the first specified value is selected;

[0079] The output data from the first transmitting end is judged by the first comparator to obtain the data sent by the second transmitting end.

[0080] Optionally, when the first selector determines that the data sent by the first data sending module is a second specified value, selecting the second comparator to judge the output data from the first sending end to obtain the data sent by the second sending end includes:

[0081] When the data sent by the first data sending module is determined to be a second specified value by the first selector, a second comparator matching the second specified value is selected;

[0082] The output data from the first transmitting end is judged by the second comparator to obtain the data sent by the second transmitting end.

[0083] Figure 7 For details, please refer to the specific implementation method of the real-time bidirectional data transmission method between chips shown in Figure 1 to Figure 5 The specific implementation of the real-time bidirectional data transmission system between chips in the illustrated embodiment will not be described in detail.

[0084] The real-time bidirectional data transmission method between chips provided in the embodiment of the present application is applied to the real-time bidirectional data transmission system between chips. Since the first data sending module includes a first output end for sending data to the second signal selection module and a second output end for sending data to the second data sending module, and the second output end of the first data sending module is also used to receive data from the second data sending module when sending data to the second data sending module, it is possible to realize that the first data sending module and the second data sending module send data to each other at the same time, thereby effectively improving the data transmission rate. Moreover, the data sent by the first data sending module can be acquired by the first signal selection module, and the first signal selection module also includes a second input end for receiving data output from the second output end of the first data sending module, that is, the first signal selection module can simultaneously acquire the data sent from the first data sending module and the composite data of the data sent by the first data sending module and the second data sending module, so that the data sent by the first data sending module can be accurately acquired based on the data sent by the first data sending module and the composite data of the data sent by the first data sending module and the second data sending module. Similarly, the second signal selection module can also simultaneously obtain the data sent from the second data sending module and the composite data of the data sent by the first data sending module and the second data sending module, so that the data sent by the second data sending module can be accurately obtained based on the data sent by the second data sending module and the composite data of the data sent by the first data sending module and the second data sending module. This achieves the purpose of accurately obtaining the data sent by the other party when the first data sending module and the second data sending module send data to each other at the same time.

[0085] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of steps 710 to 720 can be device A; for another example, the execution subject of step 710 can be device A, and the execution subject of step 720 can be device B; and so on.

[0086] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel, and the sequence numbers of the operations, such as 710, 720, etc., are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0087] Figure 8 A schematic diagram of a real-time bidirectional data transmission device 800 for inter-chip communication provided by an exemplary embodiment of the present application. The real-time bidirectional data transmission device is applied to Figure 1 to Figure 5 The real-time bidirectional data transmission system between chips is shown. Figure 8 As shown, the device includes: a determination module 810 and a selection module 820, wherein:

[0088] A determination module 810, configured to determine data sent by the first data sending module through the first selector;

[0089] The selection module 820 is used to select the first comparator to judge the output data from the first sending end to obtain the data sent by the second sending end when the data sent by the first data sending module is determined to be a first specified value through the first selector; and to select the second comparator to judge the output data from the first sending end to obtain the data sent by the second sending end when the data sent by the first data sending module is determined to be a second specified value through the first selector.

[0090] For details, please refer to the structure of the real-time bidirectional data transmission device between chips, the signal flow and data processing process, and the technical effects achieved. Figure 1 to Figure 5 The implementation method and technical effects of the real-time bidirectional data transmission system between chips in the illustrated embodiment are not described in detail.

[0091] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0092] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A real-time bidirectional data transmission system between chips, characterized in that: The system comprises a first data sending module, a first data receiving module, a first signal selecting module, a second data sending module, a second data receiving module and a second signal selecting module, wherein: The first data sending module comprises a first output end for sending data to the first signal selection module, and a second output end for sending data to the second data sending module, and the second output end of the first data sending module is also used to receive data from the second data sending module when sending data to the second data sending module; The first signal selection module comprises a first input terminal for receiving data output from a first output terminal of the first data sending module, a second input terminal for receiving data output from a second output terminal of the first data sending module, and an output terminal for outputting data to the first data receiving module; The second data sending module comprises a first output end for sending data to the second signal selecting module, and a second output end for sending data to the first data sending module, and the second output end of the second data sending module is further used to receive data from the first data sending module when sending data to the first data sending module; The second signal selection module includes a first input end for receiving data output from a first output end of the second data sending module, a second input end for receiving data output from a second output end of the second data sending module, and an output end for outputting data to the second data receiving module.

2. The system according to claim 1, characterized in that The system also includes a first data control module and a second data control module; The first data sending module includes a first data receiving end for receiving data from the first data control module, and a first sending end for sending data from the first data control module; The second data sending module includes a second data receiving end for receiving data from the second data control module, and a second sending end for sending data of the second data control module.

3. The system according to claim 2, characterized in that The first signal selection module includes a first comparator, a second comparator and a first selector, and the second signal selection module includes a third comparator, a fourth comparator and a second selector, wherein: The first selector comprises a first input terminal for receiving data output from the first data receiving terminal, a second input terminal for receiving output data of the first comparator, and a third input terminal for receiving output data of the second comparator, and an output terminal for outputting data to the first data receiving module; The first comparator includes an input terminal for receiving data output from the first transmitting terminal, and an output terminal for outputting a comparison result to the first selector, and the second comparator includes an input terminal for receiving data output from the first transmitting terminal, and an output terminal for outputting a comparison result to the first selector; The second selector comprises a first input terminal for receiving data output from the second data receiving terminal, a second input terminal for receiving output data of the third comparator, and a third input terminal for receiving output data of the fourth comparator, and an output terminal for outputting data to the second data receiving module; The third comparator includes an input terminal for receiving data output from the second transmitting end, and an output terminal for outputting a comparison result to the second selector, and the fourth comparator includes an input terminal for receiving data output from the second transmitting end, and an output terminal for outputting a comparison result to the second selector.

4. The system according to claim 3, characterized in that The first selector selects the first comparator to judge the data output from the second output terminal of the first data sending module when it is determined that the input data of the first input terminal of the first selector is a first specified value, and selects the second comparator to judge the data output from the second output terminal of the first data sending module when it is determined that the input data of the first input terminal of the first selector is a second specified value; When the second selector determines that the input data of the first input terminal of the second selector is a first specified value, the second selector judges the data output from the second output terminal of the second data sending module through the third comparator; and when the second selector determines that the input data of the first input terminal of the second selector is a second specified value, the second selector judges the data output from the second output terminal of the second data sending module through the fourth comparator.

5. The system according to any one of claims 1 to 4, characterized in that: The system further comprises a first bit delay module and a second bit delay module, wherein an output end of the first bit delay module is connected to a first input end of the first selector, and is used to synchronize signals received by the first input end and the second input end of the first selector; The output end of the second bit delay module is connected to the second input end of the second selector, and is used to synchronize the signals received by the first input end and the second data end of the second selector.

6. The system according to any one of claims 2 to 4, characterized in that: The first data sending module further includes a first data buffer module, the output end of the first data buffer module is connected to the input end of the first data sending end, and is used to cache data to be sent to the first data sending end; The first data receiving module also includes a second data buffer module and a first receiving end, the input end of the second data buffer module is connected to the output end of the first signal selector, and is used to cache the output data of the first signal selector, the output end of the second data buffer module is connected to the first receiving end, and the first receiving end is used to send the output data of the second data buffer module to the first data control module; The second data sending module further includes a third data buffer module, the output end of the third data buffer module is connected to the input end of the second data sending end, and is used to cache data to be sent to the second data sending end; The second data receiving module also includes a fourth data buffer module and a second receiving end. The input end of the fourth data buffer module is connected to the output end of the second signal selector and is used to cache the output data of the second signal selector. The output end of the fourth data buffer module is connected to the second receiving end. The second receiving end is used to send the output data of the fourth data buffer module to the second data control module.

7. An electronic device, characterized in that: The electronic device comprises the real-time bidirectional data transmission system between chips according to any one of claims 1 to 6.

8. A core particle, characterized in that The core particle comprises the real-time bidirectional data transmission system between chips as described in any one of claims 1 to 6.

9. A chip, characterized in that: The chip comprises the real-time bidirectional data transmission system between chips as described in any one of claims 1 to 6.

10. An integrated circuit, characterized in that: The integrated circuit comprises the real-time bidirectional data transmission system between chips as claimed in any one of claims 1 to 6.

11. A method for real-time bidirectional data transmission between chips, characterized in that: The method is applied to a real-time bidirectional data transmission system between chips, and the method comprises: Determine the data sent by the first data sending module by using the first selector; When it is determined by the first selector that the data sent by the first data sending module is a first specified value, the first comparator is selected to judge the output data from the first sending end to obtain the data sent by the second sending end; and when it is determined by the first selector that the data sent by the first data sending module is a second specified value, the second comparator is selected to judge the output data from the first sending end to obtain the data sent by the second sending end.

12. The method according to claim 11, characterized in that When the data sent by the first data sending module is determined to be a first specified value by the first selector, selecting the first comparator to judge the output data from the first sending end to obtain the data sent by the second sending end includes: When the data sent by the first data sending module is determined to be a first specified value by the first selector, selecting a first comparator matching the first specified value; The output data from the first transmitting end is judged by the first comparator to obtain the data sent by the second transmitting end.

13. A real-time bidirectional data transmission device between chips, characterized in that: The device is applied to a real-time bidirectional data transmission system between chips, comprising: a determination module, configured to determine data sent by the first data sending module through the first selector; A selection module is used to select the first comparator to judge the output data from the first sending end to obtain the data sent by the second sending end when the data sent by the first data sending module is determined to be a first specified value through the first selector; and to select the second comparator to judge the output data from the first sending end to obtain the data sent by the second sending end when the data sent by the first data sending module is determined to be a second specified value through the first selector.

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