Abnormality processing method of system-on-chip, system-on-chip and microcontroller
By receiving and analyzing the PWM signals sent by the SOC, determining the SOC operation abnormality, the problem of low accuracy of monitoring SOC operation abnormality in the vehicle is solved, and timely repair and system stability are achieved.
Patent Information
- Application Number
- CN202311034534.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-16
- Publication Date
- 2025-02-21
AI Technical Summary
In vehicles, the operating abnormality monitoring of the system-on-chip SOC is low, resulting in the inability to repair in time and reduce the stability of the system operation.
By receiving the pulse width transmitted by the SOC, the PWM signal is modulated, and when the accumulated time of the target PWM signal has not been received to reach the preset time, it is determined that the SOC runs abnormally. This method can detect the target PWM signal in real time when the SOC is started normally and count the cumulative time limit of the target PWM signal that has not been received continuously to ensure the accuracy of monitoring of the operation abnormality of the SOC.
Improve the accuracy of monitoring SOC operation exceptions, ensure that abnormalities can be repaired in time, and improve the stability of system operation.
Smart Images
Figure CN119493698A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of monitoring technology, and in particular, relates to an exception handling method of a system on chip, a system on chip, and a microcontroller. Background Art
[0002] With the rapid development of vehicle automation and intelligence, more complex control systems in vehicles (such as intelligent driving control systems and intelligent cockpit control systems) usually include both microcontroller units (MCU) and system-level chips / systems on chips (SOC). Among them, MCU has the characteristics of high security level, high real-time performance, and reliable operation, and SOC has the characteristics of high performance, high computing power, and strong processing capabilities. However, the reliability of SOC is poor, and it may fail to start or freeze during operation. Therefore, in order to ensure the stability of the system, it is crucial to ensure the stable operation of SOC.
[0003] At present, the MCU and SOC usually communicate with each other through interfaces such as Serial Peripheral Interface (SPI) and Universal Asynchronous Receiver / Transmitter (UART), so that the MCU can determine whether the SOC operates abnormally based on the communication results.
[0004] However, in the process of answering communications, communication packet loss is prone to occur, which will lead to low monitoring accuracy, and then lead to the inability to repair in time when an abnormality occurs, reducing the stability of system operation. Summary of the invention
[0005] The embodiments of the present application provide a method for handling an exception of a system on a chip, a system on a chip, and a microcontroller, which can ensure the accuracy of monitoring the operation abnormalities of the SOC, and can promptly repair the abnormalities when they occur, thereby improving the stability of the system operation.
[0006] In a first aspect, an embodiment of the present application provides an exception handling method for a system on chip, the method comprising:
[0007] Receiving a pulse width modulation (PWM) signal sent by a system on chip (SOC), wherein the PWM signal is a signal simulated through an input I / output O interface when the SOC is started normally;
[0008] When the accumulated time duration for which the target PWM signal is not received reaches a preset time duration, it is determined that the SOC is operating abnormally, and the target PWM signal is a PWM signal having a period within a preset period range.
[0009] In a possible implementation manner, before receiving the PWM signal sent by the SOC, the method further includes:
[0010] Controlling the SOC to power on, and obtaining the power-on time of the SOC;
[0011] Within the target time period after the power-on moment, when the number of times the target PWM signal is continuously received is less than a first preset number, it is determined that the SOC startup is abnormal.
[0012] In a possible implementation, before controlling the SOC to power on, the method further includes:
[0013] Configuring the pins of the SOC to obtain a first configuration pin, where the first configuration pin is used to control the SOC to start in a first startup mode;
[0014] The determining that the SOC startup is abnormal includes:
[0015] It is determined that the first starting mode is abnormal.
[0016] In a possible implementation manner, after determining that the first startup mode is abnormal, the method further includes:
[0017] When the number of consecutive exceptions in the first startup mode reaches a second preset number, the pin of the SOC is configured to obtain a second configuration pin, and the control of powering on the SOC is returned to execute, and the power-on time of the SOC is obtained. The second configuration pin is used to control the SOC to start according to the second startup mode, and the priority of the second startup mode is lower than that of the first startup mode.
[0018] In a possible implementation, the method further includes:
[0019] When it is determined that the SOC is operating abnormally and / or the SOC is starting abnormally, the method returns to executing the configuration of the pins of the SOC.
[0020] In a second aspect, an embodiment of the present application provides an exception handling method for a system on chip, the method comprising:
[0021] Simulating a PWM signal through an input / output interface, wherein the PWM signal is used by a microcontroller to monitor an operating state and / or a startup state of the SOC;
[0022] The PWM signal is sent to the microcontroller.
[0023] In a possible implementation, before obtaining the PWM signal through input / output simulation, the method further includes:
[0024] Identify the configuration pins and obtain the target configuration pins;
[0025] Determine a first target startup mode corresponding to the target configuration pin according to the correspondence between the configuration pin and the startup mode, wherein the first target startup mode is a startup mode for enabling the SOC to start normally;
[0026] Start according to the first target startup method.
[0027] In a possible implementation manner, starting according to the first target starting manner includes:
[0028] A function is loaded from a first storage medium corresponding to the first target startup mode.
[0029] In a possible implementation, there is a priority between the multiple startup modes, and after loading the function from the first storage medium corresponding to the first target startup mode, the method further includes:
[0030] In the case of normal startup and a second target startup mode having a higher priority than the first target startup mode, determining a second storage medium corresponding to the second target startup mode, wherein the second target startup mode is a startup mode that causes abnormal startup of the SOC;
[0031] Repair the second storage medium.
[0032] In a third aspect, an embodiment of the present application provides a microcontroller, the microcontroller comprising:
[0033] A receiving module, used for receiving a pulse width modulation (PWM) signal sent by a system on chip (SOC), wherein the PWM signal is a signal obtained by simulating an input I / output O when the SOC is started normally;
[0034] The first determination module is used to determine that the SOC is operating abnormally when the cumulative time duration for which the target PWM signal is not received reaches a preset time duration, and the target PWM signal is a PWM signal with a period within a preset period range.
[0035] In a fourth aspect, an embodiment of the present application provides a system on chip, the system on chip comprising:
[0036] A simulation module, used for simulating a PWM signal through an input / output interface, wherein the PWM signal is used by the microcontroller to monitor the operating state and / or the startup state of the SOC;
[0037] A sending module is used to send the PWM signal to the microcontroller.
[0038] In a fifth aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: a processor and a memory storing computer program instructions;
[0039] When the processor executes the computer program instructions, the method in any possible implementation method of the first aspect or the second aspect is implemented.
[0040] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, implement a method in any possible implementation method of the first aspect or the second aspect mentioned above.
[0041] In a seventh aspect, an embodiment of the present application provides a vehicle, the vehicle comprising at least one of the following:
[0042] A microcontroller as in any one of the embodiments of the third aspect;
[0043] A system on chip as in any one of the embodiments of the fourth aspect;
[0044] An electronic device as in any one of the embodiments of the fifth aspect;
[0045] A computer-readable storage medium as in any embodiment of the sixth aspect.
[0046] In the abnormality handling method of the system on chip of the embodiment of the present application, since the PWM signal is a signal obtained by simulating the input / output interface when the SOC is started normally, and the target PWM signal is a PWM signal whose period is within the preset period range, the target PWM signal can be simulated when the SOC is running normally, but the target PWM signal cannot be simulated when the SOC is running abnormally. That is, if the SOC outputs the target PWM signal normally, it can be determined that the SOC is running normally. If the SOC cannot output the target PWM signal normally, it can be determined that the SOC is running abnormally. In this way, the target PWM signal can be detected in real time when the SOC is started normally, and the cumulative time for which the target PWM signal has not been received continuously can be counted. When the cumulative time reaches the preset time, it is determined that the SOC is running abnormally, which can ensure the accuracy of monitoring the abnormal operation of the SOC, and can repair it in time when an abnormality occurs, thereby improving the stability of the system operation. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0048] Figure 1 It is a flowchart of an exception handling method for a system on a chip applied to a microcontroller provided in an embodiment of the present application;
[0049] Figure 2 It is a flowchart of an exception handling method for a system on chip applied to a system on chip provided by an embodiment of the present application;
[0050] Figure 3 It is a flowchart of an exception handling method of a system on chip provided in an embodiment of the present application;
[0051] Figure 4 It is a structural schematic diagram of a microcontroller provided in an embodiment of the present application;
[0052] Figure 5 is a schematic diagram of the structure of a system on a chip provided in an embodiment of the present application;
[0053] Figure 6 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0054] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.
[0055] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.
[0056] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0057] The following is an introduction to the terms that appear in the embodiments of the present application.
[0058] A system-on-chip (SOC) is a purpose-built integrated circuit that contains all the contents of a complete system with embedded software.
[0059] A microcontroller unit (MCU), also known as a single-chip microcomputer or a single-chip microcomputer, is a chip-level computer.
[0060] Pulse Width Modulation (PWM) is a technique that uses the digital output of a microprocessor to control analog circuits. The frequency of a PWM signal refers to the number of times the signal changes from a high level to a low level and then returns to a high level in one second. The period of a PWM signal is the time of a pulse signal. In other words, the frequency of a PWM signal is the number of periods of the PWM signal in one second.
[0061] As described in the background technology section, at present, the MCU and SOC usually communicate with each other through interfaces such as SPI and UART, so that the MCU can determine whether the SOC is operating abnormally based on the communication results. However, in the process of response communication, communication packet loss is prone to occur, and communication packet loss will lead to low monitoring accuracy, which will lead to the inability to repair in time when an abnormality occurs, reducing the stability of system operation. In addition, setting interfaces such as SPI and UART, and communicating with each other through interfaces such as SPI and UART will occupy system resources.
[0062] In addition, the operating status of the SOC can be monitored through monitoring software, and the SOC can be reset when abnormal SOC operation is detected.
[0063] However, the above two monitoring methods only monitor the running state of the SOC, but cannot monitor the startup state of the SOC, resulting in an inability to recover from the startup abnormality of the SOC, thereby reducing the stability of the system.
[0064] Thus, in order to solve the problems of the prior art, the embodiments of the present application provide an exception handling method of a system on chip, a system on chip, and a microcontroller. Among them, the exception handling method of the system on chip can be applied to a microcontroller MCU and a system on chip SOC. The MCU can be a monitoring device, and the SOC can be a monitored device. When the MCU is powered on, that is, after the MCU is started, the operating status of the SOC and whether the SOC is started normally can be monitored, and in the case of an SOC abnormality (including an operating abnormality and a startup abnormality), the stability of the system operation can be ensured by restarting the SOC.
[0065] The following is an introduction to the exception handling method of the on-chip system applied to the MCU provided in the embodiment of the present application.
[0066] Figure 1 FIG. 1 is a flow chart showing an exception handling method for an on-chip system of an MCU provided in an embodiment of the present application. Figure 1 As shown, the exception handling method of the system on chip provided in the embodiment of the present application includes the following steps:
[0067] S110, receiving a PWM signal sent by the SOC, where the PWM signal is a signal simulated through an I / O interface when the SOC is started normally;
[0068] S120 . When the accumulated time duration during which the target PWM signal is not received reaches a preset time duration, it is determined that the SOC is operating abnormally, and the target PWM signal is a PWM signal having a period within a preset period range.
[0069] In the abnormality handling method of the system on chip of the embodiment of the present application, since the PWM signal is a signal obtained by simulating the input / output interface when the SOC is started normally, and the target PWM signal is a PWM signal whose period is within the preset period range, the target PWM signal can be simulated when the SOC is running normally, but the target PWM signal cannot be simulated when the SOC is running abnormally. That is, if the SOC outputs the target PWM signal normally, it can be determined that the SOC is running normally. If the SOC cannot output the target PWM signal normally, it can be determined that the SOC is running abnormally. In this way, the target PWM signal can be detected in real time when the SOC is started normally, and the cumulative time for which the target PWM signal has not been received continuously can be counted. When the cumulative time reaches the preset time, it is determined that the SOC is running abnormally, which can ensure the accuracy of monitoring the abnormal operation of the SOC, and can repair it in time when an abnormality occurs, thereby improving the stability of the system operation.
[0070] The specific implementation methods of the above steps are introduced below.
[0071] In some embodiments, in S110, the SOC may include a pulse width modulation (PWM) module, and the PWM module may output a PWM signal. However, in actual situations, when the SOC is operating abnormally, the PWM module may continue to output a PWM signal. Therefore, in order to accurately monitor the operating state of the SOC based on the PWM signal, when the SOC is started normally, the PWM signal can be simulated through the input (Input, I) / output (Output, O) interface, and the PWM signal can be sent to the MCU. In this way, when the SOC is operating abnormally, the PWM signal can be guaranteed to be abnormal. That is, when the PWM signal is normal, it can be determined that the SOC is operating normally. Among them, the normal PWM signal can be that the period of the PWM signal is within a preset period range.
[0072] As an example, when the SOC is started normally, the SOC can simulate a PWM signal through an I / O interface and send the PWM signal to the MCU. The MCU can determine whether the SOC is operating normally according to whether it can receive a normal PWM signal.
[0073] In addition, since the SOC may include multiple I / O interfaces, simulating PWM signals through the I / O interfaces will not occupy additional system resources.
[0074] In some embodiments, in S120, the target PWM signal may be a PWM signal whose period is within a preset period range. That is, if the PWM signal is normal, the PWM signal may be a target PWM signal. The preset period range may be a period range in which the target PWM signal can fluctuate. In actual situations, if the SOC performs relatively complex calculations, it may affect the output of the PWM signal. Therefore, the preset period range may be set relatively loosely. For example, if the period of the PWM signal agreed upon between the SOC and the MCU is 100ms, the preset period range may be, for example, 60ms to 140ms.
[0075] As an example, the preset duration may be, for example, 1s, 2s, 3s, etc. If the period of the PWM signal agreed between the SOC and the MCU is 100ms, then ideally, the MCU can receive 10 periods of PWM signals within 1s, and the period of each PWM signal is 10ms. In actual situations, if the SOC performs relatively complex calculations, it may affect the output of the PWM signal. Therefore, if the MCU receives the target PWM signal within 1s, it can be determined that the SOC is operating normally. If the MCU does not receive the target PWM signal within 1s, it can be determined that the SOC is operating abnormally.
[0076] Based on this, in order to improve the stability of system operation, in some embodiments, after determining that the SOC is operating abnormally, the SOC may be reset, that is, the SOC may be restarted.
[0077] Based on this, in order to accurately determine whether the SOC is started normally, in some embodiments, before the above S110, the following steps may also be included:
[0078] Control SOC power-on and obtain SOC power-on time;
[0079] Within the target time period after the power-on moment, when the number of times the target PWM signal is continuously received is less than the first preset number, it is determined that the SOC startup is abnormal.
[0080] Here, the MCU can control the power-on time of the SOC by controlling the power switch of the SOC. In addition, the target duration can be a duration related to the startup duration of the SOC, and the target duration can be greater than the startup duration of the SOC. For example, if the startup duration of the SOC is n, the target duration can be 2n. In addition, the first preset number of times can be a preset critical number of consecutive receptions of the target PWM signal. The first preset number of times can be, for example, 3 times, 4 times, 5 times, etc.
[0081] As an example, within the target time after power-on, if the number of consecutive receptions of the target PWM signal is less than the first preset number, it can be determined that the SOC starts abnormally. If the number of consecutive receptions of the target PWM signal is not less than the first preset number, it can be determined that the SOC starts normally.
[0082] In actual situations, if the SOC starts normally, the target PWM signal can be output to the MCU immediately after the SOC starts successfully. In this way, by making the target duration greater than the startup duration, the SOC can be given a buffer time, thereby accurately determining whether the SOC starts normally.
[0083] Based on this, in order to improve the stability of system operation, in some embodiments, after determining that the SOC startup is abnormal, the SOC may be reset, that is, the SOC may be restarted.
[0084] In addition, the SOC can be started in a variety of ways. Based on this, in order to accurately locate the abnormality when the SOC is abnormally started, in some embodiments, before the above-mentioned control of the SOC powering on, it may also include:
[0085] The pin of the SOC is configured to obtain a first configuration pin, where the first configuration pin is used to control the SOC to start in a first startup mode;
[0086] Determine SOC startup abnormality, including:
[0087] It is determined that the first startup mode is abnormal.
[0088] Here, there may be a one-to-one correspondence between the startup mode and the configuration pin. In addition, the startup durations of different startup modes may be different, so the target duration may change with the change of the startup mode.
[0089] As an example, the MCU can control the startup mode of the SOC. Specifically, the MCU can configure the pins of the SOC to obtain a first configuration pin. After the MCU controls the SOC to power on, the SOC can determine the first configuration pin by identifying the configuration pin, and determine the first startup mode corresponding to the first configuration pin according to the correspondence between the configuration pin and the startup mode. Then, the SOC can be started according to the first startup mode. In this way, if it is determined that the SOC startup is abnormal, it can be determined that the first startup mode is abnormal. If it is determined that the SOC starts normally, it can be determined that the first startup mode is normal.
[0090] In this way, by controlling the startup mode of the SOC, the abnormality can be accurately located when the SOC startup is abnormal.
[0091] Based on this, in order to ensure that the SOC starts normally and thus ensure the stability of the system operation, in some embodiments, after determining that the first startup mode is abnormal, the following steps may also be included:
[0092] When the number of consecutive exceptions in the first startup mode reaches a second preset number, the pin of the SOC is configured to obtain a second configuration pin, and the execution is returned to control the SOC to power on, and the power-on time of the SOC is obtained. The second configuration pin is used to control the SOC to start according to the second startup mode. The priority of the second startup mode is lower than that of the first startup mode.
[0093] Here, the second preset number of times may be a preset critical number of consecutive abnormalities of the first startup mode. The second preset number of times may be, for example, 3 times, 4 times, 5 times, etc. If the number of consecutive abnormalities of the first startup mode is less than the second preset number of times, the SOC may continue to be started in accordance with the first startup mode. If the number of consecutive abnormalities of the first startup mode is not less than the second preset number of times, it may be determined that the SOC cannot be started normally by the first startup mode. Therefore, in order to ensure that the SOC starts normally, the SOC may be controlled to start in accordance with the second startup mode by configuring the second configuration pin. Among them, the priority of the second startup mode is lower than the priority of the first startup mode. That is, the MCU may determine the startup mode of the SOC in order from high to low priority.
[0094] As an example, the startup method may include startup through EMMC (Embedded Multi Media Card) and startup through NOR flash (non-volatile flash memory technology). Among them, EMMC and NOR flash may be storage media, and the storage medium may store codes corresponding to functions. The startup of SOC through EMMC may be that SOC loads functions from EMMC. The startup of SOC through NOR flash may be that SOC loads functions from NOR flash. Since the storage capacity in EMMC may be greater than the storage capacity in NOR flash, the functions stored in EMMC may be more than the functions stored in NOR flash, and therefore, the priority of startup through EMMC may be higher than the priority of startup through NOR flash. Therefore, the first startup method may be startup through EMMC. The second startup method may be startup through NOR flash.
[0095] In this way, by controlling the SOC to start in the second starting mode when the first starting mode is abnormal, it is possible to ensure that the SOC starts normally, thereby ensuring the stability of system operation.
[0096] Based on this, in order to ensure the stability of system operation, in some embodiments, the following steps may also be included:
[0097] When it is determined that the SOC is operating abnormally and / or the SOC is starting abnormally, the process returns to configure the pins of the SOC.
[0098] Here, after determining that the SOC is abnormal, the MCU can first configure the pins of the SOC, determine the startup mode of the SOC, and then control the SOC to power on, so that the SOC can start according to the startup mode determined by the MCU (i.e. restart the SOC). After that, the MCU can monitor whether the SOC starts normally. In the case of abnormal startup of the SOC, the pins of the SOC can be configured and the above steps can be repeated. In the case of normal startup of the SOC, the MCU can continue to monitor the operating status of the SOC. If the SOC runs abnormally, the pins of the SOC can be configured and the above steps can be repeated.
[0099] In this way, by controlling the startup mode and power-on sequence of the SOC during system operation and continuously monitoring the startup and operation abnormalities of the SOC, the abnormalities can be repaired as soon as they occur, that is, the SOC can be restarted, thereby ensuring the stability of the system operation.
[0100] The following is an introduction to the exception handling method for the system on chip applied to the SOC provided in the embodiment of the present application.
[0101] Figure 2 FIG. 1 is a flow chart showing an exception handling method for a system-on-chip (SOC) provided in an embodiment of the present application. Figure 2 As shown, the exception handling method of the system on chip provided in the embodiment of the present application includes the following steps:
[0102] S210, simulating a PWM signal through an input / output interface, where the PWM signal is used by the microcontroller to monitor the operating state and / or the startup state of the SOC;
[0103] S220, sending a PWM signal to the microcontroller.
[0104] In the exception handling method of the system on chip of the embodiment of the present application, since the SOC may include multiple I / O interfaces, simulating the PWM signal through the I / O interface will not occupy additional system resources. In addition, since the PWM module may continue to output the PWM signal when the SOC is operating abnormally, simulating the PWM signal through the I / O interface and sending the PWM signal to the MCU, relative to outputting the PWM signal through the PWM module, enables the MCU to receive the target PWM signal when the SOC is operating normally, but cannot receive the target PWM signal when the SOC is operating abnormally, thereby ensuring the accuracy of the MCU's monitoring of the operating status of the SOC based on the PWM signal.
[0105] The steps of the method in the embodiment of the present application can be seen above Figure 1 The relevant description of the illustrated embodiment will not be repeated here.
[0106] Based on this, in order to enable the MCU to accurately locate the abnormality when the SOC is abnormally started, in some embodiments, before the above S210, the following may also be included:
[0107] Identify the configuration pins and obtain the target configuration pins;
[0108] Determine a first target startup mode corresponding to the target configuration pin according to the corresponding relationship between the configuration pin and the startup mode, the first target startup mode being a startup mode for enabling the SOC to start normally;
[0109] Start according to the first target startup method.
[0110] Here, there can be a one-to-one correspondence between the startup mode and the configuration pins.
[0111] As an example, the MCU can control the startup mode of the SOC. Specifically, the MCU can configure the pins of the SOC. After the MCU controls the SOC to power on, the SOC can identify the configuration pins, determine the first target startup mode corresponding to the configuration pins, and start according to the first target startup mode. In this way, if it is determined that the SOC startup is abnormal, the MCU can determine that the first target startup mode is abnormal. If it is determined that the SOC starts normally, the MCU can determine that the first target startup mode is normal. In addition, after the SOC starts normally, the PWM signal can be simulated through the I / O interface. In an embodiment of the present application, since the SOC can simulate the PWM signal through the I / O interface, the first target startup mode can be a startup mode that enables the SOC to start normally.
[0112] In addition, in some embodiments, the above-mentioned starting in accordance with the first target starting mode may specifically include:
[0113] The function is loaded from a first storage medium corresponding to the first target startup mode.
[0114] Here, if the first target startup mode is startup through EMMC, startup through EMMC may be loading functions from EMMC. If the first target startup mode is startup through NOR flash, startup through NOR flash may be loading functions from NOR flash.
[0115] In this way, the SOC is started according to the startup mode configured by the MCU, so that the MCU can accurately locate the abnormality when the SOC starts abnormally.
[0116] In addition, there may be priorities between multiple startup methods. Starting the SOC according to a startup method with a higher priority can improve the performance of the SOC. For example, since the storage capacity in the EMMC can be greater than the storage capacity in the NOR flash, the functions stored in the EMMC can be more than the functions stored in the NOR flash. Therefore, the priority of starting through the EMMC can be higher than the priority of starting through the NOR flash. Based on this, starting through the EMMC can enable the SOC to load more functions than starting through the NOR flash, thereby improving the performance of the SOC. Therefore, in the case where the SOC is started through the NOR flash, in order to ensure the performance of the SOC, more functions can be loaded through other methods.
[0117] Based on this, in order to improve the performance of the SOC, in some embodiments, after the function is loaded from the first storage medium corresponding to the first target startup mode, the following may also be included:
[0118] In the case of normal startup, and the priority of the second target startup mode is higher than the priority of the first target startup mode, determining a second storage medium corresponding to the second target startup mode, the second startup mode being a startup mode that causes abnormal startup of the SOC;
[0119] Repair the second storage medium.
[0120] Here, the MCU can determine the startup mode of the SOC in order from high to low priority. Since the priority of the second target startup mode is higher than that of the first target startup mode, the SOC can first be started according to the second target startup mode, and then started according to the first target startup mode in the case of abnormal startup. Therefore, if the SOC is started according to the first target startup mode, it can be determined that the second target startup mode is abnormal. Therefore, after the SOC is normally started according to the first target startup mode, the second storage medium can be repaired so that it can be started according to the second target startup mode at the next restart. Specifically, the SOC can repair the second storage medium by calling a repair command. Among them, the second target startup mode can be one or more, which is not limited here. Correspondingly, the second storage medium can be one or more, which is not limited here.
[0121] As an example, if the first target startup mode is to start through NOR flash, since the priority of starting through EMMC is higher than the priority of starting through NOR flash, the EMMC can be repaired when the SOC starts normally.
[0122] In this way, by repairing the second storage medium, the SOC can be started according to the second target startup mode when it is restarted next time, thereby improving the performance of the SOC.
[0123] In addition, during the process of the SOC repairing the second storage medium, since the calculation of the SOC is relatively complex, the output of the PWM signal may be affected. That is, during the process of the SOC repairing the second storage medium, the MCU may not receive the target PWM signal. Therefore, during the process of the SOC repairing the second storage medium, the MCU may not monitor the operating state of the SOC.
[0124] In order to better describe the entire solution, some specific examples are given based on the above embodiments.
[0125] For example, Figure 3 As shown, the exception handling method of the system on chip provided in the embodiment of the present application may include the following steps:
[0126] S31, MCU starts;
[0127] S32, MCU sets the SOC startup mode to start through EMMC;
[0128] S33, MCU controls SOC to power on;
[0129] S34, MCU monitors the startup of SOC;
[0130] S35, MCU determines whether the SOC is abnormally started, if not, execute S36, if yes, execute S38;
[0131] S36, MCU monitors the operating status of SOC;
[0132] S37, MCU determines whether the SOC is operating abnormally, if not, execute S36, if yes, execute S32;
[0133] S38, MCU determines whether the SOC startup abnormality reaches 3 times, if so, execute S39, if not, execute S32;
[0134] S39, MCU sets the SOC startup mode to start through NOR flash;
[0135] S310, MCU controls SOC to power on;
[0136] S311, SOC repairs EMMC.
[0137] Therefore, by monitoring the startup and running status of the SOC through the MCU, it can be repaired in time when an abnormality occurs in the SOC, thereby improving the operating stability of the entire system.
[0138] Based on the exception handling method of the system on chip provided in the above embodiment, the present application also provides a specific implementation of the microcontroller. Please refer to the following embodiment.
[0139] like Figure 4 As shown, the microcontroller 400 provided in the embodiment of the present application includes the following modules:
[0140] The receiving module 410 is used to receive a pulse width modulation (PWM) signal sent by the system on chip (SOC). The PWM signal is a signal obtained by simulating the input I / output O when the SOC is started normally.
[0141] The first determination module 420 is used to determine that the SOC is operating abnormally when the cumulative duration of not receiving the target PWM signal reaches a preset duration, and the target PWM signal is a PWM signal with a period within a preset period range.
[0142] The microcontroller 400 is described in detail below, as shown below:
[0143] In some embodiments, the microcontroller 400 may further include:
[0144] The control module is used to control the SOC to power on and obtain the power-on time of the SOC before receiving the PWM signal sent by the SOC;
[0145] The second determination module is used to determine that the SOC startup is abnormal when the number of times the target PWM signal is continuously received is less than a first preset number within a target time period after the power-on moment.
[0146] In some embodiments, the microcontroller 400 may further include:
[0147] A configuration module, used for configuring the pins of the SOC before controlling the SOC to power on, to obtain a first configuration pin, wherein the first configuration pin is used for controlling the SOC to start in a first startup mode;
[0148] Based on this, the second determination module may specifically include:
[0149] The first determining submodule is used to determine whether the first starting mode is abnormal.
[0150] In some embodiments, the second determining module may further include:
[0151] The configuration submodule is used to configure the pins of the SOC to obtain the second configuration pins after determining that the first startup mode is abnormal and when the number of consecutive abnormalities in the first startup mode reaches a second preset number, and return to execute the control of SOC power-on and obtain the power-on time of the SOC. The second configuration pins are used to control the SOC to start according to the second startup mode, and the priority of the second startup mode is lower than that of the first startup mode.
[0152] In some embodiments, the microcontroller 400 may further include:
[0153] The execution module is used to return to execute the configuration of the pins of the SOC when it is determined that the SOC is running abnormally and / or the SOC is starting abnormally.
[0154] In the microcontroller of the embodiment of the present application, since the PWM signal is a signal obtained by simulating the I / O interface when the SOC is started normally, and the target PWM signal is a PWM signal whose period is within the preset period range, the target PWM signal can be simulated when the SOC is running normally, but the target PWM signal cannot be simulated when the SOC is running abnormally. In this way, by determining that the SOC is running abnormally when the SOC is started normally and the cumulative time for not receiving the target PWM signal reaches the preset time, compared with determining whether the SOC is running abnormally through response communication, the accuracy of monitoring can be improved, and then timely repair can be made when an abnormality occurs, thereby improving the stability of system operation.
[0155] Based on the exception handling method of the system on chip provided in the above embodiment, the present application also provides a specific implementation of the system on chip. Please refer to the following embodiment.
[0156] like Figure 5 As shown, the system on chip 500 provided in the embodiment of the present application includes the following modules:
[0157] The simulation module 510 is used to simulate a PWM signal through an input / output interface, and the PWM signal is used by the microcontroller to monitor the operating state and / or the startup state of the SOC;
[0158] The sending module 520 is used to send a PWM signal to the microcontroller.
[0159] In some embodiments, the system on chip 500 may further include:
[0160] An identification module is used to identify the configuration pins and obtain the target configuration pins before obtaining the PWM signal through input / output simulation;
[0161] A third determination module is used to determine a first target startup mode corresponding to the target configuration pin according to the correspondence between the configuration pin and the startup mode, wherein the first target startup mode is a startup mode for enabling the SOC to start normally;
[0162] The startup module is used to start the system in accordance with the first target startup mode.
[0163] In some embodiments, the startup module may specifically include:
[0164] The loading submodule is used to load functions from a first storage medium corresponding to the first target startup mode.
[0165] In some embodiments, there are priorities among the multiple startup modes. Based on this, the startup module may further include:
[0166] a second determination submodule, configured to, after loading the function from the first storage medium corresponding to the first target startup mode, determine a second storage medium corresponding to a second target startup mode in a case where the startup is normal and the priority of the second target startup mode is higher than the priority of the first target startup mode, the second target startup mode being a startup mode that causes the SOC startup to be abnormal;
[0167] The repair submodule is used to repair the second storage medium.
[0168] In the system on chip of the embodiment of the present application, since the PWM signal is a signal obtained by simulating the input / output interface when the SOC is started normally, and the target PWM signal is a PWM signal whose period is within the preset period range, the target PWM signal can be simulated when the SOC is running normally, but the target PWM signal cannot be simulated when the SOC is running abnormally. That is, if the SOC outputs the target PWM signal normally, it can be determined that the SOC is running normally. If the SOC cannot output the target PWM signal normally, it can be determined that the SOC is running abnormally. In this way, the target PWM signal can be detected in real time when the SOC is started normally, and the cumulative time for which the target PWM signal has not been received continuously can be counted. When the cumulative time reaches the preset time, it is determined that the SOC is running abnormally, which can ensure the accuracy of monitoring the abnormal operation of the SOC, and can repair it in time when the abnormality occurs, thereby improving the stability of the system operation.
[0169] Based on the exception handling method of the system on chip provided in the above embodiment, the embodiment of the present application also provides a specific implementation of the electronic device. Figure 6 A schematic diagram of an electronic device 600 provided in an embodiment of the present application is shown.
[0170] The electronic device 600 may include a processor 610 and a memory 620 storing computer program instructions.
[0171] Specifically, the processor 610 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.
[0172] The memory 620 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 620 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 620 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 620 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 620 is a non-volatile solid-state memory.
[0173] The memory may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium device, an optical storage medium device, a flash memory device, an electrical, optical or other physical / tangible memory storage device. Thus, typically, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to the first aspect of the present application.
[0174] The processor 610 implements any one of the exception handling methods of the system on chip in the above embodiments by reading and executing computer program instructions stored in the memory 620 .
[0175] In one example, the electronic device 600 may further include a communication interface 630 and a bus 640. Figure 6 As shown, the processor 610, the memory 620, and the communication interface 630 are connected via a bus 640 and communicate with each other.
[0176] The communication interface 630 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.
[0177] Bus 640 includes hardware, software or both, and the parts of electronic equipment are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 640 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the application considers any suitable bus or interconnection.
[0178] Exemplarily, the electronic device 600 may be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA).
[0179] The electronic device can execute the exception handling method of the system on chip in the embodiment of the present application, thereby realizing the combination Figures 1 to 5 The invention discloses an exception handling method of a system on chip, a system on chip and a microcontroller.
[0180] In addition, in combination with the exception handling method of the system on chip in the above embodiments, the embodiment of the present application can provide a computer-readable storage medium for implementation. The computer-readable storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any one of the exception handling methods of the system on chip in the above embodiments is implemented.
[0181] In addition, the embodiment of the present application further provides a vehicle, which may include at least one of the following:
[0182] A microcontroller as in any one of the embodiments of the third aspect;
[0183] A system on chip as in any one of the embodiments of the fourth aspect;
[0184] An electronic device as in any one of the embodiments of the fifth aspect;
[0185] Such as the computer-readable storage medium in any embodiment of the sixth aspect. No further description will be given here.
[0186] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.
[0187] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.
[0188] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.
[0189] The above reference is according to the method of the embodiment of the present application, the flow chart of the device (system) and the computer program product and / or the block diagram described various aspects of the present application.It should be understood that each square box in the flow chart and / or the block diagram and the combination of each square box in the flow chart and / or the block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the realization of the function / action specified in one or more square boxes of the flow chart and / or the block diagram.Such a processor can be but is not limited to a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit.It can also be understood that each square box in the block diagram and / or the flow chart and the combination of the square boxes in the block diagram and / or the flow chart can also be realized by the dedicated hardware that performs the specified function or action, or can be realized by the combination of dedicated hardware and computer instructions.
[0190] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.
Claims
1. A method for handling exceptions in a system on chip, characterized in that: include: Receiving a pulse width modulation (PWM) signal sent by a system on chip (SOC), wherein the PWM signal is a signal simulated through an input / output interface when the SOC is started normally; When the accumulated time duration for which the target PWM signal is not received reaches a preset time duration, it is determined that the SOC is operating abnormally, and the target PWM signal is a PWM signal having a period within a preset period range.
2. The method according to claim 1, characterized in that Before receiving the PWM signal sent by the SOC, the method further includes: Controlling the SOC to power on, and obtaining the power-on time of the SOC; Within the target time period after the power-on moment, when the number of times the target PWM signal is continuously received is less than a first preset number, it is determined that the SOC startup is abnormal.
3. The method according to claim 2, characterized in that Before controlling the SOC to power on, the method further includes: Configuring the pins of the SOC to obtain a first configuration pin, where the first configuration pin is used to control the SOC to start in a first startup mode; The determining that the SOC startup is abnormal includes: It is determined that the first starting mode is abnormal.
4. The method according to claim 3, characterized in that After determining that the first startup mode is abnormal, the method further includes: When the number of consecutive exceptions in the first startup mode reaches a second preset number, the pin of the SOC is configured to obtain a second configuration pin, and the control of powering on the SOC is returned to execute, and the power-on time of the SOC is obtained. The second configuration pin is used to control the SOC to start according to the second startup mode, and the priority of the second startup mode is lower than that of the first startup mode.
5. The method according to claim 3, characterized in that: The method further comprises: When it is determined that the SOC is operating abnormally and / or the SOC is starting abnormally, the method returns to executing the configuration of the pins of the SOC.
6. A method for handling exceptions in a system on chip, characterized in that: include: Simulating a PWM signal through an input / output interface, wherein the PWM signal is used by a microcontroller to monitor an operating state and / or a startup state of the SOC; The PWM signal is sent to the microcontroller.
7. The method according to claim 6, characterized in that Before obtaining the PWM signal through the input / output interface simulation, the method further includes: Identify the configuration pins and obtain the target configuration pins; Determine a first target startup mode corresponding to the target configuration pin according to the correspondence between the configuration pin and the startup mode, wherein the first target startup mode is a startup mode for enabling the SOC to start normally; Start according to the first target startup method.
8. The method according to claim 7, characterized in that The starting according to the first target starting mode includes: A function is loaded from a first storage medium corresponding to the first target startup mode.
9. The method according to claim 8, characterized in that There are priorities among the multiple startup modes. After loading the function from the first storage medium corresponding to the first target startup mode, the method further includes: In the case of normal startup and a second target startup mode having a higher priority than the first target startup mode, determining a second storage medium corresponding to the second target startup mode, wherein the second target startup mode is a startup mode that causes abnormal startup of the SOC; Repair the second storage medium.
10. A microcontroller, characterized in that: The microcontroller comprises: A receiving module, used for receiving a pulse width modulation (PWM) signal sent by a system on chip (SOC), wherein the PWM signal is a signal obtained by input / output simulation when the SOC is started normally; The first determination module is used to determine that the SOC is operating abnormally when the cumulative time duration for which the target PWM signal is not received reaches a preset time duration, and the target PWM signal is a PWM signal with a period within a preset period range.
11. A system on chip, characterized in that: The system on chip comprises: A simulation module, used for simulating a PWM signal through an input / output interface, wherein the PWM signal is used by the microcontroller to monitor the operating state and / or the startup state of the SOC; A sending module is used to send the PWM signal to the microcontroller.
12. An electronic device, characterized in that: The electronic device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the exception handling method of the system on chip is implemented as described in any one of claims 1-5 or 6-9.
13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by the processor, the exception handling method of the system on chip as described in any one of claims 1-5 or 6-9 is implemented.
14. A vehicle, characterized in that: Include at least one of the following: The microcontroller as claimed in claim 10; The system on chip as claimed in claim 11; The electronic device as claimed in claim 12; The computer readable storage medium of claim 13.