FPGA of parallel FFT, electronic equipment and design method
By designing parallel FFT FPGAs in FPGAs, and FFT data processing is performed through the combination of serial and parallel modules, the problems of low efficiency and high resource consumption of existing FFT IP cores are solved, real-time processing and efficient full-bandwidth data are achieved. Data throughput.
Patent Information
- Application Number
- CN202311028023.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-15
- Publication Date
- 2025-02-21
AI Technical Summary
FPGA's existing FFT IP cores are inefficient and cannot meet the needs of high-performance applications. They consume a lot of resources and cannot process full bandwidth data in real time.
Design a parallel FFT FPGA, by splitting the algorithm module into a serial module and a parallel module, the serial module performs butterfly operation to obtain the first calculation result, and then use the parallel module to perform parallel processing to output the second corresponding number of paths. The calculation result completes the conversion of FFT data.
The real-time processing of FPGAs for full bandwidth data is completed without the need to develop a dedicated FFT module, which reduces resource utilization, improves data throughput and algorithm efficiency, and makes FPGAs suitable for high-performance applications.
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Figure CN119493764A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of digital signal processing in optical communication, and in particular to a parallel FFT (fast Fourier transform) FPGA (Field Programmable Gate Array), electronic equipment and design method. Background Art
[0002] In the actual engineering of digital signal processing in optical communication, Fourier transform has been used in FPGA cores, and mature FFT IP (Intellectual Property) cores are available. With the increase of AD (analogue-to-digital) sampling rate, FPGA cannot process full bandwidth data in real time; in related technologies, the internal FPGA can use a phase-splitting method to reduce the processing speed, that is, using serial-to-parallel conversion.
[0003] However, in some high-performance applications, the classic IP core cannot meet the application requirements and requires the separate development of a dedicated FFT module, which has low efficiency, high cost, and a narrow adaptation range and cannot meet the needs of actual use. Summary of the invention
[0004] The present application provides an FFT FPGA, an electronic device and a design method to solve the problems in the related art, such as low working efficiency of the FPGA IP core, low adaptability to high-performance applications, and high resource consumption.
[0005] The first aspect of the present application provides an FFT FPGA, comprising: one or more serial modules, wherein each serial module comprises a plurality of serial sub-modules, each serial sub-module performs a butterfly operation on FFT data of a fast Fourier transform FFT to obtain a first operation result; a parallel module, wherein the parallel module comprises one or more parallel sub-modules, the first operation result output by each serial sub-module of the serial module is input to the input end of the corresponding parallel sub-module, the parallel sub-module performs a butterfly operation on each first operation result in parallel, and outputs a second operation result of a corresponding number of paths, so as to convert the FFT data into data of a corresponding number of paths.
[0006] Optionally, the serial submodule is provided with first to third level operation units, wherein the first level operation unit is used to delay the original data sequence of the FFT data by a first moment and perform time domain interpolation with the original data sequence to obtain a first data sequence; the second level operation unit is used to delay the first data sequence by a second moment and perform time domain interpolation with the first data sequence to obtain a second data sequence; the third level operation unit is used to delay the second data sequence by a third moment and perform time domain interpolation with the second data sequence to obtain a first operation result.
[0007] Optionally, the first to third level operation units share register delay.
[0008] Optionally, the parallel submodule includes fourth to eighth level operation units, wherein the fourth level operation unit and the seventh level operation unit share a register, and the fifth level operation unit, the sixth level operation unit and the eighth level operation unit share a register.
[0009] Optionally, the serial submodule includes a first number of input terminals, the parallel submodule includes a second number of input terminals, and each of the serial modules includes a second number of serial submodules.
[0010] Optionally, the first operation result includes elements of a first way number, and the second operation result includes elements of a product of the first way number and the second way number.
[0011] Optionally, a rotation factor multiplication unit is further arranged between the serial submodule and the parallel submodule, and the rotation factor multiplication unit provides a first FFT rotation factor.
[0012] Optionally, the parallel algorithm of the parallel submodule is:
[0013]
[0014] in, is the mth row and lth column subcarrier, N1 is the number of rows, N2 is the number of columns, N=N1*2, is the row FFT rotation factor, q ranges from 0 to (N1-1) (integral of the number of rows), is the original signal in the time domain, is the rotation factor corresponding to the position of the target frequency domain, The column FFT rotation factor provided for the parallel submodule body, r is from 0 to (N2-1) (column integral); m and l are the positions of the corresponding elements in the matrix space; N1-point DFTs represents N1-point DFT, and N2-point DFTs represents N2-point DFT.
[0015] A second aspect of the present application provides an electronic device, comprising an FPGA for parallel FFT as described in the above embodiment.
[0016] A third aspect of the present application provides a method for designing an FPGA for parallel FFT, the method being used for designing an FPGA for parallel FFT as described in the above-mentioned embodiment, wherein the method comprises the following steps: obtaining the algorithm principle of the parallel algorithm of the field programmable gate array FPGA; splitting the module executing the parallel algorithm into a serial module and a parallel module according to the conversion target of the FFT data of the fast Fourier transform FFT and the algorithm principle, wherein each serial module comprises a plurality of serial sub-modules, each serial sub-module performs a butterfly operation on the FFT data of the fast Fourier transform FFT to obtain a first operation result; the parallel module comprises one or more parallel sub-modules, the first operation result output by each serial sub-module of the serial module is input to the input end of the corresponding parallel sub-module, the parallel sub-module performs a parallel processing of the butterfly operation on each first operation result, and outputs a second operation result of a corresponding number of paths, so as to convert the FFT data into data of a corresponding number of paths.
[0017] Therefore, the present application can split the FPGA algorithm module into serial and parallel modules, perform butterfly operation through the serial module to obtain a first operation result, and then use the parallel module to process the first operation result to obtain a second operation result, thereby completing the conversion of FFT data to corresponding path data; therefore, the embodiment of the present application does not need to develop a dedicated FFT module to complete the real-time processing of full-bandwidth data by FPGA, while ensuring high speed and reducing resource utilization, thereby improving data throughput and algorithm efficiency, thereby increasing the scope of application of FPGA for high-performance applications and meeting actual usage needs.
[0018] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0020] Figure 1 A schematic diagram of the recursive partitioning process of an 8-point DFT (Discrete Fourier Transform) in the related art of the embodiment of the present application;
[0021] Figure 2 A schematic diagram of an 8-point butterfly algorithm in the related technology of the embodiment of the present application;
[0022] Figure 3A schematic diagram of the structure of the FPGA of the parallel FFT of the embodiment of the present application;
[0023] Figure 4 A flow chart of the 32-way parallel algorithm design for an embodiment of the present application;
[0024] Figure 5 This is a schematic diagram of an 8-point serial algorithm according to an embodiment of the present application;
[0025] Figure 6 A schematic diagram of a 32-point parallel algorithm according to an embodiment of the present application;
[0026] Figure 7 It is a 16QAM (Quadrature Amplitude Modulation) constellation diagram of an embodiment of the present application;
[0027] Figure 8 A schematic diagram of resource usage in an embodiment of the present application;
[0028] Fig. 9 The flowchart of the FPGA design method of the parallel FFT according to the embodiment of the present application. DETAILED DESCRIPTION
[0029] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.
[0030] In the related technology, in the actual engineering of digital signal processing in optical communication, the implementation of Fourier transform in FPGA has mature FFT IP cores available for use; as the AD sampling rate becomes higher and higher, FPGA cannot process full-bandwidth data in real time, and phase splitting (that is, serial-to-parallel conversion) can be adopted inside the FPGA to reduce the processing speed; but in some high-performance applications, the classic IP core cannot meet the requirements, so a dedicated FFT module has to be developed.
[0031] For example, if you want to achieve a Fourier transform with a data throughput of 2 to 3Gsps, if you simply use the IP core, the working clock must be as high as 2 to 3GHz or above. One of the solutions for high-speed FFT design is to use a parallel approach. For example, a 256-point FFT uses 32 parallel inputs and parallel calculations, and the working clock frequency is 75MHz, so the data throughput can reach 2400Msps. The principle of the 32-channel 256-point time domain interpolation FFT algorithm is as follows:
[0032]
[0033] Among them, the rotation factor
[0034] Taking 8-point DFT as an example, the recursive partitioning process is as follows Figure 1 As shown in the figure, to do a DFT on the sequence [0 7], according to the principle of FFT, we only need to do DFT on [0,2,4,6] and [1,3,5,7]. To continue the division, we need to do DFT on [0,4][2,6][1,5][3,7]. Finally, we need to do single-point DFT on 0,4,2,6,1,5,3,7 respectively. Therefore, as long as we know the order of the numbers at the bottom layer, we can start the calculation from bottom to top layer by layer. Once we know the first layer, we don’t need to recurse.
[0035] For example, the binary numbers of the source sequence 04261537 are 000, 100, 010, 110, 001, 101, 011, 111. Inverting each number gives 000, 001, 010, 011, 100, 101, 110, 111, which is exactly 01234567. The same is true for other powers of 2. Therefore, the recursive step can be implemented through several layers of loops, such as the non-recursive algorithm (also known as the "butterfly" iterative algorithm).
[0036] Figure 2 The design diagram of the 8-way 8-point FFT algorithm for base 2 requires a total of three pipelines. Taking 256-point FFT as an example, if a full parallel solution is implemented, the required storage space is large (converting serial data streams to 256-way data is very resource-consuming).
[0037] In view of the problems in the above-mentioned background technology, the present application can propose an FPGA, electronic device and design method for parallel FFT. The FPGA, electronic device and design method for parallel FFT of the present application will be described below in combination with embodiments.
[0038] The following describes the FPGA of parallel FFT proposed according to the embodiment of the present application with reference to the accompanying drawings.
[0039] Figure 3 It is a block diagram of the FPGA of the parallel FFT of the embodiment of the present application.
[0040] like Figure 3 As shown, the parallel FFT FPGA 10 includes: a serial module 100 and a parallel module 200 .
[0041] Among them, the serial module 100 can be one or more, each serial module includes multiple serial sub-modules, and each serial sub-module performs a butterfly operation on the FFT data of the fast Fourier transform FFT to obtain a first operation result; the parallel module 200 includes one or more parallel sub-modules, and the first operation result output by each serial sub-module of the serial module is input to the input end of the corresponding parallel sub-module, and the parallel sub-module performs parallel processing of the butterfly operation on each first operation result, outputs the second operation result of the corresponding number of paths, and converts the FFT data into data of the corresponding number of paths.
[0042] It is understandable that if Figure 4 As shown, the embodiment of the present application can use one or more serial modules, each serial module also includes multiple serial sub-modules, wherein the serial module and the sub-module can be set according to the actual situation, and there is no specific limitation on this. For example, there can be two sub-modules of 32-way parallel and 8-way serial, etc.; the embodiment of the present application can also use a parallel module to implement a butterfly operation on the calculation results calculated by the serial module, and then output the corresponding calculation results.
[0043] Specifically, the serial submodule is provided with first to third level operation units, wherein the first level operation unit is used to delay the original data sequence of the FFT data by the first moment and perform time domain interpolation with the original data sequence to obtain a first data sequence; the second level operation unit is used to delay the first data sequence by the second moment and perform time domain interpolation with the first data sequence to obtain a second data sequence; the third level operation unit is used to delay the second data sequence by the third moment and perform time domain interpolation with the second data sequence to obtain a first operation result.
[0044] Among them, the first to third level operation units share register delay; the first operation result includes elements of the first path, and the second operation result includes elements of the product of the first path and the second path; the serial submodule includes the input end of the first path.
[0045] It can be understood that, taking the first 8-point serial module as an example, Figure 5 As shown, the sampling point of the input end of the first path is the sampling point [0 32 64 96 128 160 192 224] of the FFT data, which is divided into three-level operation units according to the radix-2 algorithm. The first level is to delay the original sequence by 4 time points and perform time domain interpolation with the original sequence, the second level is to delay the first level output sequence by 2 time points and perform time domain interpolation with the first level output, and the third level is to delay the second level output sequence by 1 time point and perform time domain interpolation with the second level output; wherein, the register delay can share the register, and only the input and output signals need to be selected to achieve the purpose of saving registers.
[0046] In an embodiment of the present application, the parallel submodule includes fourth to eighth level operation units, wherein the fourth level operation unit and the seventh level operation unit share registers, and the fifth level operation unit, the sixth level operation unit and the eighth level operation unit share registers.
[0047] The parallel submodule includes a second number of input terminals, and each serial module includes a second number of serial submodules.
[0048] It is understandable that the 32-way parallel submodule can be Figure 4 As shown, taking the first 32-point parallel module as an example, the input end of the second path is the set of the first outputs of 32 groups of 8-point serial modules, which are divided into 5 levels; the register structure can be as follows Figure 6 As shown, the fourth and seventh level operation units share registers, and the fifth, sixth and eighth level operation units share registers.
[0049] In the embodiment of the present application, a rotation factor multiplication unit is further provided between the serial submodule and the parallel submodule, and the rotation factor multiplication unit provides a first FFT rotation factor.
[0050] It is understandable that if Figure 4 As shown, there is also a rotation factor multiplication unit between the two FFT submodules; specifically, the parallel algorithm of the parallel submodule of the embodiment of the present application is:
[0051]
[0052] in, is the mth row and lth column subcarrier, N1 is the number of rows, N2 is the number of columns, N=N1*2, is the row FFT rotation factor, q ranges from 0 to (N1-1) (integral of the number of rows), is the original signal in the time domain, is the rotation factor corresponding to the position of the target frequency domain, The column FFT rotation factor provided for the parallel submodule body, r is from 0 to (N2-1) (column integral); m and l are the positions of the corresponding elements in the matrix space; N1-point DFTs represents N1-point DFT, and N2-point DFTs represents N2-point DFT.
[0053] It can be understood that the embodiment of the present application can use a fully parallel algorithm and be implemented through FPGA to reduce resource occupancy while ensuring a high rate; wherein, the embodiment of the present application can use at least one method to use the above algorithm for simulation, for example, the embodiment of the present application can use a 16QAM constellation modulation, that is, after a 12-bit quantized frequency domain constellation at the transmitting end, iFFT at the transmitting end, AD8-bit sampling at the receiving end, FFT at the receiving end, the signal-to-noise ratio simulation performance diagram can be as follows Figure 7 As shown, the resource usage graph can be Figure 8 shown.
[0054] According to the FPGA of parallel FFT proposed in the embodiment of the present application, the FPGA algorithm module can be split into serial and parallel modules, and a butterfly operation is performed by the serial module to obtain a first operation result, and then the first operation result is processed by the parallel module to obtain a second operation result, thereby completing the conversion of FFT data to corresponding path data; therefore, the embodiment of the present application can complete the real-time processing of full-bandwidth data by FPGA without the need to develop a dedicated FFT module, thereby reducing resource utilization while ensuring a high rate, thereby improving data throughput and algorithm efficiency, thereby increasing the scope of application of FPGA for high-performance applications and meeting actual usage needs.
[0055] An embodiment of the present application also provides an electronic device, comprising an FPGA of the parallel FFT as in the above embodiment.
[0056] The embodiment of the present application also provides a design method for a parallel FFT FPGA. The design method for a parallel FFT FPGA of the embodiment of the present application is described below with reference to the accompanying drawings.
[0057] like Fig. 9 As shown, the design method of the FPGA for parallel FFT is used for the design of the FPGA for parallel FFT in the above embodiment, wherein the method comprises the following steps:
[0058] In step S101, the algorithm principle of the parallel algorithm of the field programmable gate array FPGA is obtained.
[0059] It is understandable that the embodiment of the present application can first obtain the algorithm principle of the parallel algorithm of the FPGA to facilitate the subsequent splitting and transformation of the algorithm modules.
[0060] In step S102, the module executing the parallel algorithm is split into a serial module and a parallel module according to the conversion target and algorithm principle of the FFT data of the fast Fourier transform FFT, wherein each serial module includes multiple serial sub-modules, and each serial sub-module performs a butterfly operation on the FFT data of the fast Fourier transform FFT to obtain a first operation result; the parallel module includes one or more parallel sub-modules, and the first operation result output by each serial sub-module of the serial module is input to the input end of the corresponding parallel sub-module, and the parallel sub-module performs parallel processing of the butterfly operation on each first operation result, and outputs the second operation result of the corresponding number of paths, so as to convert the FFT data into the data of the corresponding number of paths.
[0061] It is understandable that the embodiment of the present application can perform Fourier transform on the algorithm obtained in the above step S101. Specifically, in the design of the submodule, the embodiment of the present application can divide the 8-point serial module into three levels according to the base 2 algorithm, the first level is to delay the original sequence by 4 moments and then perform time domain interpolation with the original sequence, the second level is to delay the first level output sequence by 2 moments and then perform time domain interpolation with the first level output, and the third level is to delay the second level output sequence by 1 moment and then perform time domain interpolation with the second level output; the 32-way FFT module five-level operation shares two registers to store butterflies, and is implemented with FPGA after the full parallel algorithm design is completed; wherein, the delay register is the input selection mode, and the three-level registers are shared.
[0062] In summary, according to the FPGA design method of parallel FFT proposed in the embodiment of the present application, the FPGA can be designed based on parallel FFT, the FPGA algorithm module can be split into serial and parallel modules, a butterfly operation is performed by the serial module to obtain a first operation result, and then the first operation result is processed by the parallel module to obtain a second operation result, thereby completing the conversion of FFT data to corresponding path data; therefore, the embodiment of the present application does not need to develop a dedicated FFT module to complete the real-time processing of full-bandwidth data by the FPGA, while ensuring a high rate and reducing resource utilization, thereby improving data throughput and algorithm efficiency, thereby increasing the scope of application of FPGA for high-performance applications and meeting actual usage needs.
[0063] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.
[0064] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0065] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.
[0066] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one or a combination of multiple of the following technologies known in the art: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array, a field programmable gate array, etc.
[0067] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.
[0068] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. A parallel FFT FPGA, characterized in that: include: One or more serial modules, wherein each serial module includes a plurality of serial sub-modules, and each serial sub-module performs a butterfly operation on FFT data of a fast Fourier transform FFT to obtain a first operation result; A parallel module, wherein the parallel module includes one or more parallel sub-modules, the first operation result output by each serial sub-module of the serial module is input to the input end of the corresponding parallel sub-module, the parallel sub-module performs parallel processing of butterfly operation on each first operation result, and outputs the second operation result of the corresponding path, so as to convert the FFT data into data of the corresponding path.
2. The FPGA of parallel FFT according to claim 1, characterized in that: The serial submodule is provided with first to third level operation units, wherein: A first-stage operation unit is used to delay the original data sequence of the FFT data by a first time instant and perform time domain interpolation with the original data sequence to obtain a first data sequence; The second-stage operation unit is used for performing time domain interpolation on the first data sequence after delaying the first data sequence by a second time instant to obtain a second data sequence; The third-level operation unit is used to perform time domain interpolation on the second data sequence after delaying the second data sequence by a third time instant to obtain a first operation result.
3. The FPGA of parallel FFT according to claim 2, characterized in that: The first to third level operation units share register delay.
4. The FPGA of parallel FFT according to claim 1, characterized in that: The parallel submodule includes fourth to eighth level operation units, wherein the fourth level operation unit and the seventh level operation unit share a register, and the fifth level operation unit, the sixth level operation unit and the eighth level operation unit share a register.
5. The FPGA of parallel FFT according to claim 1, characterized in that: The serial submodule includes a first number of input terminals, the parallel submodule includes a second number of input terminals, and each of the serial modules includes a second number of serial submodules.
6. The FPGA of parallel FFT according to claim 5, characterized in that: The first operation result includes elements of a first way number, and the second operation result includes elements of a product of the first way number and the second way number.
7. The FPGA of parallel FFT according to claim 5, characterized in that: A rotation factor multiplication unit is also arranged between the serial submodule and the parallel submodule, and the rotation factor multiplication unit provides a first FFT rotation factor.
8. The FPGA of parallel FFT according to claim 7, characterized in that: The parallel algorithm of the parallel submodule is: in, is the mth row and lth column subcarrier, N1 is the number of rows, N2 is the number of columns, N=N1*2, is the row FFT rotation factor, q ranges from 0 to (N1-1) (integral of the number of rows), is the original signal in the time domain, is the rotation factor corresponding to the position of the target frequency domain, The column FFT rotation factor provided for the parallel submodule body, r is from 0 to (N2-1) (column integral); m and l are the positions of the corresponding elements in the matrix space; N1-point DFTs represents N1-point DFT, and N2-point DFTs represents N2-point DFT.
9. An electronic device, characterized in that: An FPGA comprising a parallel FFT as described in any one of claims 1-8.
10. A design method for FPGA of parallel FFT, characterized in that: The method is used for designing an FPGA of a parallel FFT as claimed in any one of claims 1 to 8, wherein the method comprises the following steps: Obtain the algorithmic principles of parallel algorithms for field programmable gate arrays (FPGAs); According to the conversion target of the FFT data of the fast Fourier transform FFT and the algorithm principle, the module executing the parallel algorithm is split into a serial module and a parallel module, wherein each serial module includes a plurality of serial sub-modules, and each serial sub-module performs a butterfly operation on the FFT data of the fast Fourier transform FFT to obtain a first operation result; the parallel module includes one or more parallel sub-modules, and the first operation result output by each serial sub-module of the serial module is input to the input end of the corresponding parallel sub-module, and the parallel sub-module performs a butterfly operation on each first operation result in parallel, and outputs a second operation result of a corresponding number of paths, so as to convert the FFT data into data of a corresponding number of paths.