Pixel circuit and display device including same

Abstract

Disclosed are a pixel circuit and a display device including the same, the pixel circuit connecting one terminal of a second capacitor to a line of an anode initialization gate signal rather than an anode of a light emitting element, thereby preventing a change in a gate-source voltage of a first transistor. The change in the gate-source voltage of the first transistor is prevented, thereby preventing a change in the driving current generated by the first transistor. Accordingly, damage due to degradation of the light emitting element receiving the driving current is prevented, thereby improving brightness accuracy of the light emitting element.

Description

Technical Field

[0001] The present invention relates to a pixel circuit and a display device including the same, and more particularly, to a pixel circuit for preventing degradation of a light emitting element and a display device including the same. Background Art

[0002] Generally, a display device includes a display panel and a display panel driving unit. The display panel includes gate lines, data lines, emission lines and pixel circuits. The display panel driving unit includes a gate driving unit that provides a gate signal to the gate line, a data driving unit that provides a data voltage to the data line, an emission driving unit that provides an emission signal to the emission line, and a drive control unit that controls the gate driving unit, the data driving unit and the emission driving unit.

[0003] Each of the pixel circuits includes a light emitting element. The light emitting element may be degraded according to the level of the anode of the light emitting element. When the degree of the degradation is serious, the light emitting element may be damaged. When the light emitting element is damaged, the brightness accuracy of the light emitting element may be reduced. Summary of the invention

[0004] An object of the present invention is to provide a pixel circuit that prevents degradation of a light emitting element.

[0005] Another object of the present invention is to provide a display device including the pixel circuit.

[0006] To achieve one purpose of the present invention, a pixel circuit according to an embodiment of the present invention includes: a first transistor, generating a driving current; a light-emitting element, including an anode and a cathode connected to the second terminal of the first transistor; a second transistor, providing a data voltage to the gate terminal of the first transistor in response to a write gate signal; a third transistor, providing a ground voltage to the anode in response to an anode initialization gate signal; a first capacitor, including a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; and a second capacitor, including a first terminal connected to the gate terminal of the first transistor and a second terminal receiving the anode initialization gate signal.

[0007] In one embodiment, it may be that a back gate terminal of the first transistor receives a first power supply voltage.

[0008] In one embodiment, the pixel circuit may further include: a fourth transistor providing a first power supply voltage to the first terminal of the first transistor in response to an emission signal.

[0009] In one embodiment, the first to fourth transistors may be P-type transistors.

[0010] In one embodiment, the inactive level of the anode initialization gate signal may be adjusted.

[0011] In one embodiment, in the first interval, the emission signal and the anode initialization gate signal have a valid level, and the write gate signal has an invalid level.

[0012] In one embodiment, in the first interval, the first terminal of the first transistor is initialized to the first power supply voltage, and the anode is initialized to the ground voltage.

[0013] In one embodiment, it may be that in a second interval after the first interval, the write gate signal and the anode initialization gate signal have the valid level, and the emission signal has the invalid level.

[0014] In one embodiment, in the second interval, when the second transistor provides the data voltage to the gate terminal of the first transistor and the fourth transistor is turned off, the first capacitor stores a threshold voltage of the first transistor.

[0015] In one embodiment, in a third interval after the second interval, the anode initialization gate signal has the valid level, and the emission signal and the write gate signal have the invalid level.

[0016] In one embodiment, in the third interval, the first capacitor may maintain a threshold voltage of the first transistor.

[0017] In one embodiment, in a fourth interval after the third interval, the emission signal has the valid level, and the write gate signal and the anode initialization gate signal have the invalid level.

[0018] In one embodiment, the light emitting element may emit light based on the driving current in the fourth interval.

[0019] In one embodiment, it may be that the first transistor includes the gate terminal connected to the first node, the first terminal connected to the second node, and the second terminal connected to the third node, the light emitting element includes the anode connected to the third node and the cathode receiving the second power supply voltage, the second transistor includes the gate terminal receiving the write gate signal, the first terminal connected to the data line transmitting the data voltage, and the second terminal connected to the first node, the third transistor includes the gate terminal receiving the emission signal, the first terminal connected to the third node, and the second terminal receiving the ground voltage, the fourth transistor includes the gate terminal receiving the emission signal, the first terminal receiving the first power supply voltage, and the second terminal connected to the second node, the first capacitor includes the first terminal connected to the second node and the second terminal connected to the first node, and the second capacitor includes the first terminal connected to the first node and the second terminal receiving the anode initialization gate signal.

[0020] In one embodiment, the pixel circuit may further include: a third capacitor including a first terminal receiving the first power supply voltage and a second terminal connected to the gate terminal of the first transistor.

[0021] In one embodiment, the third capacitor may include the first terminal receiving the first power supply voltage and the second terminal connected to a first node.

[0022] To achieve another object of the present invention, a display device according to an embodiment of the present invention includes: a display panel including a pixel circuit; and a display panel driving unit driving the display panel. The pixel circuit includes: a first transistor generating a driving current; a light emitting element including an anode and a cathode connected to the second terminal of the first transistor; a second transistor providing a data voltage to the gate terminal of the first transistor in response to a write gate signal; a third transistor providing a ground voltage to the anode in response to an anode initialization gate signal; a first capacitor including a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; and a second capacitor including a first terminal connected to the gate terminal of the first transistor and a second terminal receiving the anode initialization gate signal.

[0023] In one embodiment, it may be that a back gate terminal of the first transistor receives a first power supply voltage.

[0024] In one embodiment, the pixel circuit may further include: a fourth transistor providing a first power supply voltage to the first terminal of the first transistor in response to an emission signal.

[0025] In one embodiment, the first to fourth transistors may be P-type transistors.

[0026] According to the pixel circuit of the embodiment of the present invention and the display device including the same, one terminal of the second capacitor is connected to the line of the anode initialization gate signal instead of the anode of the light-emitting element, so that the gate-source voltage of the first transistor can be prevented from changing. The gate-source voltage of the first transistor is prevented from changing, so that the driving current generated by the first transistor can be prevented from changing. Therefore, the damage caused by the degradation of the light-emitting element receiving the driving current can be prevented, thereby improving the brightness accuracy of the light-emitting element.

[0027] However, the effects of the present invention are not limited to the above-described effects, and can be variously extended within the scope not departing from the concept and field of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0029] Figure 2 It is shown Figure 1 A circuit diagram of an example of a pixel circuit.

[0030] Figure 3 Is shown driving Figure 2 A timing diagram of an example of a pixel circuit.

[0031] Figure 4 It is shown Figure 2 The pixel circuit is Figure 3 A timing diagram of an example of operation in the first interval.

[0032] Figure 5 It is shown Figure 2 The pixel circuit is Figure 3 A circuit diagram of an example of operation in the first interval.

[0033] Figure 6 It is shown Figure 2 The pixel circuit is Figure 3 A timing diagram of an example of operation in the second interval.

[0034] Figure 7 It is shown Figure 2 The pixel circuit is Figure 3 A circuit diagram of an example of operation in the second interval.

[0035] Figure 8 It is shown Figure 2 The pixel circuit is Figure 3A timing diagram of an example of operation in the third interval.

[0036] Fig. 9 It is shown Figure 2 The pixel circuit is Figure 3 A circuit diagram of an example of operation in the third interval.

[0037] Fig.10 It is shown Figure 2 The pixel circuit is Figure 3 A timing diagram of an example of operation in the fourth interval.

[0038] Fig.11 It is shown Figure 2 The pixel circuit is Figure 3 A circuit diagram of an example of operation in the fourth interval.

[0039] Fig.12 It is shown Figure 1 A circuit diagram of an example of a pixel circuit.

[0040] Fig.13 is a block diagram illustrating an electronic device according to an embodiment of the present invention.

[0041] Fig.14 It is shown Fig.13 An example of an electronic device implemented as a smart phone is shown in the figure.

[0042] Fig.15 It is shown Fig.13 FIG. 1 is a diagram showing an example of an electronic device implemented as a head-mounted display device.

[0043] (Explanation of Reference Numerals)

[0044] 10: Display device 100: Display panel

[0045] 200: drive control unit 300: gate drive unit

[0046] 400: Gamma reference voltage generating unit 500: Data driving unit

[0047] 600: Transmitter drive unit DETAILED DESCRIPTION

[0048] Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

[0049] Figure 1 is a block diagram showing a display device 10 according to an embodiment of the present invention.

[0050] Reference Figure 1The display device 10 may include a display panel 100 and a display panel driving unit. The display panel driving unit may include a driving control unit 200, a gate driving unit 300, a gamma reference voltage generating unit 400, a data driving unit 500, and an emission driving unit 600.

[0051] For example, the drive control unit 200 and the data drive unit 500 may be formed as one body. For example, the drive control unit 200, the gamma reference voltage generating unit 400 and the data drive unit 500 may be formed as one body. For example, the drive control unit 200, the gate drive unit 300, the gamma reference voltage generating unit 400 and the data drive unit 500 may be formed as one body. For example, the drive control unit 200, the gate drive unit 300, the gamma reference voltage generating unit 400, the data drive unit 500 and the emission drive unit 600 may be formed as one body. On the other hand, the drive module in which at least the drive control unit 200 and the data drive unit 500 are formed as one body may be named as a timing controller embedded data driver (TED).

[0052] The display panel 100 may include a display portion that displays an image and a peripheral portion that is disposed adjacent to the display portion.

[0053] For example, the display panel 100 may be an organic light emitting diode display panel including an organic light emitting diode. As another example, the display panel 100 may be a quantum dot organic light emitting diode display panel including an organic light emitting diode and a quantum dot color filter. As yet another example, the display panel 100 may be a quantum dot nano light emitting diode display panel including a nano light emitting diode and a quantum dot color filter. As yet another example, the display panel 100 may be a liquid crystal display panel including a liquid crystal layer.

[0054] The display panel 100 may include gate lines GL, data lines DL, emission lines EML, and pixel circuits P electrically connected to the gate lines GL, the data lines DL, and the emission lines EML. The gate lines GL may extend in a first direction, the data lines DL may extend in a second direction crossing the first direction, and the emission lines EML may extend in the first direction.

[0055] The drive control unit 200 may receive input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. According to an embodiment, the input image data IMG may also include white image data. As another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0056] The driving control part 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0057] The driving control part 200 may generate the first control signal CONT1 for controlling the operation of the gate driving part 300 based on the input control signal CONT and output it to the gate driving part 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0058] The driving control part 200 may generate the second control signal CONT2 for controlling the operation of the data driving part 500 based on the input control signal CONT and output it to the data driving part 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0059] The driving control part 200 may generate the data signal DATA based on the input image data IMG. The driving control part 200 may output the data signal DATA to the data driving part 500.

[0060] The driving control part 200 may generate the third control signal CONT3 for controlling the operation of the gamma reference voltage generating part 400 based on the input control signal CONT and output the third control signal CONT3 to the gamma reference voltage generating part 400 .

[0061] The driving control part 200 may generate the fourth control signal CONT4 for controlling the operation of the emission driving part 600 based on the input control signal CONT and output it to the emission driving part 600 .

[0062] The gate driving part 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving control part 200. The gate driving part 300 may output the gate signal to the gate line GL.

[0063] In one embodiment, the gate driving unit 300 may be integrated on the periphery of the display panel 100 .

[0064] The gamma reference voltage generating part 400 may generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving control part 200. The gamma reference voltage generating part 400 may provide the gamma reference voltage VGREF to the data driving part 500. The gamma reference voltage VGREF may have a value corresponding to each of the data signals DATA.

[0065] In one embodiment, the gamma reference voltage generating section 400 may be configured in the driving control section 200 or in the data driving section 500 .

[0066] The data driving unit 500 may receive the second control signal CONT2 and the data signal DATA from the driving control unit 200, and may receive the gamma reference voltage VGREF from the gamma reference voltage generating unit 400. The data driving unit 500 may convert the data signal DATA into a data voltage VDATA in an analog form by using the gamma reference voltage VGREF. The data driving unit 500 may output the data voltage VDATA to the data line DL.

[0067] The emission driving part 600 may generate an emission signal for driving the emission line EML in response to the fourth control signal CONT4 received from the driving control part 200. The emission driving part 600 may output the emission signal to the emission line EML.

[0068] In one embodiment, the emission driving unit 600 may be integrated in the peripheral portion of the display panel 100. In one embodiment, the emission driving unit 600 may be mounted in the peripheral portion of the display panel 100.

[0069] For ease of explanation, Figure 1, the gate driving unit 300 is configured on the first side of the display panel 100, and the emission driving unit 600 is configured on the second side of the display panel 100, but the present invention is not limited thereto. For example, the gate driving unit 300 and the emission driving unit 600 may all be configured on the first side of the display panel 100. For example, the gate driving unit 300 and the emission driving unit 600 may all be configured on both sides of the display panel 100. For example, the gate driving unit 300 and the emission driving unit 600 may also be formed as one body.

[0070] Figure 2 It is shown Figure 1 A circuit diagram of an example of a pixel circuit P.

[0071] Reference Figure 1 as well as Figure 2 The pixel circuit P may include a first transistor T1 generating a driving current, a light emitting element EE including an anode connected to the second terminal of the first transistor T1 and a cathode, a second transistor T2 providing a data voltage VDATA to the gate terminal of the first transistor T1 in response to a write gate signal GW, a third transistor T3 providing a ground voltage VGND to the anode in response to an anode initialization gate signal EB, a first capacitor C1 including a first terminal connected to the first terminal of the first transistor T1 and a second terminal connected to the gate terminal of the first transistor T1, and a second capacitor C2 including a first terminal connected to the gate terminal of the first transistor T1 and a second terminal receiving the anode initialization gate signal EB. The pixel circuit P may further include a fourth transistor T4 providing a first power supply voltage ELVDD to the first terminal of the first transistor T1 in response to an emission signal EM.

[0072] The first transistor T1 may include the gate terminal connected to the first node N1, the first terminal connected to the second node N2, and the second terminal connected to the third node N3. The first transistor may also include a back gate terminal receiving the first power supply voltage ELVDD. When the emission signal EM has an effective level, the voltage of the back gate terminal of the first transistor T1 and the voltage of the first terminal of the first transistor T1 may be equal to the first power supply voltage ELVDD. Therefore, the first transistor T1 may include the back gate terminal receiving the first power supply voltage ELVDD, thereby minimizing the body effect of changing the threshold voltage of the first transistor T1. That is, the threshold voltage compensation capability of the pixel circuit P can be improved.

[0073] The light emitting element EE may include the anode connected to the third node N3 and the cathode receiving the second power supply voltage ELVSS. The second power supply voltage ELVSS may be lower than the first power supply voltage ELVDD. For example, the second power supply voltage ELVSS may be -4V. In the present embodiment, the light emitting element EE may be an ultra-small light emitting diode (or a micro light emitting diode). The display device including the ultra-small light emitting diode may be a silicon-based display. The silicon-based display is conducive to achieving high integration due to the excellent electrical characteristics and fine device size of silicon-based devices. However, the present invention is not limited thereto. In another embodiment, the light emitting element EE may also be an organic light emitting diode.

[0074] The second transistor T2 may include a gate terminal receiving the write gate signal GW, a first terminal connected to the data line DL transmitting the data voltage VDATA, and a second terminal connected to the first node N1.

[0075] The third transistor T3 may include a gate terminal receiving the anode initialization gate signal EB, a first terminal connected to the third node N3, and a second terminal receiving the ground voltage VGND. For example, the ground voltage VGND may be 0V.

[0076] The fourth transistor T4 may include a gate terminal receiving the emission signal EM, a first terminal receiving the first power voltage ELVDD, and a second terminal connected to the second node N2.

[0077] The first capacitor C1 may include the first terminal connected to the second node N2 and the second terminal connected to the first node N1.

[0078] The second capacitor C2 may include the first terminal connected to the first node N1 and the second terminal receiving the anode initializing gate signal EB.

[0079] In one embodiment, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 may be P-type transistors. In this case, the first terminals of the first to fourth transistors T1 to T4 may be source terminals, and the second terminals of the first to fourth transistors T1 to T4 may be drain terminals. In addition, the effective level may be a low level, and the ineffective level may be a high level. For example, when the gate signal applied to the gate terminal of the P-type transistor has the low level, the P-type transistor may be turned on. For example, when the gate signal applied to the gate terminal of the P-type transistor has the high level, the P-type transistor may be turned off.

[0080] However, the present invention is not limited thereto. In one embodiment, the first to fourth transistors T1 to T4 may be N-type transistors. In this case, the effective level may be the high level, and the ineffective level may be the low level. For example, when the gate signal applied to the gate terminal of the N-type transistor has the high level, the P-type transistor may be turned on. For example, when the gate signal applied to the gate terminal of the N-type transistor has the low level, the N-type transistor may be turned off.

[0081] Figure 3 Is shown driving Figure 2 A timing diagram of an example of a pixel circuit P.

[0082] Reference Figures 1 to 3 , it may be that, in the first interval P1, the emission signal EM and the anode initialization gate signal EB have the effective level, and the write gate signal GW has the ineffective level.

[0083] It may be that, in a second interval P2 after the first interval P1, the write gate signal GW and the anode initialization gate signal EB have the effective level, and the emission signal EM has the ineffective level.

[0084] It may be that, in a third interval P3 after the second interval P2, the anode initialization gate signal EB has the effective level, and the emission signal EM and the write gate signal GW have the ineffective level.

[0085] It may be that, in a fourth interval P4 after the third interval P3, the emission signal has the valid level, and the write gate signal GW and the anode initialization gate signal EB have the invalid level.

[0086] Figure 4 It is shown Figure 2 The pixel circuit P in Figure 3 This is a timing diagram of an example of operation in the first interval P1 of FIG. Figure 5 It is shown Figure 2 The pixel circuit P in Figure 3 A circuit diagram of an example of operation in the first interval P1 of FIG.

[0087] Reference Figure 4 as well as Figure 5 , in the first interval P1, the third transistor T3 and the fourth transistor T4 can be turned on, and the second transistor T2 can be turned off.

[0088] A path may be formed through the fourth transistor T4, the first transistor T1, and the third transistor T3. The first terminal of the first transistor T1 may be initialized through the path. The anode may be initialized through the path. For example, the second node N2 (i.e., the first terminal of the first transistor T1) may be initialized to the first power supply voltage ELVDD. The third node N3 (i.e., the second terminal of the first transistor T1 and the anode) may be initialized to the ground voltage VGND.

[0089] The anode is initialized to the ground voltage VGND, so that light emission of the light emitting element EE due to leakage current in the pixel circuit P displaying black can be minimized.

[0090] Figure 6 It is shown Figure 2 The pixel circuit P in Figure 3 A timing diagram of an example of operation in the second interval P2. Figure 7 It is shown Figure 2 The pixel circuit P in Figure 3 A circuit diagram of an example of operation in the second interval P2.

[0091] Reference Figure 6 as well as Figure 7 In the second interval P2, the second transistor T2 and the third transistor T3 can be turned on, and the fourth transistor T4 can be turned off.

[0092] The second transistor T2 may provide the data voltage VDATA to the first node N1 (i.e., the gate terminal of the first transistor). The second transistor T2 provides the data voltage VDATA to the first node N1 and the fourth transistor T4 is turned off, so the voltage of the first node N1 may be the data voltage VDATA, and the voltage of the second node N2 may be VDATA-VTH. Here, VDATA is the data voltage, and VTH is the threshold voltage of the first transistor T1. The first capacitor C1 may store the threshold voltage VTH of the first transistor T1. Thus, the threshold voltage VTH of the first transistor T1 may be compensated.

[0093] Figure 8 It is shown Figure 2 The pixel circuit P in Figure 3 A timing diagram of an example of operation in the third interval P3. Fig. 9 It is shown Figure 2 The pixel circuit P in Figure 3A circuit diagram of an example of operation in the third interval P3.

[0094] Reference Figure 8 as well as Fig. 9 In the third interval P3, the third transistor T3 may be turned on, and the second transistor T2 and the fourth transistor T4 may be turned off.

[0095] In the third interval P3, the first capacitor C1 may maintain the threshold voltage VTH of the first transistor T1 stored in the second interval P2. Thus, the threshold voltage VTH of the first transistor T1 may be continuously compensated.

[0096] Fig.10 It is shown Figure 2 The pixel circuit P in Figure 3 A timing diagram of an example of operation in the fourth interval P4. Fig.11 It is shown Figure 2 The pixel circuit P in Figure 3 A circuit diagram of an example of operation in the fourth interval P4.

[0097] Reference Fig.10 as well as Fig.11 In the fourth interval P4, the fourth transistor T4 may be turned on, and the second transistor T2 and the third transistor T3 may be turned off.

[0098] The voltage of the first node N1 (i.e., the gate terminal of the first transistor T1) may be determined based on the data voltage VDATA. The driving current may be determined based on the gate-source voltage of the first transistor T1. Therefore, the driving current may be determined based on the voltage of the first node N1, and the light emitting element EE may emit light at a brightness corresponding to the driving current.

[0099] The voltage of the second node N2 is the first power supply voltage ELVDD and the third transistor T3 is turned off, so the voltage of the first node N1 (that is, the voltage of the gate terminal of the first transistor T1) can be voltage-divided by the first capacitor C1 and the second capacitor C2. Therefore, the voltage of the first node N1 may be VDATA+(ELVDD-VDATA-VTH)×(C_C1) / (C_C1+C_C2)+ΔV_EB×(C_C2) / (C_C1+C_C2), and the voltage of the second node N2 may be ELVDD. That is, the gate-source voltage of the first transistor T1 may be -(ELVDD–VDATA-ΔV_EB)×(C_C2) / (C_C1+C_C2)+VTH×(C_C1) / (C_C1+C_C2). In the gate-source voltage of the first transistor T1, the component of VDATA is VDATA×(C_C2) / (C_C1+C_C2), (C_C2) / (C_C1+C_C2) is less than 1, so the data range of the data voltage VDATA can be extended. Here, ELVDD is the first power supply voltage, VDATA is the data voltage, VTH is the threshold voltage of the first transistor T1, C_C1 is the capacitance of the first capacitor C1, C_C2 is the capacitance of the second capacitor C2, and ΔV_EB is the difference between the effective level of the anode initialization gate signal EB and the ineffective level of the anode initialization gate signal EB.

[0100] On the other hand, in the case where the second terminal of the second capacitor C2 is connected to the anode, when the light emitting element EE emits light, the light emitting element EE may be degraded and the voltage of the anode may change. When the voltage of the anode changes, the voltage of the first node N1 may change. When the voltage of the first node N1 changes, the driving current of the first transistor T1 may change. Therefore, the brightness accuracy of the light emitting element EE according to the data voltage VDATA may be reduced.

[0101] The second terminal of the second capacitor C2 may be connected to the line of the anode initialization gate signal EB instead of the anode. That is, the second terminal of the second capacitor C2 may receive the anode initialization gate signal EB. Therefore, during the period when the light emitting element EE emits light, the second terminal of the second capacitor C2 and the anode are not connected to each other, so that the degradation of the light emitting element EE can be prevented. Therefore, the situation in which the brightness accuracy of the light emitting element EE according to the first data voltage VDATA is reduced can be prevented.

[0102] Such an effect can be confirmed in the mathematical formula "-(ELVDD-VDATA-ΔV_EB)×(C_C2) / (C_C1+C_C2)+VTH×(C_C1) / (C_C1+C_C2)" for the gate-source voltage of the first transistor T1 described above. During the light emission of the light-emitting element EE, in the mathematical formula for the gate-source voltage of the first transistor T1, the difference between the valid level of the anode initialization gate signal EB and the invalid level of the anode initialization gate signal EB is shown, and the changed voltage of the anode of the light-emitting element is not shown. In one embodiment, the invalid level of the anode initialization gate signal EB can be adjusted. That is, ΔV_EB can be adjusted.

[0103] In this way, according to the pixel circuit P and the display device 10 including the pixel circuit P, one terminal of the second capacitor C2 can be connected to the line of the anode initialization gate signal EB instead of the anode of the light emitting element EE, thereby preventing the gate-source voltage of the first transistor T1 from changing. By preventing the gate-source voltage of the first transistor T1 from changing, the driving current generated by the first transistor T1 can be prevented from changing. Therefore, damage caused by degradation of the light emitting element EE receiving the driving current can be prevented, thereby improving the brightness accuracy of the light emitting element EE.

[0104] Fig.12 It is shown Figure 1 A circuit diagram of an example of a pixel circuit P.

[0105] Fig.12 The pixel circuit P includes a third capacitor C3 and a Figure 2 The pixel circuits P of FIG. 1 and FIG. 2 are substantially the same. Therefore, descriptions of substantially the same or repeated structures and operations are omitted.

[0106] Reference Figure 2 as well as Fig.12 , Fig.12 The pixel circuit P may also include Figure 2 The third capacitor C3 has a first terminal in the pixel circuit P receiving the first power voltage ELVDD and a second terminal connected to the first node N1.

[0107] The third capacitor C3 may include the first terminal receiving the first power voltage ELVDD and the second terminal connected to the first node N1.

[0108] Fig.12The pixel circuit P further includes the third capacitor C3, so that the data range of the data voltage VDATA can be changed.

[0109] In the second interval P2 , the second transistor T2 provides the data voltage VDATA to the first node N1 , and the fourth transistor T4 is turned off, so the voltage of the first node N1 may be the data voltage VDATA, and the voltage of the second node N2 may be VDATA-VTH.

[0110] In the fourth interval P4, the voltage of the second node N2 is the first power supply voltage ELVDD, and the third transistor T3 is turned off, so the voltage of the first node N1 (that is, the voltage of the gate terminal of the first transistor T1) can be voltage-divided by the first capacitor C1, the second capacitor C2, and the third capacitor C3. Therefore, the voltage of the first node N1 may be VDATA+(ELVDD-VDATA-VTH)×(C_C1) / (C_C1+C_C2+C_C3)+ΔV_EB×(C_C2) / (C_C1+C_C2+C_C3), and the voltage of the second node N2 is ELVDD. That is, the gate-source voltage of the first transistor T1 may be -(ELVDD-VDATA)×(C_C2+C_C3) / (C_C1+C_C2+C_C3)+ΔV_EB×(C_C2) / (C_C1+C_C2+C_C3)+VTH×(C_C1) / (C_C1+C_C2+C_C3). In the gate-source voltage of the first transistor T1, the component of VDATA is VDATA×(C_C2+C_C3) / (C_C1+C_C2+C_C3), (C_C2+C_C3) / (C_C1+C_C2+C_C3) is less than 1, so the data range of the data voltage VDATA may be extended. Here, C_C3 is the capacitance of the third capacitor C3.

[0111] In this way, according to the pixel circuit P and the display device 10 including the pixel circuit P, one terminal of the second capacitor C2 is connected to the line of the anode initialization gate signal EB of the anode instead of the light emitting element EE, so that the gate-source voltage of the first transistor T1 can be prevented from changing. The gate-source voltage of the first transistor T1 is prevented from changing, so that the driving current generated by the first transistor T1 can be prevented from changing. Therefore, the light emitting element EE receiving the driving current can be prevented from being damaged due to degradation, thereby improving the brightness accuracy of the light emitting element EE.

[0112] Fig.13 is a block diagram illustrating an electronic device according to an embodiment of the present invention. Fig.14 It is shown Fig.13 The electronic device 1000 is implemented as an example of a smart phone. Fig.15 It is shown Fig.13 FIG. 1 is a diagram showing an example of an electronic device 1000 implemented as a head-mounted display device.

[0113] Reference Figures 13 to 15 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include various ports that can communicate with a graphics card, a sound card, a memory card, a USB device, etc., or communicate with other systems.

[0114] According to one embodiment, Fig.14 As shown, the electronic device 1000 may be implemented as a smart phone. According to another embodiment, Fig.15 As shown, the electronic device 1000 can be implemented as a head mounted display device. However, this is exemplary, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can also be implemented by a portable phone, a video phone, a smart tablet, a smart watch, a tablet PC, a vehicle navigation system, a computer monitor, a notebook, etc.

[0115] The processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be connected to other components via an address bus, a control bus, and a data bus, etc. According to an embodiment, the processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0116] The memory device 1020 can store data required for the operation of the electronic device 1000 . For example, the memory device 1020 may include an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM) device, and / or a non-volatile memory device such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device. Memory; SRAM) devices, mobile DRAM devices and other volatile memory devices.

[0117] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

[0118] The input-output device 1040 may include an input device such as a keyboard, a numeric keypad, a touch pad, a touch screen, a mouse, and an output device such as a speaker and a printer. According to an embodiment, the display device 1060 may also be included in the input-output device 1040.

[0119] The power supply 1050 can provide the power required for the electronic device 1000 to operate.

[0120] The display device 1060 may be connected to other components via a bus or other communication links.

[0121] The present invention can be applied to pixel circuits and display devices including the same. For example, the present invention can be applied to mobile phones, smart phones, tablet computers, TVs, digital TVs, 3D TVs, PCs, home electronic devices, notebook computers, PDAs, PMPs, digital cameras, music players, portable game consoles, navigation devices, etc.

[0122] The above description refers to the embodiments of the present invention, but it should be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the concept and scope of the present invention described in the appended claims.

Claims

1. A pixel circuit, characterized in that: include: A first transistor generates a driving current; a light emitting element including an anode connected to the second terminal of the first transistor and a cathode; a second transistor providing a data voltage to a gate terminal of the first transistor in response to a write gate signal; a third transistor providing a ground voltage to the anode in response to an anode initialization gate signal; a first capacitor comprising a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; as well as A second capacitor includes a first terminal connected to the gate terminal of the first transistor and a second terminal receiving the anode initialization gate signal.

2. The pixel circuit according to claim 1, characterized in that: A back gate terminal of the first transistor receives a first supply voltage.

3. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes a fourth transistor that provides a first power supply voltage to the first terminal of the first transistor in response to an emission signal.

4. The pixel circuit according to claim 3, characterized in that: The first to fourth transistors are P-type transistors.

5. The pixel circuit according to claim 1, characterized in that: The inactive level of the anode initialization gate signal is adjusted.

6. The pixel circuit according to claim 3, characterized in that: In a first interval, the emission signal and the anode initialization gate signal have a valid level, and the write gate signal has an invalid level.

7. The pixel circuit according to claim 6, characterized in that: In the first interval, the first terminal of the first transistor is initialized to the first power supply voltage, and the anode is initialized to the ground voltage.

8. The pixel circuit according to claim 6, characterized in that: In a second interval after the first interval, the write gate signal and the anode initialization gate signal have the valid level, and the emission signal has the invalid level.

9. The pixel circuit according to claim 8, characterized in that: In the second interval, when the second transistor supplies the data voltage to the gate terminal of the first transistor and the fourth transistor is turned off, the first capacitor stores a threshold voltage of the first transistor.

10. The pixel circuit according to claim 8, characterized in that: In a third interval after the second interval, the anode initialization gate signal has the active level, and the emission signal and the write gate signal have the inactive level.

11. The pixel circuit according to claim 10, characterized in that: In the third interval, the first capacitor holds a threshold voltage of the first transistor.

12. The pixel circuit according to claim 10, characterized in that: In a fourth interval after the third interval, the emission signal has the active level, and the write gate signal and the anode initialization gate signal have the inactive level.

13. The pixel circuit according to claim 12, characterized in that: In the fourth section, the light emitting element emits light based on the driving current.

14. The pixel circuit according to claim 3, characterized in that: The first transistor includes the gate terminal connected to a first node, the first terminal connected to a second node, and the second terminal connected to a third node, The light emitting element includes the anode connected to the third node and the cathode receiving the second power supply voltage, The second transistor includes a gate terminal receiving the write gate signal, a first terminal connected to a data line transmitting the data voltage, and a second terminal connected to the first node. The third transistor includes a gate terminal receiving the transmission signal, a first terminal connected to the third node, and a second terminal receiving the ground voltage. The fourth transistor includes a gate terminal receiving the transmission signal, a first terminal receiving the first power supply voltage, and a second terminal connected to the second node. The first capacitor includes the first terminal connected to the second node and the second terminal connected to the first node, The second capacitor includes the first terminal connected to the first node and the second terminal receiving the anode initialization gate signal.

15. The pixel circuit according to claim 3, characterized in that: The pixel circuit further includes a third capacitor including a first terminal receiving the first power supply voltage and a second terminal connected to the gate terminal of the first transistor.

16. The pixel circuit according to claim 15, characterized in that: The third capacitor includes the first terminal receiving the first power supply voltage and the second terminal connected to a first node.

17. A display device, characterized in that: include: A display panel including a pixel circuit; as well as A display panel driving unit drives the display panel. The pixel circuit comprises: A first transistor generates a driving current; a light emitting element including an anode connected to the second terminal of the first transistor and a cathode; a second transistor providing a data voltage to a gate terminal of the first transistor in response to a write gate signal; a third transistor providing a ground voltage to the anode in response to an anode initialization gate signal; a first capacitor including a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; and A second capacitor includes a first terminal connected to the gate terminal of the first transistor and a second terminal receiving the anode initialization gate signal.

18. The display device according to claim 17, characterized in that: A back gate terminal of the first transistor receives a first supply voltage.

19. The display device according to claim 17, characterized in that: The pixel circuit further includes a fourth transistor that provides a first power supply voltage to the first terminal of the first transistor in response to an emission signal.

20. The display device according to claim 19, characterized in that The first to fourth transistors are P-type transistors.

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