Electronic device and electronic system for performing phase adjustment operation

Abstract

The invention relates to an electronic device and an electronic system for performing a phase adjustment operation. The electronic device includes: a phase detection circuit configured to detect a phase difference between a reference clock and a feedback clock; and a phase-locked signal generation circuit configured to generate a phase-locked signal based on a detection result of a phase difference between the reference clock and the feedback clock. The phase-locked signal generation circuit is configured to generate a phase-locked signal when a phase difference between the reference clock and the feedback clock is equal to or less than a first phase difference after the initial operation starts, and is configured to generate a phase-locked signal when a phase difference between the reference clock and the feedback clock is equal to or less than a second phase difference after the phase-locked signal is output. And when the phase difference between the reference clock and the feedback clock is equal to or greater than a second phase difference, stopping generating the phase-locked signal, wherein the second phase difference is greater than the first phase difference.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0107234 filed in the Korean Intellectual Property Office on August 16, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an electronic device and an electronic system for performing a phase adjustment operation, which adjusts the phase of a phase-locked loop (PLL) clock by detecting a difference between the phases of a reference clock and a feedback clock during a setup period. Background Art

[0004] Generally, a semiconductor device including a double data rate synchronous DRAM (DDR SDRAM) generates an internal clock signal by receiving a clock signal from an external device, and uses the internal clock signal as a reference for synchronizing various types of operation timings within the semiconductor device. Therefore, a circuit for generating an internal clock signal is included in the semiconductor device. Such a circuit typically includes a phase-locked loop (PLL) and a delay-locked loop (DLL). Summary of the invention

[0005] In an embodiment, the electronic device may include: a phase detection circuit configured to detect a phase difference between a reference clock and a feedback clock; and a phase lock signal generation circuit configured to generate a phase lock signal based on a detection result of the phase difference between the reference clock and the feedback clock. The phase lock signal generation circuit is configured to generate the phase lock signal when the phase difference between the reference clock and the feedback clock is equal to or less than a first phase difference after the initial operation starts, and is configured to stop generating the phase lock signal when the phase difference between the reference clock and the feedback clock is equal to or greater than a second phase difference after the phase lock signal is output, and the second phase difference is greater than the first phase difference.

[0006] In addition, the electronic device may include: an initial detection signal generating circuit, configured to generate an initial detection signal after the initial operation starts, when the phase difference between the reference clock and the feedback clock is equal to or less than a first phase difference; an operation detection signal generating circuit, configured to stop generating the operation detection signal after outputting a phase-locked signal, when the phase difference between the reference clock and the feedback clock is equal to or greater than a second phase difference, and the second phase difference is greater than the first phase difference; and a latch circuit, configured to generate a phase-locked signal based on the initial detection signal and the operation detection signal.

[0007] In addition, the method for adjusting the phase may include: an initial operation step, which: after the initial operation starts, detects the phase difference between the reference clock and the feedback clock, and generates an initial detection signal for generating a phase-locked signal when the phase difference between the reference clock and the feedback clock is equal to or less than a first phase difference; and a phase-locked signal control step, which: after outputting the phase-locked signal, generates an operation detection signal for stopping the generation of the phase-locked signal when the phase difference between the reference clock and the feedback clock is equal to or greater than a second phase difference, and the second phase difference is greater than the first phase difference. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram showing a structure of an electronic system according to an embodiment of the present disclosure.

[0009] Figure 2 It shows that according to Figure 1 A block diagram of the structure of an embodiment of an electronic device included in the electronic system shown.

[0010] Figure 3 It shows that according to Figure 2 FIG. 2 is a block diagram showing a structure of an embodiment of a PLL clock generation circuit included in an electronic device.

[0011] Figure 4 It shows that according to Figure 3 FIG. 2 is a block diagram showing a structure of an embodiment of a phase detection circuit included in a PLL clock generation circuit.

[0012] Figure 5 It shows that according to Figure 4 A circuit diagram showing a structure of an embodiment of a reference clock phase control circuit included in a phase detection circuit shown in FIG.

[0013] Figure 6 It shows that according to Figure 4 A circuit diagram showing the structure of an embodiment of a feedback clock phase control circuit included in a phase detection circuit shown.

[0014] Figure 7 It shows that according to Figure 4 FIG. 2 is a circuit diagram showing a structure of an embodiment of a reset signal generating circuit included in a phase detection circuit.

[0015] Figure 8 and Fig. 9 is a timing chart for describing the operation of the phase detection circuit according to the embodiment of the present disclosure.

[0016] Fig.10 It shows that according to Figure 3 FIG. 2 is a block diagram showing a structure of an embodiment of a phase lock signal generating circuit included in a PLL clock generating circuit.

[0017] Fig.11 It shows that according to Fig.10 FIG. 2 is a block diagram showing a structure of an embodiment of an initial detection signal generating circuit included in a phase lock signal generating circuit.

[0018] Fig.12 It shows that according to Fig.11 FIG. 2 is a diagram showing a structure of an embodiment of a setting signal generating circuit included in an initial detection signal generating circuit shown in FIG.

[0019] Fig.13 It shows that according to Fig.11 FIG. 2 is a block diagram showing a structure of an embodiment of a period setting circuit included in an initial detection signal generating circuit.

[0020] Fig.14 It shows that according to Fig.13 A circuit diagram showing a structure of an embodiment of an adder included in a period setting circuit shown.

[0021] Fig.15 is a table for describing a first setting period and a second setting period based on a compensation code and an offset code according to an embodiment of the present disclosure.

[0022] Fig.16 It shows that according to Fig.10 A circuit diagram showing a structure of an embodiment of a latch circuit included in a phase-locked signal generating circuit.

[0023] Fig.17 and Fig.18 is a timing chart for describing the operation of the initial detection signal generating circuit according to an embodiment of the present disclosure.

[0024] Fig.19 is a timing chart for describing the operation of the phase lock signal generating circuit according to an embodiment of the present disclosure.

[0025] Fig. 20 is a flowchart for describing a method for adjusting a phase according to an embodiment of the present disclosure.

[0026] Fig.21 It shows that according to the application Figure 1 and Fig.19 A diagram of the structure of an embodiment of an electronic system is shown. DETAILED DESCRIPTION

[0027] In the description of the following embodiments, the term "preset" means that the value of the parameter is predetermined when the parameter is used in a process or algorithm. According to the embodiment, the value of the parameter can be set when the process or algorithm is started or when the process or algorithm is executed.

[0028] Terms such as "first" and "second" used to distinguish between various components are not limited to the components. For example, a first component may be referred to as a second component, and vice versa.

[0029] When a component is referred to as being “coupled” or “connected” to another component, it should be understood that the components may be directly coupled or connected to each other, or coupled or connected to each other with another component interposed therebetween. Conversely, when a component is referred to as being “directly coupled” or “directly connected” to another component, it should be understood that the components are directly coupled or connected to each other without another component interposed therebetween.

[0030] "Logical high level" and "logical low level" are used to describe the logic level of a signal. A signal with a "logical high level" is different from a signal with a "logical low level". For example, when a signal with a first voltage corresponds to a signal with a "logical high level", a signal with a second voltage may correspond to a signal with a "logical low level". According to an embodiment, the "logical high level" may be set to a voltage higher than the "logical low level". According to an embodiment, the logic level of a signal may be set to a different logic level or an opposite logic level. For example, in some embodiments, a signal with a logical high level may be set to have a logical low level, and in some embodiments, a signal with a logical low level may be set to have a logical high level.

[0031] Hereinafter, the present disclosure will be described in more detail by way of examples. The examples are only used to illustrate the present disclosure, and the scope of the present disclosure is not limited by the examples.

[0032] Embodiments of the present disclosure can provide an electronic device and an electronic system that can prevent unnecessary generation of a phase-locked signal due to jitter and noise by setting a first setting period to short based on a compensation code, setting a second setting period to long based on an offset code, and generating a phase-locked signal after an initial operation starts.

[0033] According to the present disclosure, it is possible to prevent a phase lock signal from being unnecessarily generated due to jitter and noise by setting a first setting period short based on a compensation code, setting a second setting period long based on an offset code, and generating a phase lock signal after an initial operation starts.

[0034] like Figure 1 As shown in FIG. 1 , the electronic system 1 according to an embodiment of the present disclosure may include a controller 10 and an electronic device 20 . The electronic device 20 may include a PLL clock generating circuit (PLL_CLK GEN) 230 .

[0035] The controller 10 may include a first control pin 11_1, a second control pin 11_2, a third control pin 11_3, a fourth control pin 11_4, a fifth control pin 11_5, and a sixth control pin 11_6. The electronic device 20 may include a first device pin 21_1, a second device pin 21_2, a third device pin 21_3, a fourth device pin 21_4, a fifth device pin 21_5, and a sixth device pin 21_6. The first transmission line L11 may be connected between the first control pin 11_1 and the first device pin 21_1. The second transmission line L12 may be connected between the second control pin 11_2 and the second device pin 21_2. The third transmission line L13 may be connected between the third control pin 11_3 and the third device pin 21_3. The fourth transmission line L14 may be connected between the fourth control pin 11_4 and the fourth device pin 21_4. The fifth transmission line L15 may be connected between the fifth control pin 11_5 and the fifth device pin 21_5. The sixth transmission line L16 may be connected between the sixth control pin 11_6 and the sixth device pin 21_6 .

[0036] The controller 10 may transmit a command address CA for controlling the electronic device 20 to the electronic device 20 through the first transmission line L11. The controller 10 may transmit a clock CLK to the electronic device 20 through the second transmission line L12. The controller 10 may transmit a compensation code RCD to the electronic device 20 through the third transmission line L13. The controller 10 may transmit an offset code FCD to the electronic device 20 through the fourth transmission line L14. The controller 10 may transmit data DATA to the electronic device 20 through the fifth transmission line L15. The controller 10 may receive data DATA from the electronic device 20 through the fifth transmission line L15. The controller 10 may receive a phase lock signal PLL_LK from the electronic device 20 through the sixth transmission line L16. The controller 10 may detect that a PLL clock ( Figure 2 The command address CA may include a plurality of bits and may be set to a signal including a command and an address for controlling the operation of the electronic device 20. The clock CLK may be set to a signal that is periodically triggered so as to synchronize the operations of the controller 10 and the electronic device 20. The compensation code RCD may include a plurality of bits and may be set to a signal for setting a first setting period for detecting the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 The offset code FCD may include a plurality of bits and may be set to a signal for setting a second setting period, the second setting period being used to detect the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3The first setting period and the second setting period may be set to different periods. The first setting period may be set to a period shorter than the second setting period. The data DATA may include a plurality of bits. The plurality of bits may be input and output in series. The phase lock signal PLL_LK may be set to indicate that a PLL clock ( Figure 2 A signal that determines the phase of the PLL_CLK in the circuit.

[0037] The PLL clock generation circuit 230 can generate a PLL clock ( Figure 2 , so that the PLL clock is generated within the target period ( Figure 2 After the initial operation starts, the PLL clock generation circuit 230 can set a first setting period based on the compensation code RCD for detecting the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 The phase difference of FCLK in the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference of the reference clock FCLK in the output is equal to or less than the first phase difference, the phase lock signal PLL_LK is generated. After outputting the phase lock signal PLL_LK, the PLL clock generation circuit 230 can set a second setting period based on the offset code FCD for detecting the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 The phase difference of FCLK in the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference of the reference clock ( FCLK in ) is less than the second phase difference (the second phase difference is greater than the first phase difference), the phase lock signal PLL_LK is generated, and when the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference of the FCLK in the electronic device 20 is equal to or greater than the second phase difference (the second phase difference is greater than the first phase difference), the generation of the phase lock signal PLL_LK is stopped. The initial operation can be set to an operation performed before performing the normal operation of the electronic device 20. The normal operation may include a write operation and a read operation of the electronic device 20.

[0038] The electronic device 20 can generate a PLL clock ( Figure 2 , so that the PLL clock is generated within the target period ( Figure 2 After the initial operation starts, the electronic device 20 can set a first setting period based on the compensation code RCD for detecting the phase of the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 The phase difference of FCLK in the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference of the reference clock FCLK in the output is equal to or less than the first phase difference, the phase lock signal PLL_LK is generated. After outputting the phase lock signal PLL_LK, the electronic device 20 can set a second setting period based on the offset code FCD for detecting the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 The phase difference of the FCLK in the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference of the FCLK in the PLL is equal to or greater than the second phase difference, the generation of the phase lock signal PLL_LK is stopped, and the second phase difference is greater than the first phase difference. After the writing operation of the normal operation starts, the electronic device 20 can communicate with the PLL clock ( Figure 2 After the normal operation of the read operation starts, the electronic device 20 can synchronize with the PLL clock ( Figure 2 The data DATA is output synchronously with the PLL_CLK in the circuit.

[0039] like Figure 2 As shown, the electronic device 20 according to an embodiment of the present disclosure may include a command generation circuit (CMD GEN) 210, an internal address generation circuit (IADD GEN) 220, a PLL clock generation circuit (PLL_CLK GEN) 230, a data input and output circuit (data I / O) 240 and a storage circuit 250.

[0040] The command generation circuit 210 can generate a write command WT and a read command RD based on the first to Lth command addresses CA<1:L> in synchronization with the clock CLK. The command generation circuit 210 can generate a write command WT that is enabled when the first to Lth command addresses CA<1:L> input in synchronization with the clock CLK have a logic level combination for performing a write operation. The command generation circuit 210 can generate a read command RD that is enabled when the first to Lth command addresses CA<1:L> input in synchronization with the clock CLK have a logic level combination for performing a read operation. The first to Lth command addresses CA<1:L> may include commands for controlling the write operation and the read operation of the electronic device 20 and addresses for selecting storage cells to perform the write operation and the read operation. The number of bits of the first to Lth command addresses CA<1:L> may be set to a variety of bit numbers according to the embodiment. The number of bits "L" of the first to Lth command addresses CA<1:L> may be set to a positive integer.

[0041] The internal address generation circuit 220 may generate the first to Mth internal addresses IADD<1:M> based on the first to Lth command addresses CA<1:L> in synchronization with the clock CLK. The internal address generation circuit 220 may generate the first to Mth internal addresses IADD<1:M> by decoding the first to Lth command addresses CA<1:L> in synchronization with the clock CLK. The number of bits of the first to Mth internal addresses IADD<1:M> may be set to a variety of number of bits according to the embodiment. The number of bits "M" of the first to Mth internal addresses IADD<1:M> may be set to a positive integer.

[0042] The PLL clock generation circuit 230 can generate the PLL clock PLL_CLK so that the phase of the PLL clock PLL_CLK is generated within the target period. After the initial operation starts, the PLL clock generation circuit 230 can set the first setting period for detecting the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 The phase difference of FCLK in the first setting period can be obtained when the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 After outputting the phase lock signal PLL_LK, the PLL clock generation circuit 230 can: set a second setting period based on the first to fourth offset codes FCD<1:4> for detecting the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 During the second setup period, when the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference between the reference clock (FCLK in ( )) is less than a second phase difference greater than the first phase difference, a phase lock signal PLL_LK is generated; and during the second setting period when the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference of the reference clock ( FCLK in ) is equal to or greater than a second phase difference greater than the first phase difference, the generation of the phase lock signal PLL_LK is stopped. The operation of generating the PLL clock PLL_CLK by the PLL clock generating circuit 230 so that the phase of the PLL clock PLL_CLK is generated within the target period may mean controlling the phase of the PLL clock PLL_CLK so that the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 The phase lock signal PLL_LK can be set to generate a PLL clock (FCLK) in the target period when the phase difference is less than the first phase difference. Figure 2The signal is enabled when the phase of PLL_CLK in the PLL is set.

[0043] After the write operation starts, the data input-output circuit 240 may sequentially latch the first to Nth data DATA<1:N> in synchronization with the rising and falling edges of the PLL clock PLL_CLK, and may generate the first to Nth internal data ID<1:N> by aligning the first to Nth data DATA<1:N> that have been latched in synchronization with the rising and falling edges of the PLL clock PLL_CLK. The first to Nth data DATA<1:N> may be input from the controller 10 after the write operation starts. After the read operation starts, the data input-output circuit 240 may latch the first to Nth internal data ID<1:N> in synchronization with the rising and falling edges of the PLL clock PLL_CLK, and may generate the first to Nth data DATA<1:N> by serializing the first to Nth internal data ID<1:N> that have been latched in synchronization with the rising and falling edges of the PLL clock PLL_CLK. After the read operation starts, the first to Nth data DATA<1:N> may be output to the controller 10. The first to Nth data DATA<1:N> may be input and output in series. The first to Nth internal data ID<1:N> may be generated in parallel. The number of bits of each of the first to Nth data DATA<1:N> and the first to Nth internal data ID<1:N> may be set to a variety of number of bits according to an embodiment. The number of bits "N" of each of the first to Nth data DATA<1:N> and the first to Nth internal data ID<1:N> may be set to a positive integer.

[0044] The memory circuit 250 may include a plurality of memory cells MC. When a write command WT is enabled, the memory circuit 250 may store the first to Nth internal data ID<1:N> in the memory cells MC selected by the first to Mth internal addresses IADD<1:M>. When a read command RD is enabled, the memory circuit 250 may output the first to Nth internal data ID<1:N> stored in the memory cells MC selected by the first to Mth internal addresses IADD<1:M>.

[0045] After the initial operation starts, the electronic device 20 may set a first setting period for detecting the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 and during the first setup period when the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3When the phase difference of the reference clock FCLK in the output is equal to or less than the first phase difference, the phase lock signal PLL_LK can be generated. After outputting the phase lock signal PLL_LK, the electronic device 20 can set a second setting period for detecting the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 and during the second setup period when the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference of the FCLK in the PLL clock (PLL_CLK) is equal to or greater than a second phase difference greater than the first phase difference, the generation of the phase lock signal PLL_LK may be stopped. After the write operation of the normal operation starts, the electronic device 20 may store the first to Nth data DATA<1:N> in synchronization with the PLL clock PLL_CLK. After the read operation of the normal operation starts, the electronic device 20 may output the first to Nth data DATA<1:N> in synchronization with the PLL clock PLL_CLK.

[0046] Figure 3 2 is a block diagram showing a structure according to an embodiment of a PLL clock generating circuit 230 included in the electronic device 20. The PLL clock generating circuit 230 may include a PLL circuit (PLL) 300, a replica circuit (REP CP) 310, a phase detection circuit (PH DET) 320, and a phase lock signal generating circuit (PLL LK GEN) 330.

[0047] The PLL circuit 300 may generate a PLL clock PLL_CLK so that the phase of the PLL clock PLL_CLK is generated within a target period. The PLL circuit 300 may adjust the phase of the PLL clock PLL_CLK so that the phase difference between the reference clock RCLK generated from the PLL clock PLL_CLK and the feedback clock FCLK is less than the first phase difference. The PLL circuit 340 may be implemented with a common phase-locked loop (PLL).

[0048] The replica circuit 310 may generate a reference clock RCLK by receiving the PLL clock PLL_CLK. The reference clock RCLK may have the same phase as the PLL clock PLL_CLK. The replica circuit 310 may generate a feedback clock FCLK by delaying the reference clock RCLK based on an internal jitter value. The replica circuit 310 may generate a feedback clock FCLK by delaying the reference clock RCLK by the same delay amount as the delay amount of the internal jitter value.

[0049] The phase detection circuit 320 can generate a first drive control signal UP and a second drive control signal DN by detecting the phase difference between the reference clock RCLK and the feedback clock FCLK. The phase detection circuit 320 can generate the first drive control signal UP and the second drive control signal DN based on the detection result of the phase difference between the reference clock RCLK and the feedback clock FCLK. The phase detection circuit 320 can generate the first drive control signal UP that is enabled when the phase of the reference clock RCLK is earlier than the phase of the feedback clock FCLK. The phase detection circuit 320 can generate the second drive control signal DN that is enabled when the phase of the feedback clock FCLK is earlier than the phase of the reference clock RCLK.

[0050] After the initial operation starts, the phase lock signal generating circuit 330 can: set a first setting period for detecting the phase difference between the reference clock RCLK and the feedback clock FCLK based on the first drive control signal UP, the second drive control signal DN and the first to fourth compensation codes RCD<1:4>; during the first setting period, when the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference of the reference clock ( FCLK in ) is equal to or less than the first phase difference, an enabled phase lock signal PLL_LK is generated; and during the first setting period, when the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference between the reference clock RCLK and the feedback clock FCLK is greater than the first phase difference, a disabled phase lock signal PLL_LK is generated. After outputting the phase lock signal PLL_LK, the phase lock signal generation circuit 330 may: set a second setting period for detecting the phase difference between the reference clock RCLK and the feedback clock FCLK based on the first drive control signal UP, the second drive control signal DN, and the first to fourth offset codes FCD<1:4>; during the second setting period, when the reference clock ( Figure 3 RCLK in) and the feedback clock ( Figure 3 When the phase difference between the reference clock (FCLK in ( )) is less than a second phase difference greater than the first phase difference, an enabled phase lock signal PLL_LK is generated; during the second setting period, when the reference clock ( Figure 3 FCLK in) and feedback clock ( Figure 3 When the phase difference between the reference clock (FCLK in ( )) is equal to or greater than a second phase difference greater than the first phase difference, a disabled phase lock signal PLL_LK is generated; and during the second setting period when the reference clock ( Figure 3 FCLK in) and feedback clock ( Figure 3 When the phase difference between the FCLK in the control signal PLL and the control signal FCLK in the control signal PLL_LK is equal to or greater than a second phase difference that is larger than the first phase difference, generation of the phase lock signal PLL_LK is stopped.

[0051] Figure 4 is a block diagram showing a structure according to an embodiment of a phase detection circuit 320 included in the PLL clock generation circuit 230. The phase detection circuit 320 may include a reference clock phase control circuit (RCLK PH CTR) 321, a feedback clock phase control circuit (FCLK PH CTR) 322, and a reset signal generation circuit (RST GEN) 323.

[0052] The reference clock phase control circuit 321 may generate a reference setting signal RS, a first pre-drive control signal PUP, and a first drive control signal UP based on the reference clock RCLK and the reset signal RST. The reference clock phase control circuit 321 may generate a reference setting signal RS that is enabled when the level of the reference clock RCLK changes from a first logic level (logic low level) to a second logic level (logic high level). The reference clock phase control circuit 321 may generate a first pre-drive control signal PUP that is enabled when the reference setting signal RS is enabled and disabled when the reset signal RST is enabled. The reference clock phase control circuit 321 may generate a first drive control signal UP based on the reference setting signal RS, the first pre-drive control signal PUP, and the reset signal RST.

[0053] The feedback clock phase control circuit 322 can generate a feedback setting signal FS, a second pre-drive control signal PDN, and a second drive control signal DN based on the feedback clock FCLK and the reset signal RST. The feedback clock phase control circuit 322 can generate a feedback setting signal FS that is enabled when the level of the feedback clock FCLK changes from a first logic level (logic low level) to a second logic level (logic high level). The feedback clock phase control circuit 322 can generate a second pre-drive control signal PDN that is enabled when the feedback setting signal FS is enabled and disabled when the reset signal RST is enabled. The feedback clock phase control circuit 322 can generate a second drive control signal DN based on the feedback setting signal FS, the second pre-drive control signal PDN, and the reset signal RST.

[0054] The reset signal generating circuit 323 may generate a reset signal RST based on the reference setting signal RS, the first pre-driving control signal PUP, the feedback setting signal FS, and the second pre-driving control signal PDN. The reset signal generating circuit 323 may generate a reset signal RST that is enabled when the reference setting signal RS, the first pre-driving control signal PUP, the feedback setting signal FS, and the second pre-driving control signal PDN are all enabled.

[0055] Figure 5is a circuit diagram showing a structure according to an embodiment of a reference clock phase control circuit 321 included in the phase detection circuit 320. The reference clock phase control circuit 321 may include a first driving control signal generating circuit 321_1 and a first pre-driving control signal generating circuit 321_2.

[0056] The first driving control signal generating circuit 321_1 can use the inverter 321 <1> And NAND gate 321 <2> and 321 <3> to be implemented. When the level of the reference clock RCLK changes from a logic low level to a logic high level, the first drive control signal generating circuit 321_1 may generate a reference setting signal RS enabled to a logic high level. When both the reference setting signal RS and the first pre-drive control signal PUP are enabled to a logic high level during a period in which the reset signal RST is disabled to a logic high level, the first drive control signal generating circuit 321_1 may generate a first drive control signal UP enabled to a logic low level. When at least one of the reset signal RST, the reference setting signal RS, and the first pre-drive control signal PUP is generated to have a logic low level, the first drive control signal generating circuit 321_1 may generate a first drive control signal UP disabled to a logic high level.

[0057] The first pre-driving control signal generating circuit 321_2 can be formed by using a NAND gate 321 <4> and 321 <5> to be implemented. The first pre-drive control signal generating circuit 321_2 may generate a first pre-drive control signal PUP based on a reference setting signal RS and a reset signal RST. When the level of the reference setting signal RS is a logic low level, the first pre-drive control signal generating circuit 321_2 may generate a first pre-drive control signal PUP enabled to a logic high level. When the level of the reference setting signal RS is a logic low level, the first pre-drive control signal generating circuit 321_2 may generate a first pre-drive control signal PUP enabled to a logic high level. When the level of the reference setting signal RS is a logic high level and the level of the reset signal RST is a logic low level, the first pre-drive control signal generating circuit 321_2 may generate a first pre-drive control signal PUP disabled to a logic low level.

[0058] Figure 6 is a circuit diagram showing a structure according to an embodiment of a feedback clock phase control circuit 322 included in the phase detection circuit 320. The feedback clock phase control circuit 322 may include a second driving control signal generating circuit 322_1 and a second pre-driving control signal generating circuit 322_2.

[0059] The second driving control signal generating circuit 322_1 can use the inverter 322 <1> and NAND gate 322 <2> and 322 <3> to be implemented. When the level of the feedback clock FCLK changes from a logic low level to a logic high level, the second drive control signal generating circuit 322_1 may generate a feedback setting signal FS enabled to a logic high level. When both the feedback setting signal FS and the second pre-drive control signal PDN are enabled to a logic high level during a period in which the reset signal RST is disabled to a logic high level, the second drive control signal generating circuit 322_1 may generate a second drive control signal DN enabled to a logic low level. When at least one of the reset signal RST, the feedback setting signal FS, and the second pre-drive control signal PDN is generated to have a logic low level, the second drive control signal generating circuit 322_1 may generate a second drive control signal DN disabled to a logic high level.

[0060] The second pre-driving control signal generating circuit 322_2 can be formed by using a NAND gate 322 <4> and 322 <5> The second pre-driver control signal generating circuit 322_2 may generate a second pre-driver control signal PDN based on the feedback setting signal FS and the reset signal RST. When the level of the feedback setting signal FS is a logic low level, the second pre-driver control signal generating circuit 322_2 may generate a second pre-driver control signal PDN enabled to a logic high level. When the level of the feedback setting signal FS is a logic high level and the level of the reset signal RST is a logic low level, the second pre-driver control signal generating circuit 322_2 may generate a second pre-driver control signal PDN disabled to a logic low level.

[0061] Figure 7 is a circuit diagram showing a structure according to an embodiment of the reset signal generation circuit 323 included in the phase detection circuit 320 .

[0062] The reset signal generating circuit 323 can be a NAND gate 323 <1> and inverter 323 <2> and 323 <3> When the reference setting signal RS, the first pre-driving control signal PUP, the feedback setting signal FS, and the second pre-driving control signal PUP are all enabled to a logic high level, the reset signal generating circuit 323 may generate a reset signal RST enabled to a logic low level. When the level of at least one of the reference setting signal RS, the first pre-driving control signal PUP, the feedback setting signal FS, and the second pre-driving control signal PDN is a logic low level, the reset signal generating circuit 323 may generate a reset signal RST disabled to a logic high level.

[0063] Figure 8 is a timing chart for describing the operation of the phase detection circuit 320 according to an embodiment of the present disclosure. Figure 8The operation of the phase detection circuit 320 is described below. The operation of the phase detection circuit 320 when the phase of the reference clock RCLK is earlier than the phase of the feedback clock FCLK is described below.

[0064] At timing T1 , the level of the reference clock RCLK may transition from a logic low level to a logic high level.

[0065] When the level of the reference clock RCLK changes from a logic low level to a logic high level, the first drive control signal generating circuit 321_1 of the reference clock phase control circuit 321 may generate a reference setting signal RS (not shown) enabled to a logic high level. The first drive control signal generating circuit 321_1 may generate a first drive control signal UP enabled to a logic low level based on the reference setting signal RS and the first pre-drive control signal PUP (not shown) both enabled to a logic high level during a period in which the reset signal RST is disabled to a logic high level.

[0066] At the timing T2 , the level of the feedback clock FCLK may transition from a logic low level to a logic high level.

[0067] When the level of the feedback clock FCLK changes from a logic low level to a logic high level, the second drive control signal generating circuit 322_1 of the feedback clock phase control circuit 322 may generate a feedback setting signal FS (not shown) enabled to a logic high level. The first drive control signal generating circuit 321_1 may generate a second drive control signal DN enabled to a logic low level based on the feedback setting signal FS and the second pre-drive control signal PDN (not shown) both enabled to a logic high level during a period in which the reset signal RST is disabled to a logic high level.

[0068] When the reference setup signal RS, the first pre-driving control signal PUP, the feedback setup signal FS, and the second pre-driving control signal PUP are all enabled to a logic high level, the reset signal generating circuit 323 may generate a reset signal RST enabled to a logic low level.

[0069] At timing T3, the first driving control signal generating circuit 321_1 may generate the first driving control signal UP disabled to a logic high level by the reset signal RST enabled to a logic low level at timing T2. The first driving control signal generating circuit 321_1 may generate the first pre-driving control signal PUP disabled to a logic low level by the reset signal RST enabled to a logic low level at timing T2.

[0070] The second driving control signal generating circuit 322_1 may generate the second driving control signal DN disabled to a logic high level by the reset signal RST enabled to a logic low level at timing T2. The second driving control signal generating circuit 322_1 may generate the second pre-driving control signal PDN disabled to a logic low level by the reset signal RST enabled to a logic low level at timing T2.

[0071] The reset signal generating circuit 323 may generate a reset signal RST disabled to a logic high level based on the first pre-driving control signal PUP having a logic low level and the second pre-driving control signal PDN having a logic low level.

[0072] The phase detection circuit 320 may generate a first driving control signal UP that is enabled when the phase of the reference clock RCLK is earlier than the phase of the feedback clock FCLK, and may generate a second driving control signal DN that is disabled when the phase of the reference clock RCLK is earlier than the phase of the feedback clock FCLK.

[0073] Fig. 9 is a timing chart for describing the operation of the phase detection circuit 320 according to an embodiment of the present disclosure. Fig. 9 The operation of the phase detection circuit 320 is described below. The operation of the phase detection circuit 320 when the phase of the feedback clock FCLK is earlier than the phase of the reference clock RCLK is described below.

[0074] At timing T5 , the level of the feedback clock FCLK may transition from a logic low level to a logic high level.

[0075] When the level of the feedback clock FCLK changes from a logic low level to a logic high level, the second driving control signal generating circuit 322_1 of the feedback clock phase control circuit 322 may generate a feedback setting signal FS enabled to a logic high level. The first driving control signal generating circuit 321_1 may generate a second driving control signal DN enabled to a logic low level based on the feedback setting signal FS and the second pre-driving control signal PDN being enabled to a logic high level during a period in which the reset signal RST is disabled to a logic high level.

[0076] At timing T6 , the level of the reference clock RCLK may transition from a logic low level to a logic high level.

[0077] When the level of the reference clock RCLK changes from a logic low level to a logic high level, the first drive control signal generating circuit 321_1 of the reference clock phase control circuit 321 may generate a reference setting signal RS enabled to a logic high level. The first drive control signal generating circuit 321_1 may generate a first drive control signal UP enabled to a logic low level based on the reference setting signal RS and the first pre-drive control signal PUP being enabled to a logic high level during a period in which the reset signal RST is disabled to a logic high level.

[0078] When the reference setup signal RS, the first pre-driving control signal PUP, the feedback setup signal FS, and the second pre-driving control signal PDN are all enabled to a logic high level, the reset signal generation circuit 323 may generate a reset signal RST enabled to a logic low level.

[0079] At timing T7, the first driving control signal generating circuit 321_1 may generate the first driving control signal UP disabled to a logic high level by the reset signal RST enabled to a logic low level at timing T6. The first driving control signal generating circuit 321_1 may generate the first pre-driving control signal PUP disabled to a logic low level by the reset signal RST enabled to a logic low level at timing T6.

[0080] The second driving control signal generating circuit 322_1 may generate the second driving control signal DN disabled to a logic high level by the reset signal RST enabled to a logic low level at timing T6. The second driving control signal generating circuit 322_1 may generate the second pre-driving control signal PDN disabled to a logic low level by the reset signal RST enabled to a logic low level at timing T6.

[0081] The reset signal generating circuit 323 may generate a reset signal RST disabled to a logic high level based on the first pre-driving control signal PUP having a logic low level and the second pre-driving control signal PDN having a logic low level.

[0082] The phase detection circuit 320 may generate a second driving control signal DN enabled when the phase of the feedback clock FCLK is earlier than the phase of the reference clock RCLK, and may generate a first driving control signal UP disabled when the phase of the feedback clock FCLK is earlier than the phase of the reference clock RCLK.

[0083] Fig.10is a block diagram showing a structure according to an embodiment of a phase lock signal generating circuit 330 included in the PLL clock generating circuit 230. The phase lock signal generating circuit 330 may include an initial detection signal generating circuit (FDET GEN) 331, an operation detection signal generating circuit (CDET GEN) 332, and a latch circuit (LAT CT) 333.

[0084] During the first setting period after the initial operation starts, the initial detection signal generating circuit 331 may generate the initial detection signal FDET by detecting the number of triggering times of the reference clock RCLK based on the first drive control signal UP, the second drive control signal DN, and the first to fourth compensation codes RCD<1:4>. After the initial operation starts, the initial detection signal generating circuit 331 may set the first setting period based on the first drive control signal UP, the second drive control signal DN, and the first to fourth compensation codes RCD<1:4>. During the first setting period, the initial detection signal generating circuit 331 may generate the initial detection signal FDET that is enabled when the phase difference between the reference clock RCLK and the feedback clock FCLK is equal to or less than the first phase difference, and may generate the initial detection signal FDET that is disabled when the phase difference between the reference clock RCLK and the feedback clock FCLK is less than the first phase difference.

[0085] The operation detection signal generating circuit 332 may generate the operation detection signal CDET by detecting the number of triggering times of the reference clock RCLK during the second setting period based on the first drive control signal UP, the second drive control signal DN, and the first to fourth offset codes FCD<1:4>. The operation detection signal generating circuit 332 may set the second setting period based on the first drive control signal UP, the second drive control signal DN, and the first to fourth offset codes FCD<1:4>. During the second setting period, the operation detection signal generating circuit 332 may generate the operation detection signal CDET that is enabled when the difference between the phases of the reference clock RCLK and the feedback clock FCLK is less than a second phase difference that is larger than the first phase difference, and may generate the operation detection signal CDET that is disabled when the difference between the phases of the reference clock RCLK and the feedback clock FCLK is equal to or larger than the second phase difference that is larger than the first phase difference.

[0086] The latch circuit 333 may be directly electrically connected to the initial detection signal generating circuit 331 and may receive the initial detection signal FDET. The latch circuit 333 may be directly electrically connected to the operation detection signal generating circuit 332 and may receive the operation detection signal CDET. Based on the initial detection signal FDET and the operation detection signal CDET, the latch circuit 333 may generate a phase lock signal PLL_LK, which generates a PLL clock ( Figure 2The latch circuit 333 may be enabled when the phase of the PLL_CLK in the initial detection signal FDET is changed. When both the initial detection signal FDET and the operation detection signal CDET are enabled, the latch circuit 333 may generate the phase lock signal PLL_LK. When the operation detection signal CDET is disabled after the initial detection signal FDET is enabled, the latch circuit 333 may stop generating the phase lock signal PLL_LK.

[0087] Reference Figures 11 to 13 The first setting period, the second setting period, the first phase difference, and the second phase difference are described in detail.

[0088] Fig.11 is a block diagram showing a structure according to an embodiment of an initial detection signal generating circuit 331 included in the phase lock signal generating circuit 330. The initial detection signal generating circuit 331 may include a first setting signal generating circuit (SET GEN) 410 and a first period setting circuit (PERIOD SET) 420.

[0089] The first setting signal generating circuit 410 can generate a first internal pulse ( Fig.12 The first setting signal generating circuit 410 can generate the first internal pulse ( Fig.12 IP in) delays the first setting period to generate the first selection pulse ( Fig.12 The first setting signal generating circuit 410 may generate a first setting signal based on the first selection pulse ( Fig.12 SP in) and the first internal pulse ( Fig.12 IP in generates a first setting signal SET.

[0090] The first period setting circuit 420 may generate an initial detection signal FDET based on the first setting signal SET and the reference clock RCLK. When the reference clock RCLK is triggered a set number of times, the first period setting circuit 420 may generate an initial detection signal FDET that is enabled when the first setting signal SET is disabled. When the reference clock RCLK is triggered a set number of times, the first period setting circuit 420 may generate an initial detection signal FDET that is disabled when the first setting signal SET is enabled.

[0091] Fig.12 is a diagram showing a structure according to an embodiment of a first setting signal generating circuit 410 included in the initial detection signal generating circuit 331. The first setting signal generating circuit 410 may include a first signal synthesizing circuit 411, a first delay circuit 412, and a first selection transfer circuit (SEL TR) 413.

[0092] The first signal synthesis circuit 411 can be formed by using a NAND gate 411 <1> and 411 <2> , Inverter 411 <3> AND NOR gate 411 <4> The first signal synthesis circuit 411 may generate a first internal pulse IP by synthesizing the first drive control signal UP and the second drive control signal DN. The first signal synthesis circuit 411 may generate a first internal pulse IP having a logic high level by synthesizing during a period when the first drive control signal UP is enabled to a logic low level and a period when the second drive control signal DN is enabled to a logic low level. The first signal synthesis circuit 411 may generate a first setting signal SET by synthesizing the first internal pulse IP and the first selection pulse SP. The first signal synthesis circuit 411 may generate a first setting signal SET having a logic low level by synthesizing during a period when the first internal pulse IP is enabled to a logic high level and a period when the first selection pulse SP is enabled to a logic high level. Before the initial operation, when the initialization signal INIT is enabled to a logic high level, the first signal synthesis circuit 411 may generate a first setting signal SET initialized to a logic low level.

[0093] The first delay circuit 412 may include a first unit delayer DLY1 to a sixteenth unit delayer DLY16. The first to sixteenth unit delayers DLY1 to DLY16 may respectively generate first to sixteenth delayed signals D1 to D16 by sequentially delaying the first internal pulse IP. Each of the first to sixteenth unit delayers DLY1 to DLY16 included in the first delay circuit 412 may be implemented using a common delayer that outputs an input signal by delaying the input signal by the same delay amount. The delay amount of each of the first to sixteenth unit delayers DLY1 to DLY16 may be set differently according to embodiments.

[0094] The first selection transfer circuit 413 may output one of the first to sixteenth delayed signals D1 to D16 as a first selection pulse SP based on a logic level combination of the first to fourth compensation codes RCD<1:4>. For example, when the first to sixteenth delayed signals D1 to D16 are "0, 0, 0, 0", the first selection transfer circuit 413 may output the first delayed signal D1 as a first selection pulse SP. When the first to sixteenth delayed signals D1 to D16 are "0, 0, 0, 1", the first selection transfer circuit 413 may output the second delayed signal D2 as a first selection pulse SP. When the first to sixteenth delayed signals D1 to D16 are "1, 1, 1, 1", the first selection transfer circuit 413 may output the sixteenth delayed signal D16 as a first selection pulse SP.

[0095] Fig.133 is a block diagram showing a structure according to an embodiment of a first period setting circuit 420 included in the initial detection signal generating circuit 331. The first period setting circuit 420 may include first to sixth counters 421 to 426 and a first detection signal output circuit 427.

[0096] The first counter 421 may include an adder 421_1 and a flip-flop 421_2. The adder 421_1 may generate a first sum signal S1 and a first carry signal C1 by adding a power supply voltage VDD and a first transfer signal Q1. When the level of the reference clock RCLK transitions to a logic low level, the flip-flop 421_2 may output the first sum signal S1 as the first transfer signal Q1 by inverting the first sum signal S1. Whenever the level of the reference clock RCLK transitions to a logic low level twice, the first counter 421 may generate a first carry signal C1 having a logic high level by performing an addition operation.

[0097] The second counter 422 may include an adder 422_1 and a flip-flop 422_2. The adder 422_1 may generate a second sum signal S2 and a second carry signal C2 by adding the first carry signal C1 and the second transfer signal Q2. When the level of the reference clock RCLK is changed to a logic low level, the flip-flop 422_2 may output the second sum signal S2 as the second transfer signal Q2 by inverting the second sum signal S2. Whenever the level of the reference clock RCLK is changed to a logic low level for the fourth time, the second counter 422 may generate a second carry signal C2 having a logic high level by performing an addition operation.

[0098] The third to fifth counters 423 to 425 may each perform the same operation as the second counter 422 except for their input signals and output signals, and a detailed description thereof has been omitted.

[0099] The sixth counter 426 may include an adder (ADDER) 426_1 and a flip-flop 426_2. The adder 426_1 may generate a sixth sum signal S6 and a sixth carry signal C6 by adding the fifth carry signal C5 and the sixth transfer signal Q6. When the level of the reference clock RCLK is changed to a logic low level, the flip-flop 426_2 may output the sixth sum signal S6 as the sixth transfer signal Q6 by inverting the sixth sum signal S6. Whenever the level of the reference clock RCLK is changed to a logic low level for the twelfth time, the sixth counter 426 may generate a sixth carry signal C6 having a logic high level by performing an addition operation.

[0100] The first to sixth counters 421 to 426 may be provided as a first group of counters.

[0101] The first detection signal output circuit 427 may include flip-flops 427_1 and 427_2. When the level of the reference clock RCLK is turned to a logic low level during a period in which the first setting signal SET having a logic low level is generated, the flip-flop 427_1 may output the sixth carry signal S6 as the seventh carry signal Q7 by inverting the sixth carry signal S6. When the first setting signal SET having a logic high level is generated, the flip-flop 427_1 may generate the seventh carry signal Q7 having a logic low level. When the level of the seventh carry signal Q7 is turned to a logic low level during a period in which the first setting signal SET having a logic low level is generated, the flip-flop 427_2 may output the power supply voltage VDD as the initial detection signal FDET. When the first setting signal SET having a logic high level is generated, the flip-flop 427_2 may generate the initial detection signal FDET having a logic low level.

[0102] The first setting period may refer to a period from the time when the first internal pulse IP with a logic high level is generated to the time when the first selection pulse SP with a logic high level is generated. The first phase difference may refer to the time when the first setting signal SET is prohibited to the logic low level until the level of the reference clock RCLK is changed to a logic low level for the twelfth time (i.e., the number of settings). That is, when the level of the reference clock RCLK is changed to a logic low level for the twelfth time, the initial detection signal generating circuit 331 may generate an initial detection signal FDET with a logic high level when the first setting signal SET with a logic low level is generated, and may generate an initial detection signal FDET with a logic low level when the first setting signal SET with a logic high level is generated. The first setting period may be adjusted to a combination of the logic levels of the first to fourth compensation codes RCD<1:4>. The number of settings may be adjusted to correspond to the number of counters. The first setting period and the number of settings may be set differently according to the embodiment.

[0103] Fig.10 The operation detection signal generating circuit 332 shown can be implemented as the same circuit as the initial detection signal generating circuit 331, and can perform the same operation as the initial detection signal generating circuit 331, except that the operation detection signal generating circuit 332 receives the first to fourth offset codes FCD<1:4> to set the second setting period of the initial detection signal generating circuit 331, and the second setting period is greater than the first setting period. Therefore, a detailed description of the operation detection signal generating circuit 332 is omitted.

[0104] The second setting period may mean the period from the time when the first internal pulse IP with a logic high level is generated to the time when the first selection pulse SP with a logic high level is generated. The second phase difference may refer to the time when the first setting signal SET is prohibited to the logic low level until the level of the reference clock RCLK is changed to a logic low level for the twelfth time (i.e., the number of settings). That is, when the level of the reference clock RCLK is changed to a logic low level for the twelfth time, the operation detection signal generating circuit 332 may generate an operation detection signal CDET with a logic high level when the first setting signal SET with a logic low level is generated. When the level of the reference clock RCLK is changed to a logic low level for the twelfth time, the operation detection signal generating circuit 332 may generate an operation detection signal CDET with a logic low level when the first setting signal SET with a logic high level is generated. The second setting period may be adjusted to a combination of the logic levels of the first to fourth offset codes FCD<1:4>. The number of settings may be adjusted to correspond to the number of counters. The second setting period and the number of settings may be set differently according to the embodiment.

[0105] Fig.14 4 is a circuit diagram showing a configuration according to an embodiment of an adder 421_1 included in the first counter 421.

[0106] The adder 421_1 can be implemented using an XOR gate 421 <1> and 421 <2> , AND gate 421 <3> and 421 <4> AND OR gate 421 <5> The adder 421_1 may generate a first sum signal S1 and a first carry signal C1 by performing an addition operation on the power supply voltage VDD and the first transfer signal Q1.

[0107] For example, the operation of the first counter 421 when the level of the reference clock RCLK transitions to a logic low level for the first time and when the level of the reference clock RCLK transitions to a logic low level for the second time is described as follows.

[0108] When the level of the reference clock RCLK first transitions to a logic low level, the adder 421_1 may generate a first sum signal S1 having a logic high level and a first carry signal C1 having a logic low level by performing an addition operation on the power supply voltage VDD and the first transfer signal Q1 having a logic low level.

[0109] When the level of the reference clock RCLK transitions to a logic low level for the second time, the adder 421_1 may generate a first sum signal S1 having a logic low level and a first carry signal C1 having a logic high level by performing an addition operation on the power supply voltage VDD and the first transfer signal Q1 having a logic high level.

[0110] That is, whenever the level of the reference clock RCLK transitions to a logic low level for the second time, the first counter 421 may generate the first carry signal C1 having a logic high level by performing an addition operation.

[0111] Fig.15 is a table for describing first and second setting periods according to first to fourth compensation codes RCD<1:4> and first to fourth offset codes FCD<1:4> according to an embodiment of the present disclosure.

[0112] First, an operation of setting a first setting period based on a logic level combination of the first to fourth compensation codes RCD<1:4> is described as follows.

[0113] When the first to fourth compensation codes RCD<1:4> have a logic level combination of "0, 0, 0, 0", the first setup period may be set to 0.35 ns. The case where the first setup period is 0.35 ns may refer to the case where a period from when the first internal pulse IP having a logic high level is generated to when the first selection pulse SP having a logic high level is generated is 0.35 ns.

[0114] When the first to fourth compensation codes RCD<1:4> have a logic level combination of "0, 0, 0, 1", the first setting period may be set to 0.70ns. The case where the first setting period is 0.70ns may refer to the case where the period from the time when the first internal pulse IP having a logic high level is generated to the time when the first selection pulse SP having a logic high level is generated is 0.70ns.

[0115] When the first to fourth compensation codes RCD<1:4> have a logic level combination of "1, 1, 1, 1", the first setup period may be set to 5.62ns. The case where the first setup period is 5.62ns may refer to the case where a period from when the first internal pulse IP having a logic high level is generated to when the first selection pulse SP having a logic high level is generated is 5.62ns.

[0116] As described above, the first setting period may be differently set based on a combination of logic levels of the first to fourth compensation codes RCD<1:4>.

[0117] Next, an operation of setting the second setting period based on a logic level combination of the first to fourth offset codes FCD<1:4> is described as follows.

[0118] When the first to fourth offset codes FCD<1:4> have a logic level combination of "0, 0, 0, 0", the second setup period may be set to 0.53 ns. The case where the second setup period is 0.53 ns may refer to the case where the period from the time when the first internal pulse IP having a logic high level is generated to the time when the first selection pulse SP having a logic high level is generated is 0.53 ns.

[0119] When the first to fourth offset codes FCD<1:4> have a logic level combination of "0, 0, 0, 1", the second setting period may be set to 1.05ns. The case where the second setting period is 1.05ns may refer to the case where the period from the time when the first internal pulse IP having a logic high level is generated to the time when the first selection pulse SP having a logic high level is generated is 1.05ns.

[0120] When the first to fourth offset codes FCD<1:4> have a logic level combination of "1, 1, 1, 1", the second setup period may be set to 8.43 ns. The case where the second setup period is 8.43 ns may refer to the case where the period from the time when the first internal pulse IP having a logic high level is generated to the time when the first selection pulse SP having a logic high level is generated is 8.43 ns.

[0121] As described above, the second setting period can be set differently based on the logic level combination of the first to fourth offset codes FCD<1:4>. In this case, according to an embodiment of the present disclosure, the first setting period and the second setting period can be set to different time periods, and the first setting period can be set to a shorter time period than the second setting period.

[0122] Fig.16 is a circuit diagram showing a structure according to an embodiment of a latch circuit 333 included in the phase lock signal generating circuit 330 .

[0123] The latch circuit 333 can be implemented by using a NOR gate 333 <1> and 333 <2> and inverter 333 <3> When the initial detection signal FDET having a logic high level is generated and the operation detection signal CDET having a logic high level is generated, the latch circuit 333 may generate a phase lock signal PLL_LK enabled to a logic high level. When one of the initial detection signal FDET and the operation detection signal CDET is generated to have a logic low level, the latch circuit 333 may generate a phase lock signal PLL_LK disabled to a logic low level.

[0124] Fig.17 and Fig.18 is a timing chart for describing the operation of the initial detection signal generating circuit 331 according to an embodiment of the present disclosure.

[0125] First, refer to Fig.17 The operation of the initial detection signal generating circuit 331 is described as follows. In this case, during the first setting period, the operation of the initial detection signal generating circuit 331 when the phase difference between the reference clock RCLK and the feedback clock FCLK is equal to or smaller than the first phase difference is described as follows.

[0126] At timing T11, the first signal synthesis circuit 411 of the first setting signal generation circuit 410 can generate a first internal pulse IP with a logic high level by synthesizing a first drive control signal UP with a logic low level and a second drive control signal DN with a logic high level. The first drive control signal UP can be generated to have a logic low level from timing T11 to timing T13. The second drive control signal DN can be generated to have a logic low level from timing T12 to timing T13. The first internal pulse IP can be generated to have a logic high level from timing T11 to timing T13.

[0127] The first delay circuit 412 of the first setting signal generating circuit 410 may generate the first to sixteenth delayed signals D1 to D16 by sequentially delaying the first internal pulse IP.

[0128] The first counter 421 to the sixth counter 426 of the first period setting circuit 420 may count the number of triggering times of the reference clock RCLK.

[0129] At timing T12, the first selection transfer circuit 413 of the first setting signal generating circuit 410 may generate a first selection pulse SP having a logic high level from one of the first to sixteenth delay signals D1 to D16 based on the logic level combination of the first to fourth compensation codes RCD<1:4>. Timing T11 to timing T12 may represent a first setting period.

[0130] The first signal synthesizing circuit 411 of the first setting signal generating circuit 410 may generate the first setting signal SET having a logic low level by synthesizing the first internal pulse IP having a logic high level and the first selection pulse SP having a logic high level.

[0131] When the level of the reference clock RCLK transitions twelfthly (ie, the setting number of times), the first to sixth counters 421 to 426 of the first period setting circuit 420 may generate a sixth carry signal C6 having a logic high level.

[0132] The first detection signal output circuit 427 of the first period setting circuit 420 may generate the initial detection signal FDET having a logic high level because the sixth carry signal S6 having a logic high level is generated during a period in which the first setting signal SET is enabled to a logic low level.

[0133] The operation of generating the operation detection signal CDET is the same as that already referred to Fig.17 The operation of generating the initial detection signal FDET described is the same, and thus, a detailed description thereof is omitted.

[0134] Next, refer to Fig.18 The operation of the initial detection signal generating circuit 331 is described as follows. In this case, during the first setting period, the operation of the initial detection signal generating circuit 331 when the phase difference between the reference clock RCLK and the feedback clock FCLK is equal to or smaller than the first phase difference is described as follows.

[0135] At timing T14, the first signal synthesis circuit 411 of the first setting signal generation circuit 410 can generate a first internal pulse IP with a logic high level by synthesizing a first drive control signal UP with a logic low level and a second drive control signal DN with a logic high level. The first drive control signal UP can be generated to have a logic low level from timing T14 to timing T16. The second drive control signal DN can be generated to have a logic low level from timing T15 to timing T16. The first internal pulse IP can be generated to have a logic high level from timing T14 to timing T16.

[0136] The first delay circuit 412 of the first setting signal generating circuit 410 may generate the first to sixteenth delayed signals D1 to D16 by sequentially delaying the first internal pulse IP.

[0137] The first counter 421 to the sixth counter 426 of the first period setting circuit 420 may count the number of triggering times of the reference clock RCLK.

[0138] At timing T17, the first selection transfer circuit 413 of the first setting signal generating circuit 410 may generate a first selection pulse SP having a logic high level from one of the first to sixteenth delay signals D1 to D16 based on the logic level combination of the first to fourth compensation codes RCD<1:4>. Timing T14 to timing T17 may represent a first setting period.

[0139] The first signal synthesizing circuit 411 of the first setting signal generating circuit 410 may generate the first setting signal SET having a logic high level by synthesizing the first internal pulse IP having a logic low level and the first selection pulse SP having a logic high level.

[0140] When the level of the reference clock RCLK transitions twelfthly (ie, the setting number of times), the first to sixth counters 421 to 426 of the first period setting circuit 420 may generate a sixth carry signal C6 having a logic high level.

[0141] Since the first setting signal SET is enabled to a logic high level, the first detection signal output circuit 427 of the first period setting circuit 420 may generate the initial detection signal FDET having a logic low level.

[0142] The operation of generating the operation detection signal CDET can be the same as that already referred to Fig.18 The operation of generating the initial detection signal FDET described is the same, and thus a detailed description thereof is omitted.

[0143] Fig.19 2 is a timing diagram for describing the operation of the phase lock signal generating circuit 330 according to an embodiment of the present disclosure. Fig.19 The operation of the phase lock signal generating circuit 330 is described, but the operation of the phase lock signal generating circuit 330 after the initial operation and outputting the phase lock signal is described as follows.

[0144] From timing T21 to timing T22, after the initial operation starts, the initial detection signal generating circuit 331 of the phase lock signal generating circuit 330 may set a first setting period for detecting the phase difference between the reference clock RCLK and the feedback clock FCLK based on the first drive control signal UP, the second drive control signal DN, and the first to fourth compensation codes RCD<1:4>. During the first setting period, when the phase difference between the reference clock RCLK and the feedback clock FCLK is equal to or less than the first phase difference, the initial detection signal generating circuit 331 of the phase lock signal generating circuit 330 may generate an initial detection signal FDET having a logic high level.

[0145] After the initial operation starts, the operation detection signal generation circuit 332 of the phase lock signal generation circuit 330 may generate the operation detection signal CDET having a logic low level.

[0146] When the initial detection signal FDET having a logic high level is generated and the operation detection signal CDET having a logic low level is generated, the latch circuit 333 of the phase lock signal generation circuit 330 may generate the phase lock signal PLL_LK disabled to a logic low level.

[0147] From timing T23 to timing T28, after the initial operation starts, the initial detection signal generating circuit 331 of the phase lock signal generating circuit 330 may set a first setting period for detecting the phase difference between the reference clock RCLK and the feedback clock FCLK based on the first drive control signal UP, the second drive control signal DN, and the first to fourth compensation codes RCD<1:4>. During the first setting period, when the phase difference between the reference clock RCLK and the feedback clock FCLK is equal to or less than the first phase difference, the initial detection signal generating circuit 331 of the phase lock signal generating circuit 330 may generate an initial detection signal FDET having a logic high level.

[0148] From timing T24 to timing T25, after outputting the phase lock signal PLL_LK, the operation detection signal generating circuit 332 of the phase lock signal generating circuit 330 may set a second setting period based on the first drive control signal UP, the second drive control signal DN, and the first to fourth offset codes FCD<1:4>. During the second setting period, when the difference between the phases of the reference clock RCLK and the feedback clock FCLK is less than a second phase difference greater than the first phase difference, the operation detection signal generating circuit 332 of the phase lock signal generating circuit 330 may generate an operation detection signal CDET having a logic high level.

[0149] When the initial detection signal FDET having a logic high level is generated and the operation detection signal CDET having a logic high level is generated, the latch circuit 333 of the phase lock signal generation circuit 330 may generate the phase lock signal PLL_LK enabled to a logic high level.

[0150] From timing T25 to timing T26, after outputting the phase lock signal PLL_LK, the operation detection signal generating circuit 332 of the phase lock signal generating circuit 330 may set a second setting period based on the first drive control signal UP, the second drive control signal DN, and the first to fourth offset codes FCD<1:4>. During the second setting period, when the difference between the phases of the reference clock RCLK and the feedback clock FCLK is equal to or greater than a second phase difference greater than the first phase difference, the operation detection signal generating circuit 332 of the phase lock signal generating circuit 330 may generate an operation detection signal CDET having a logic low level.

[0151] When the initial detection signal FDET having a logic high level is generated and the operation detection signal CDET having a logic low level is generated, the latch circuit 333 of the phase lock signal generation circuit 330 may generate the phase lock signal PLL_LK disabled to a logic low level.

[0152] From timing T26 to timing T27, after outputting the phase lock signal PLL_LK, the operation detection signal generating circuit 332 of the phase lock signal generating circuit 330 may set a second setting period based on the first drive control signal UP, the second drive control signal DN, and the first to fourth offset codes FCD<1:4>. During the second setting period, when the difference between the phases of the reference clock RCLK and the feedback clock FCLK is less than a second phase difference greater than the first phase difference, the operation detection signal generating circuit 332 of the phase lock signal generating circuit 330 may generate an operation detection signal CDET having a logic high level.

[0153] When the initial detection signal FDET having a logic high level is generated and the operation detection signal CDET having a logic high level is generated, the latch circuit 333 of the phase lock signal generation circuit 330 may generate the phase lock signal PLL_LK enabled to a logic high level.

[0154] From timing T27 to timing T28, after outputting the phase lock signal PLL_LK, the operation detection signal generating circuit 332 of the phase lock signal generating circuit 330 may set a second setting period based on the first drive control signal UP, the second drive control signal DN, and the first to fourth offset codes FCD<1:4>. During the second setting period, when the difference between the phases of the reference clock RCLK and the feedback clock FCLK is equal to or greater than a second phase difference greater than the first phase difference, the operation detection signal generating circuit 332 of the phase lock signal generating circuit 330 may generate an operation detection signal CDET having a logic low level.

[0155] When the initial detection signal FDET having a logic high level is generated and the operation detection signal CDET having a logic low level is generated, the latch circuit 333 of the phase lock signal generation circuit 330 may generate the phase lock signal PLL_LK disabled to a logic low level.

[0156] According to an embodiment of the present disclosure, the phase-lock signal generating circuit 330 can prevent the phase-lock signal PLL_LK from being unnecessarily generated due to noise after the phase-lock signal PLL_LK is output by setting the first setting period to short based on the first to fourth compensation codes RCD<1:4> after the initial operation starts, setting the second setting period to long based on the first to fourth offset codes FCD<1:4> after the phase-lock signal PLL_LK is output, and generating the phase-lock signal PLL_LK.

[0157] Fig. 20 is a flowchart for describing a method for adjusting a phase according to an embodiment of the present disclosure.

[0158] The method for adjusting the phase according to the embodiment of the present disclosure may include a phase detection step S1 , an initial operation step S2 , a phase lock signal generation preventing step S3 , a phase lock signal generating step S4 , and a PLL clock generating step S5 .

[0159] The phase detection step S1 may be set as a step of generating a first drive control signal UP and a second drive control signal DN by detecting a phase difference between a reference clock RCLK generated by a PLL clock PLL_CLK and a feedback clock FCLK. In the phase detection step S1, when the phase of the reference clock RCLK is earlier than the phase of the feedback clock FCLK, the phase detection circuit 320 may generate an enabled first drive control signal UP. In the phase detection step S1, when the phase of the feedback clock FCLK is earlier than the phase of the reference clock RCLK, the phase detection circuit 320 may generate an enabled second drive control signal DN.

[0160] The initial operation step S2 may include an initial operation entering step S21 , a first setting period setting step S22 , and an initial detection signal (FDET) generating step S23 .

[0161] The initial operation entry step S21 may be set as a step of entering the initial operation.

[0162] After the initial operation starts, the first setting period setting step S22 may be set as a step of setting the first setting period based on the first drive control signal UP, the second drive control signal DN, and the first to fourth compensation codes RCD<1:4>. In the first setting period setting step S22, after the initial operation starts, the initial detection signal generating circuit 331 may set a first setting period for detecting the phase difference between the reference clock RCLK and the feedback clock FCLK based on the first drive control signal UP, the second drive control signal DN, and the first to fourth compensation codes RCD<1:4>.

[0163] During the first setting period, the initial detection signal generating step S23 may be set to an operation of generating the initial detection signal FDET when the phase difference between the reference clock RCLK and the feedback clock FCLK is equal to or less than the first phase difference. In the initial detection signal generating step S23, during the first setting period, the initial detection signal generating circuit 331 may generate the initial detection signal FDET enabled to a logic high level when the phase difference between the reference clock RCLK and the feedback clock FCLK is equal to or less than the first phase difference, and may generate the initial detection signal FDET disabled to a logic low level when the phase difference between the reference clock RCLK and the feedback clock FCLK is greater than the first phase difference. After the initial detection signal generating step S23 is performed, the phase lock signal generating step S4 may be performed.

[0164] During the first setting period, the initial operation step S2 may be set to the following operation: after the initial operation starts, the first setting period is set based on the first drive control signal UP, the second drive control signal DN, and the first to fourth compensation codes RCD<1:4>; and the initial detection signal FDET is generated based on the phase difference between the reference clock RCLK and the feedback clock FCLK. In the initial operation step S2, after the initial operation starts, when the phase difference between the reference clock RCLK and the feedback clock FCLK during the first setting period is equal to or less than the first phase difference, the enabled initial detection signal FDET may be generated. In the initial operation step S2, after the initial operation starts, when the phase difference between the reference clock RCLK and the feedback clock FCLK during the first setting period is greater than the first phase difference, the disabled initial detection signal FDET may be generated.

[0165] The phase lock signal control step S3 may include a second setting period setting step S31 and an operation detection signal generating step S32.

[0166] After the phase lock signal PLL_LK is output, the second setting period setting step S31 may be set as a step of setting the second setting period based on the first drive control signal UP, the second drive control signal DN, and the first to fourth offset codes FCD<1:4>. In the second setting period setting step S31, after the phase lock signal PLL_LK is output, the operation detection signal generating circuit 332 may set the second setting period based on the first drive control signal UP, the second drive control signal DN, and the first to fourth offset codes FCD<1:4>.

[0167] During the second setting period, the operation detection signal generating step S32 may be set as a step of generating the operation detection signal CDET when the phase difference between the reference clock RCLK and the feedback clock FCLK is less than a second phase difference greater than the first phase difference. In the operation detection signal generating step S32, during the second setting period, the operation detection signal generating circuit 332 may generate the operation detection signal CDET enabled to a logic high level when the phase difference between the reference clock RCLK and the feedback clock FCLK is less than the second phase difference greater than the first phase difference, and may generate the operation detection signal CDET disabled to a logic low level when the phase difference between the reference clock RCLK and the feedback clock FCLK is equal to or greater than the second phase difference greater than the first phase difference. After the operation detection signal generating step S32 is performed, the phase lock signal generating step S4 may be performed.

[0168] The phase lock signal control step S3 may be set as follows: after the phase lock signal PLL_LK is output, a second setting period is set based on the first drive control signal UP, the second drive control signal DN, and the first to fourth offset codes FCD<1:4>; and during the second setting period, an operation detection signal CDET is generated based on the phase difference between the reference clock RCLK and the feedback clock FCLK. In the phase lock signal control step S3, after the phase lock signal PLL_LK is output, when the phase difference between the reference clock RCLK and the feedback clock FCLK during the second setting period is less than a second phase difference greater than the first phase difference, an operation detection signal CDET enabled to a logic high level may be generated. In the phase lock signal control step S3, after the phase lock signal PLL_LK is output, when the phase difference between the reference clock RCLK and the feedback clock FCLK during the second setting period is equal to or greater than the second phase difference greater than the first phase difference, an operation detection signal CDET disabled to a logic low level may be generated.

[0169] The phase-lock signal generating step S4 may be set as a step of generating the phase-lock signal PLL_LK based on the initial detection signal FDET and the operation detection signal CDET. In the phase-lock signal generating step S4, the latch circuit 333 may generate the phase-lock signal PLL_LK based on the initial detection signal FDET and the operation detection signal CDET. When both the initial detection signal FDET and the operation detection signal CDET are enabled to a logic high level, the latch circuit 333 may generate the phase-lock signal PLL_LK enabled to a logic high level. When one of the initial detection signal FDET and the operation detection signal CDET is disabled to a logic low level, the latch circuit 333 may stop generating the phase-lock signal PLL_LK.

[0170] The PLL clock generation step S5 may be set as a step of generating the PLL clock PLL_CLK. In the PLL clock generation step S5, the PLL circuit 300 may generate the PLL clock PLL_CLK so that the phase of the PLL clock PLL_CLK is generated within the target period. The PLL circuit 300 may adjust the phase of the PLL clock PLL_CLK so that the difference between the phases of the reference clock RCLK generated from the PLL clock PLL_CLK and the feedback clock FCLK is less than the first phase difference. When the PLL clock generation step S5 is terminated, the phase detection step S1 may be entered again.

[0171] According to the method of adjusting the phase of an embodiment of the present disclosure, the phase-locked signal PLL_LK can be prevented from being unnecessarily generated due to jitter variation and noise by setting the first setting period to be short based on the first to fourth compensation codes RCD<1:4>, setting the second setting period to be long based on the first to fourth offset codes FCD<1:4>, and generating the phase-locked signal PLL_LK after the initial operation starts. Fig.21 1 is a block diagram showing the configuration of an embodiment of an electronic system 1000 according to an embodiment of the present disclosure. Fig.21 As shown, the electronic system 1000 may include a host 1100 and a semiconductor system 1200 .

[0172] The host 1100 and the semiconductor system 1200 may transmit signals to each other by using an interface protocol. The interface protocol used between the host 1100 and the semiconductor system 1200 may include a multimedia card (MMC), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), and a universal serial bus (USB).

[0173] The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400 (K: 1). The controller 1300 may control the semiconductor device 1400 (K: 1) so that the semiconductor device 1400 (K: 1) performs a write operation and a read operation. Each semiconductor device 1400 (K: 1) may prevent a phase lock signal from being unnecessarily generated due to jitter and noise by setting a first setting period to be short based on a compensation code, setting a second setting period to be long based on an offset code, and generating a phase lock signal after an initial operation starts.

[0174] The controller 1300 may be implemented as Figure 1 Each semiconductor device 1400 (K:1) can be implemented as Figure 2 The electronic device 20 shown. According to an embodiment, each semiconductor device 1400 (K:1) may be implemented as one of a dynamic random access memory (DRAM), a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

Claims

1. An electronic device, comprising: A phase detection circuit that detects a phase difference between a reference clock and a feedback clock; as well as a phase lock signal generating circuit, which generates a phase lock signal based on a detection result of the phase difference between the reference clock and the feedback clock, Wherein, the phase-locked signal generating circuit: After the initial operation starts, the phase lock signal is generated when the phase difference between the reference clock and the feedback clock is equal to or smaller than a first phase difference, and After the phase lock signal is output, generation of the phase lock signal is stopped when the phase difference between the reference clock and the feedback clock is equal to or greater than a second phase difference, the second phase difference being greater than the first phase difference.

2. The electronic device according to claim 1, wherein: The phase lock signal generating circuit generates the phase lock signal based on the difference between the phases of the reference clock and the feedback clock during a first setting period and during a second setting period, and The first setting period and the second setting period are set to different periods. The first setting period is set to be shorter than the second setting period.

3. The electronic device according to claim 1, wherein: The phase detection circuit generates a first driving control signal and a second driving control signal by detecting the phase difference between the reference clock and the feedback clock.

4. The electronic device according to claim 3, in, When the phase of the reference clock is earlier than the phase of the feedback clock, the phase detection circuit generates the first driving control signal which is enabled, and Wherein, when the phase of the feedback clock is earlier than the phase of the reference clock, the phase detection circuit generates the second driving control signal which is enabled.

5. The electronic device according to claim 3, wherein: The phase detection circuit comprises: A reference clock phase control circuit which: generating the first driving control signal, the first driving control signal being enabled when the level of the reference clock transitions from the first logic level to the second logic level and being disabled when the reset signal is enabled, and generating a reference setting signal and a first pre-driver control signal, the reference setting signal and the first pre-driver control signal being enabled when the reference clock transitions from the first logic level to the second logic level; A feedback clock phase control circuit which: generating the second drive control signal, the second drive control signal being enabled when the feedback clock transitions from the first logic level to the second logic level and being disabled when the reset signal is enabled, and generating a feedback setting signal and a second pre-driver control signal, the feedback setting signal and the second pre-driver control signal being enabled when the feedback clock transitions from the first logic level to the second logic level; and A reset signal generating circuit generates the reset signal, wherein the reset signal is enabled when the reference setting signal, the first pre-driving control signal, the feedback setting signal and the second pre-driving control signal are all enabled.

6. The electronic device according to claim 5, wherein: The reference clock phase control circuit comprises: A first drive control signal generating circuit, which: generating the reference setting signal, the reference setting signal being enabled when the reference clock transitions from the first logic level to the second logic level, and generating the first drive control signal, the first drive control signal being enabled when the reference setting signal and the first pre-drive control signal are both enabled during a period in which the reset signal is disabled; and a first pre-drive control signal generating circuit, which generates the first pre-drive control signal, the first pre-drive control signal being enabled when the reference setting signal is disabled and being disabled when the reset signal is enabled.

7. The electronic device according to claim 5, wherein: The feedback clock phase control circuit comprises: A second drive control signal generating circuit, which: generating the feedback setting signal, the feedback setting signal being enabled when the feedback clock transitions from the first logic level to the second logic level, and generating the second drive control signal, the second drive control signal being enabled when the feedback setting signal and the second pre-drive control signal are both enabled during a period in which the reset signal is disabled; and a second pre-drive control signal generating circuit, which generates the second pre-drive control signal, the second pre-drive control signal being enabled when the feedback setting signal is disabled and being disabled when the reset signal is enabled.

8. The electronic device according to claim 1, wherein: The phase-locked signal generating circuit comprises: An initial detection signal generating circuit, which: After the initial operation starts, a first setting period is set based on the first driving control signal and the second driving control signal and the compensation code, and generating an initial detection signal based on the phase difference between the reference clock and the feedback clock during the first setting period; An operation detection signal generating circuit is provided, which: After the phase lock signal is output, a second setting period is set based on the first drive control signal and the second drive control signal and an offset code, and generating an operation detection signal based on the phase difference between the reference clock and the feedback clock during the second setting period; and A latch circuit generates the phase lock signal based on the initial detection signal and the operation detection signal.

9. The electronic device according to claim 8, in, The compensation code is a signal input from an external device to set the first setting period, the first setting period is used to detect the phase difference between the reference clock and the feedback clock, and The offset code is a signal input from the external device to set the second setting period, and the second setting period is used to detect the phase difference between the reference clock and the feedback clock.

10. The electronic device according to claim 8, wherein: The initial detection signal generating circuit comprises: First, a signal generating circuit is provided, which: generating a first internal pulse by synthesizing the first drive control signal and the second drive control signal, and generating a first selection pulse and a first setting signal based on the first internal pulse, the first selection pulse being generated by delaying the first internal pulse by the first setting period based on the compensation code; and A first period setting circuit generates the initial detection signal in response to the first setting signal when the reference clock is triggered a first setting number of times.

11. The electronic device according to claim 10, wherein: The first setting signal generating circuit comprises: a first signal synthesis circuit that generates the first internal pulse by synthesizing the first drive control signal and the second drive control signal, and generates the first setting signal by synthesizing the first internal pulse and the first selection pulse; a first delay circuit that generates first to fourth delay signals by delaying the first internal pulse, the first to fourth delay signals being sequentially enabled; and A first selection transfer circuit outputs one of the first delay signal to the fourth delay signal as the first selection pulse based on the compensation code.

12. The electronic device according to claim 10, wherein: The first time period setting circuit comprises: a first group of counters, comprising a plurality of counters, the first group of counters counting the reference clock through the plurality of counters; and generating a first carry signal, wherein the first carry signal is enabled when the reference clock is triggered by the first set number of times; and A first detection signal output circuit generates the initial detection signal when the first carry signal is generated, the initial detection signal being enabled when the first setting signal is disabled and being disabled when the first setting signal is enabled.

13. The electronic device according to claim 8, wherein: The operation detection signal generating circuit comprises: a second setting signal generating circuit that generates a second internal pulse by synthesizing the first drive control signal and the second drive control signal, and generates a second selection pulse and a second setting signal based on the second internal pulse, the second selection pulse being generated by delaying the second internal pulse by the second setting period based on the offset code; and A second period setting circuit generates the operation detection signal based on the second setting signal when the reference clock is triggered a second setting number of times.

14. The electronic device according to claim 13, wherein: The second setting signal generating circuit comprises: a second signal synthesis circuit that generates the second internal pulse by synthesizing the first drive control signal and the second drive control signal, and generates the second setting signal by synthesizing the second internal pulse and the second selection pulse; a second delay circuit that generates fifth to eighth delayed signals by delaying the second internal pulse, the fifth to eighth delayed signals being sequentially enabled; and A second selection transfer circuit outputs one of the fifth delayed signal to the eighth delayed signal as the second selection pulse based on the offset code.

15. The electronic device according to claim 13, wherein: The second time period setting circuit comprises: a second group of counters, comprising a plurality of counters, the second group of counters counting the reference clock by the plurality of counters; and generating a second carry signal, the second carry signal being enabled when the reference clock is triggered the second set number of times; and A second detection signal output circuit generates the operation detection signal when the second carry signal is generated, the operation detection signal being enabled when the second setting signal is disabled and being disabled when the second setting signal is enabled.

16. An electronic device comprising: an initial detection signal generating circuit that generates an initial detection signal when a phase difference between a reference clock and a feedback clock is equal to or smaller than a first phase difference after an initial operation starts; an operation detection signal generating circuit, which stops generating the operation detection signal when the phase difference between the reference clock and the feedback clock is equal to or greater than a second phase difference after outputting the phase lock signal, and the second phase difference is greater than the first phase difference; as well as A latch circuit generates the phase lock signal based on the initial detection signal and the operation detection signal.

17. The electronic device according to claim 16, wherein: The latch circuit is directly electrically connected to the initial detection signal generating circuit, receives the initial detection signal directly electrically connected to the operation detection signal generating circuit, and receives the operation detection signal.

18. The electronic device according to claim 16, wherein: The initial detection signal generating circuit: After the initial operation starts, a first setting period is set based on a first drive control signal and a second drive control signal and a compensation code, the first drive control signal and the second drive control signal being generated based on the phase difference between the reference clock and the feedback clock, and During the first setting period, the initial detection signal is generated based on the difference between the phases of the reference clock and the feedback clock.

19. The electronic device according to claim 16, wherein: The operation detection signal generating circuit: After outputting the phase lock signal, setting a second setting period greater than a first setting period based on the first drive control signal and the second drive control signal and the offset code, the first drive control signal and the second drive control signal being generated based on the phase difference between the reference clock and the feedback clock, and During the second setting period, the operation detection signal is generated based on the difference between the phases of the reference clock and the feedback clock.

20. The electronic device according to claim 19, wherein: The offset code is a signal input from an external device to set the second setting period for detecting the difference between the phases of the reference clock and the feedback clock.

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