Packaging substrate structure and preparation method thereof

Abstract

The invention provides a package substrate structure and a preparation method thereof, and the method comprises the steps: forming a blind groove structure on a first dielectric layer of a package substrate to expose a blocking structure of the package substrate, and enabling a passive surface of a silicon-based intermediate layer comprising a passive device to be disposed in the blind groove structure through an organic mucous membrane, a plurality of layers of interconnection structures and interconnection layers are arranged on the surface of the packaging substrate, and the circuit layers are all in effective electric connection; and solder mask layers are respectively arranged on the surfaces of the packaging substrates. According to the invention, the passive device is integrated into the silicon-based intermediate layer and is embedded into the packaging substrate, so that the surface mounting space of the packaging substrate is improved, the circuit design flexibility is improved, the step of mounting the device for multiple times is avoided, and the process flow and the cost are reduced; in addition, by means of the design that the passive device is embedded in the packaging substrate, the integrated interconnection density of packaging is improved, and the packaging size is reduced. And finally, in cooperation with a semitransparent dielectric layer, the position alignment precision of patterning is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a packaging substrate structure and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor process technology, the requirements of artificial intelligence, servers, and wearable devices for integrated circuits are shifting towards portability, miniaturization, and multi-functionality, which requires chips to have a smaller size while achieving high integration. However, due to the physical limitations of silicon materials, transistors will require higher R&D costs to achieve technology nodes below 5 nanometers, and "Moore's Law" is gradually coming to an end. Advanced packaging uses technologies such as through silicon vias (TSV), micro bumps (μBump), redistribution layers (RDL), and interposers to achieve multi-chip packaging interconnection, which is a feasible solution to continue "Moore's Law".

[0003] In order to ensure the power integrity and signal integrity of the chip, an array of passive devices such as capacitors and resistors are generally mounted on the surface of the package substrate. Usually, passive devices will occupy about 30% of the surface area of ​​the PIN (pin) surface of the CPU / GPU package substrate, covering the positions of about 300 to 500 PINs (about 1100 to 2000 PINs on a conventional size carrier). With the current electronic products becoming smaller and smaller and more integrated, this surface mounting capacitor method can no longer meet the needs, affecting the packaging interconnection of multiple chips.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0005] In view of the above shortcomings of the prior art, an object of the present invention is to provide a packaging substrate structure and a preparation method thereof, so as to solve the problems of insufficient surface mounting space and difficult design of high-integration packaging substrates in the prior art.

[0006] To achieve the above object, the present invention provides a method for preparing a packaging substrate structure, the method comprising:

[0007] Step 1: providing a packaging substrate, the packaging substrate comprising a core board layer, a circuit layer and a first dielectric layer, wherein two circuit layers are respectively arranged on two opposite surfaces of the core board layer, the two circuit layers penetrate the core board layer to achieve mutual connection, the first dielectric layer respectively covers the circuit layer and the exposed upper surface of the core board layer, and the circuit layer comprises a blocking structure;

[0008] Step 2: providing a silicon-based intermediate layer, wherein the silicon-based intermediate layer comprises a passive surface and an active surface which are arranged opposite to each other, a passive device is arranged on the passive surface of the silicon-based intermediate layer, and the silicon-based intermediate layer comprises an interconnection layer, and the interconnection layer is located on a side of the silicon-based intermediate layer close to the active surface;

[0009] Step 3: forming a blind groove structure on the first dielectric layer of the packaging substrate, wherein a blocking structure in the circuit layer is exposed below the blind groove structure, and a cross-sectional area of ​​the blind groove structure parallel to the core layer is larger than a cross-sectional area of ​​the blocking structure parallel to the core layer;

[0010] Step 4: Arranging an organic adhesive film on the passive surface of the silicon-based intermediate layer, and arranging the silicon-based intermediate layer into the blind groove structure through the organic adhesive film;

[0011] Step 5: a multi-layer interconnection structure is respectively arranged on the upper surface and the lower surface of the packaging substrate after the silicon-based intermediate layer is arranged, and the multi-layer interconnection structure forms an effective electrical connection with the interconnection layer of the silicon-based intermediate layer and the circuit layer of the packaging substrate;

[0012] Step 6: After the multi-layer interconnection structure is provided, solder resist layers are respectively provided on the upper surface and the lower surface of the packaging substrate, thereby obtaining the packaging substrate structure including the silicon-based intermediate layer.

[0013] Optionally, the passive device includes any combination of one or more of a silicon-based capacitor, a silicon-based resistor, and / or a silicon-based inductor.

[0014] Optionally, the method for preparing the silicon-based intermediate layer comprises:

[0015] Providing a first substrate, wherein the lower surface of the first substrate serves as a passive surface of the silicon-based intermediate layer, and a first oxide layer is disposed on the first substrate;

[0016] Setting a deep hole penetrating through the first oxide layer and extending into the first substrate;

[0017] A first electrode layer is disposed on the first oxide layer, the first electrode layer covers the first oxide layer and the surface exposed by the deep hole; a second dielectric layer is disposed on the first electrode layer, the second dielectric layer covers the surface of the first electrode layer; a second electrode layer is disposed on the second dielectric layer, the second electrode layer covers the surface of the second dielectric layer and fills the deep hole;

[0018] The second electrode layer is planarized, and a first through hole is set to penetrate the second electrode layer and the second dielectric layer; a second oxide layer is set on the second electrode layer, and the second oxide layer fills the first through hole; a second through hole is set on the second oxide layer, and the second through hole is set in the first through hole and penetrates the first through hole, and the second through hole and the second electrode layer and the second dielectric layer are isolated by the second oxide layer; a third through hole is set on the second oxide layer, and the third through hole is set at a position where the first through hole is not set, and the third through hole penetrates the second electrode layer; a first metal layer is set on the second oxide layer, and the first metal layer is connected to the first electrode layer through the second through hole, and the first metal layer is connected to the second electrode layer through the third through hole;

[0019] The first metal layer is patterned, and a third dielectric layer is filled in the patterned gaps of the first metal layer. The first metal layer and the third dielectric layer form a first interconnect layer, and the upper surface of the first interconnect layer serves as the active surface of the silicon-based intermediate layer.

[0020] Optionally, the method for preparing the silicon-based intermediate layer comprises:

[0021] Providing a second substrate, and disposing a third oxide layer on the second substrate;

[0022] Disposing a resistance metal layer on the third oxide layer;

[0023] A fourth dielectric layer is disposed on the resistive metal layer, and a fourth through hole is disposed on the fourth dielectric layer, wherein the fourth through hole is located above the resistive metal layer and penetrates the fourth dielectric layer;

[0024] Disposing a second metal layer on the fourth dielectric layer;

[0025] The second metal layer is patterned and a fifth dielectric layer is filled in the gaps of the patterned second metal layer. The second metal layer and the fifth dielectric layer form a second interconnection layer.

[0026] The present invention also provides a method for preparing a packaging substrate structure, the method comprising:

[0027] Step 1: providing a packaging substrate, the packaging substrate comprising a core board layer, a circuit layer and a first dielectric layer, the two circuit layers are arranged on two opposite surfaces of the core board layer and penetrate the core board layer for connection, the first dielectric layer covers the circuit layer and the exposed upper surface of the core board layer respectively, the packaging substrate comprises a first surface and a second surface arranged oppositely, the first surface is close to the upper surface of the core board layer;

[0028] Step 2: providing a silicon-based intermediate layer, wherein the silicon-based intermediate layer comprises a passive surface and an active surface which are arranged opposite to each other, a passive device layer is arranged on the passive surface of the silicon-based intermediate layer, and the silicon-based intermediate layer comprises an interconnection layer, and the interconnection layer is located on a surface of the silicon-based intermediate layer close to the active surface;

[0029] Step 3: a through-groove structure is provided on the packaging substrate, wherein the through-groove structure penetrates the packaging substrate, and a cross-sectional area of ​​the through-groove structure parallel to the core plate layer is larger than a cross-sectional area of ​​the silicon-based intermediate layer parallel to the core plate layer;

[0030] Step 4: thinning the first dielectric layer located on the second surface of the packaging substrate to expose the circuit layer;

[0031] Step 5: Laminating a barrier layer on the second surface of the packaging substrate after thinning;

[0032] Step 6: disposing the active surface of the silicon-based intermediate layer on the barrier layer in the through-groove structure of the packaging substrate;

[0033] Step 7: Laminating a sixth dielectric layer on the packaging substrate after the silicon-based intermediate layer is provided;

[0034] Step 8: removing the barrier layer to expose the interconnection layer of the silicon-based intermediate layer and the circuit layer of the packaging substrate;

[0035] Step 9: a multi-layer interconnection structure is respectively arranged on the first surface and the second surface of the packaging substrate after the barrier layer is removed, wherein the multi-layer interconnection structure forms an effective electrical connection with the interconnection layer of the silicon-based intermediate layer and the circuit layer of the packaging substrate;

[0036] Step 10: After the multi-layer interconnection structure is provided, solder resist layers are respectively provided on the first surface and the second surface of the packaging substrate, thereby obtaining the packaging substrate structure including the silicon-based intermediate layer.

[0037] Optionally, the passive device includes any combination of one or more of a silicon-based capacitor, a silicon-based resistor, and / or a silicon-based inductor.

[0038] Optionally, the method for preparing the silicon-based intermediate layer comprises:

[0039] Providing a first substrate, wherein the lower surface of the first substrate serves as a passive surface of the silicon-based intermediate layer, and a first oxide layer is disposed on the first substrate;

[0040] Setting a deep hole penetrating through the first oxide layer and extending into the first substrate;

[0041] A first electrode layer is disposed on the first oxide layer, the first electrode layer covers the first oxide layer and the surface exposed by the deep hole; a second dielectric layer is disposed on the first electrode layer, the second dielectric layer covers the surface of the first electrode layer; a second electrode layer is disposed on the second dielectric layer, the second electrode layer covers the surface of the second dielectric layer and fills the deep hole;

[0042] The second electrode layer is planarized, and a first through hole is set to penetrate the second electrode layer and the second dielectric layer; a second oxide layer is set on the second electrode layer, and the second oxide layer fills the first through hole; a second through hole is set on the second oxide layer, and the second through hole is set in the first through hole and penetrates the first through hole, and the second through hole and the second electrode layer and the second dielectric layer are isolated by the second oxide layer; a third through hole is set on the second oxide layer, and the third through hole is set at a position where the first through hole is not set, and the third through hole penetrates the second electrode layer; a first metal layer is set on the second oxide layer, and the first metal layer is connected to the first electrode layer through the second through hole, and the first metal layer is connected to the second electrode layer through the third through hole;

[0043] The first metal layer is patterned, and a third dielectric layer is filled in the patterned gaps of the first metal layer. The first metal layer and the third dielectric layer form a first interconnect layer, and the upper surface of the first interconnect layer serves as the active surface of the silicon-based intermediate layer.

[0044] Optionally, the method for preparing the silicon-based intermediate layer comprises:

[0045] Providing a second substrate, and disposing a third oxide layer on the second substrate;

[0046] Disposing a resistance metal layer on the third oxide layer;

[0047] A fourth dielectric layer is disposed on the resistive metal layer, and a fourth through hole is disposed on the fourth dielectric layer, wherein the fourth through hole is located above the resistive metal layer and penetrates the fourth dielectric layer;

[0048] Disposing a second metal layer on the fourth dielectric layer;

[0049] The second metal layer is patterned and a fifth dielectric layer is filled in the gaps of the patterned second metal layer. The second metal layer and the fifth dielectric layer form a second interconnection layer.

[0050] Optionally, the material of the first dielectric layer of the packaging substrate is a semi-transparent organic substance.

[0051] The present invention also provides a packaging substrate structure, and the packaging substrate structure is obtained by using any one of the above-mentioned preparation methods.

[0052] As described above, the packaging substrate structure and the preparation method thereof of the present invention have the following beneficial effects:

[0053] The present invention integrates passive devices into a silicon-based intermediate layer and buries the package substrate, thereby increasing the mounting space on the surface of the package substrate, improving the flexibility of circuit design, and avoiding the steps of mounting devices multiple times, thereby reducing the process flow and cost.

[0054] In addition, the design of embedding passive components into the package substrate can improve the integrated interconnection density of the package and reduce the package size;

[0055] Finally, a semi-transparent dielectric layer is used to improve the positioning accuracy of the patterning. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a schematic diagram of the structure presented by providing a packaging substrate in step 1 in the first embodiment of the present invention.

[0057] Figure 2 It is a schematic diagram showing the structure of the silicon-based capacitor integrated in the silicon-based intermediate layer in the present invention.

[0058] Figure 3 It is a schematic diagram showing the structure of the silicon-based resistor integrated in the silicon-based intermediate layer in the present invention.

[0059] Figure 4 It is a schematic structural diagram of the blind groove structure formed in step 3 in the first embodiment of the present invention.

[0060] Figure 5 It is a schematic diagram of the structure presented by setting a silicon-based intermediate layer in step 4 in the first embodiment of the present invention.

[0061] Figure 6 It is a schematic structural diagram of the first dielectric build-up layer provided in step 5 in the first embodiment of the present invention.

[0062] Figure 7 It is a schematic structural diagram of providing a first via hole in the first dielectric build-up layer in step 5 in the first embodiment of the present invention.

[0063] Figure 8It is a schematic diagram showing the structure of the first circuit build-up layer obtained in step 5 in the first embodiment of the present invention.

[0064] Fig. 9 It is a schematic structural diagram of the second dielectric build-up layer provided in step 5 in the first embodiment of the present invention.

[0065] Fig.10 It is a schematic structural diagram of providing a second via hole in the second dielectric build-up layer in step 5 in the first embodiment of the present invention.

[0066] Fig.11 It is a schematic diagram showing the structure of the second circuit build-up layer obtained in step 5 in the first embodiment of the present invention.

[0067] Fig.12 It is a schematic diagram of the structure presented by providing a solder resist layer in step 6 in the first embodiment of the present invention.

[0068] Fig.13 It is a schematic diagram of the structure presented by providing a packaging substrate in step 1 in the second embodiment of the present invention.

[0069] Fig.14 It is a schematic diagram of the structure presented by forming a through groove structure in step 3 of the second embodiment of the present invention.

[0070] Fig.15 It is a schematic diagram of the structure presented by thinning the first dielectric layer in step 4 in the second embodiment of the present invention.

[0071] Fig.16 It is a schematic diagram showing the structure of the barrier layer pressed in step 5 in the second embodiment of the present invention.

[0072] Fig.17 It is a schematic diagram of the structure presented by setting a silicon-based intermediate layer in step 6 in the second embodiment of the present invention.

[0073] Fig.18 It is a schematic diagram of the structure presented by setting the sixth dielectric layer in step 7 in the second embodiment of the present invention.

[0074] Fig.19 It is a schematic diagram of the structure presented by removing the barrier layer in step 8 in the second embodiment of the present invention.

[0075] Fig. 20 It is a schematic structural diagram of the first dielectric build-up layer provided in step 9 in the second embodiment of the present invention.

[0076] Fig.21 It is a schematic structural diagram of providing a first via hole in the first dielectric build-up layer and the sixth dielectric layer in step 9 in the second embodiment of the present invention.

[0077] Fig. 22 It is a schematic diagram showing the structure of the first circuit build-up layer obtained in step 9 in the second embodiment of the present invention.

[0078] Fig.23 It is a schematic structural diagram of the second dielectric build-up layer provided in step 9 in the second embodiment of the present invention.

[0079] Fig.24 It is a schematic structural diagram of providing a second via hole in the second dielectric build-up layer in step 9 of the second embodiment of the present invention.

[0080] Fig.25 It is a schematic diagram showing the structure of the second circuit build-up layer obtained in step 9 in the second embodiment of the present invention.

[0081] Fig.26 It is a schematic diagram of the structure presented by providing a solder resist layer in step 10 in the second embodiment of the present invention.

[0082] Component number description

[0083] 101, core layer; 102, circuit layer; 103, first dielectric layer; 104, blind slot structure; 105, barrier structure; 106, organic adhesive film; 107, first dielectric build-up layer; 108, first via hole; 109, first circuit build-up layer; 110, second dielectric build-up layer; 111, second via hole; 112, second circuit build-up layer; 113, solder mask layer

[0084] 201, second dielectric layer; 202, second electrode layer; 203, first metal layer; 204, second oxide layer; 205, first oxide layer; 206, third dielectric layer; 207, first electrode layer; 208, first substrate;

[0085] 304, through-groove structure; 305, barrier layer; 306, sixth dielectric layer;

[0086] 401, resistance metal layer; 402, second metal layer; 403, fifth dielectric layer; 404, third oxide layer; 405, fourth dielectric layer; 406, second substrate. DETAILED DESCRIPTION

[0087] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0088] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0089] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0090] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0091] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0092] Embodiment 1:

[0093] The present invention provides a method for preparing a packaging substrate structure, the preparation method comprising:

[0094] Step 1: providing a packaging substrate, the packaging substrate comprising a core board layer 101, a circuit layer 102 and a first dielectric layer 103, the two circuit layers 102 are respectively arranged on two opposite surfaces of the core board layer 101, the two circuit layers 102 penetrate the core board layer 101 to achieve mutual connection, the first dielectric layer 103 respectively covers the circuit layer 102 and the exposed upper surface of the core board layer 101, and the circuit layer 102 includes a blocking structure 105;

[0095] Step 2: providing a silicon-based intermediate layer, the silicon-based intermediate layer comprising a passive surface and an active surface arranged opposite to each other, a passive device being arranged on the passive surface of the silicon-based intermediate layer, and the silicon-based intermediate layer comprising an interconnection layer, and the interconnection layer being located on a side of the silicon-based intermediate layer close to the active surface;

[0096] Step 3: forming a blind groove structure 104 on the first dielectric layer 103 of the package substrate, wherein the blocking structure 105 in the circuit layer 102 is exposed below the blind groove structure 104, and the cross-sectional area of ​​the blind groove structure 104 parallel to the core layer 101 is larger than the cross-sectional area of ​​the blocking structure 105 parallel to the core layer 101;

[0097] Step 4: an organic adhesive film 106 is disposed on the passive surface of the silicon-based intermediate layer, and the silicon-based intermediate layer is disposed in the blind groove structure 104 through the organic adhesive film 106;

[0098] Step 5: a multi-layer interconnection structure is respectively arranged on the upper surface and the lower surface of the packaging substrate after the silicon-based intermediate layer is arranged, and the multi-layer interconnection structure forms an effective electrical connection with the interconnection layer of the silicon-based intermediate layer and the circuit layer 102 of the packaging substrate;

[0099] Step 6: Solder resist layers 113 are respectively provided on the upper surface and the lower surface of the packaging substrate after the multi-layer interconnection structure is provided, thereby obtaining a packaging substrate structure including a silicon-based intermediate layer.

[0100] The preparation method of the packaging substrate structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the packaging substrate structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0101] First, if Figure 1 As shown, step 1 is performed to provide a packaging substrate, the packaging substrate includes a core board layer 101, a circuit layer 102 and a first dielectric layer 103, the two circuit layers 102 are respectively arranged on two opposite surfaces of the core board layer 101, the two circuit layers 102 penetrate the core board layer 101 to achieve mutual connection, the first dielectric layer 103 respectively covers the circuit layer 102 and the exposed upper surface of the core board layer 101, and the circuit layer 102 includes a blocking structure 105.

[0102] Specifically, the circuit layer 102 is a conductive layer, and the blocking structure 105 is a portion of the conductive layer after the circuit layer 102 is patterned. The conductive layer may be a copper surface.

[0103] Then, step 2 is performed to provide a silicon-based intermediate layer, the silicon-based intermediate layer includes a passive surface and an active surface arranged opposite to each other, passive devices are arranged on the passive surface of the silicon-based intermediate layer, and the silicon-based intermediate layer includes an interconnection layer, which is located on the side of the silicon-based intermediate layer close to the active surface.

[0104] In one embodiment, the passive device includes any combination of one or more of a silicon-based capacitor, a silicon-based resistor, and / or a silicon-based inductor.

[0105] In one embodiment, when multiple passive devices are simultaneously arranged in a silicon-based intermediate layer, the multiple passive devices can be arranged in the same layer, or vertically stacked, or simultaneously laid flat in the same layer and vertically stacked.

[0106] In one embodiment, Figure 2 The method for preparing the silicon-based intermediate layer shown includes:

[0107] Providing a first substrate 208, wherein the lower surface of the first substrate 208 serves as a passive surface of the silicon-based intermediate layer, and a first oxide layer 205 is disposed on the first substrate 208;

[0108] A deep hole is provided to penetrate the first oxide layer 205 and extend into the first substrate 208;

[0109] A first electrode layer 207 is disposed on the first oxide layer 205, and the first electrode layer 207 covers the first oxide layer 205 and the surface exposed by the deep holes; a second dielectric layer 201 is disposed on the first electrode layer 207, and the second dielectric layer 201 covers the surface of the first electrode layer 207; a second electrode layer 202 is disposed on the second dielectric layer 201, and the second electrode layer 202 covers the surface of the second dielectric layer 201 and fills the deep holes;

[0110] The second electrode layer 202 is planarized, and a first through hole is set to penetrate the second electrode layer 202 and the second dielectric layer 201; a second oxide layer 204 is set on the second electrode layer 202, and the second oxide layer 204 fills the first through hole; a second through hole is set on the second oxide layer 204, the second through hole is set in the first through hole and penetrates the first through hole, and the second through hole and the second electrode layer 202 and the second dielectric layer 201 are isolated by the second oxide layer 204; a third through hole is set on the second oxide layer 204, the third through hole is set at a position where the first through hole is not set, and the third through hole penetrates the second electrode layer 202; a first metal layer 203 is set on the second oxide layer 204, the first metal layer 203 is connected to the first electrode layer 207 through the second through hole, and the first metal layer 203 is connected to the second electrode layer 202 through the third through hole;

[0111] The first metal layer 203 is patterned, and the third dielectric layer 206 is filled in the patterned gaps of the first metal layer 203. The first metal layer 203 and the third dielectric layer 206 form a first interconnect layer, and the upper surface of the first interconnect layer serves as the active surface of the silicon-based intermediate layer.

[0112] Specifically, the above method is a method for preparing a structure in which a silicon-based capacitor is integrated in a silicon-based intermediate layer.

[0113] In one embodiment, the first oxide layer 205 is prepared by thermal oxidation, and the material of the first oxide layer 205 is silicon dioxide.

[0114] In one embodiment, the deep holes are prepared by deep silicon etching.

[0115] In one embodiment, the first electrode layer 207 is formed by atomic layer deposition, the second dielectric layer 201 is formed by sputtering, and the second electrode layer 202 is formed by electroplating.

[0116] In one embodiment, chemical mechanical polishing is used to planarize the second electrode layer 202 .

[0117] In one embodiment, the second oxide layer 204 is formed by sputtering.

[0118] In one embodiment, the first metal layer 203 is formed by sputtering or electroplating.

[0119] In one embodiment, the third dielectric layer 206 is formed by sputtering or electroplating, and the material of the third dielectric layer 206 is silicon dioxide.

[0120] In one embodiment, after the third dielectric layer 206 is provided, the first interconnect layer is planarized by chemical mechanical polishing to expose the first metal layer 203 .

[0121] In one embodiment, Figure 3 The method for preparing the silicon-based intermediate layer shown includes:

[0122] Providing a second substrate 406, and disposing a third oxide layer 404 on the second substrate 406;

[0123] Disposing a resistance metal layer 401 on the third oxide layer 404;

[0124] A fourth dielectric layer 405 is disposed on the resistance metal layer 401 , and a fourth through hole is disposed on the fourth dielectric layer 405 , wherein the fourth through hole is located above the resistance metal layer 401 and penetrates the fourth dielectric layer 405 ;

[0125] Disposing a second metal layer 402 on the fourth dielectric layer 405;

[0126] The second metal layer 402 is patterned and the fifth dielectric layer 403 is filled in the patterned gap of the second metal layer 402 . The second metal layer 402 and the fifth dielectric layer 403 form a second interconnect layer.

[0127] Specifically, the above method is a method for preparing a structure in which a silicon-based resistor is integrated in a silicon-based intermediate layer.

[0128] In one embodiment, the third oxide layer 404 is prepared by thermal oxidation, and the material of the third oxide layer 404 is silicon dioxide.

[0129] In one embodiment, the resistive metal layer 401 is formed by atomic layer deposition, sputtering or doping.

[0130] In one embodiment, the material of the resistance metal layer 401 is titanium nitride, nickel-chromium alloy or heavily doped semiconductor.

[0131] In one embodiment, the fourth dielectric layer 405 is deposited by plasma enhanced chemical vapor deposition.

[0132] In one embodiment, the fourth through hole is provided by ion beam etching.

[0133] In one embodiment, the second metal layer 402 is formed by atomic layer deposition, sputtering or electroplating.

[0134] In one embodiment, after the fifth dielectric layer 403 is provided, the second interconnect layer is planarized by chemical mechanical polishing to expose the second metal layer 402 .

[0135] The present invention avoids the step of repeatedly mounting passive components on the surface of a packaging substrate by integrating the preparation method of passive components in a silicon-based intermediate layer. Since the silicon-based intermediate layer can be prepared in batches in advance, the preparation process and preparation cost of the packaging substrate can be reduced, and the preparation efficiency can be effectively improved.

[0136] Then, if Figure 4 As shown, step 3 is performed to form a blind groove structure 104 on the first dielectric layer 103 of the packaging substrate, and the blocking structure 105 in the circuit layer 102 is exposed below the blind groove structure 104. The cross-sectional area of ​​the blind groove structure 104 parallel to the core board layer 101 is larger than the cross-sectional area of ​​the blocking structure 105 parallel to the core board layer 101.

[0137] Specifically, the present invention ensures that the depth of the blind groove structure 104 formed is consistent and all are located on the blocking structure 105 by setting the cross-sectional area of ​​the blind groove structure 104 parallel to the core plate layer 101 to be larger than the cross-sectional area of ​​the blocking structure 105 parallel to the core plate layer 101 .

[0138] In one embodiment, the difference between the length of the blind groove structure 104 and the length of the blocking structure 105 is approximately 200 microns, and the difference between the width of the blind groove structure 104 and the width of the blocking structure 105 is approximately 200 microns, where the length and width refer to two mutually perpendicular directions parallel to the core board layer 101.

[0139] In one embodiment, the blind groove structure 104 is provided by mechanical drilling, laser drilling, or stamping.

[0140] Then, if Figure 5As shown, step 4 is performed to set an organic adhesive film 106 on the passive surface of the silicon-based intermediate layer, and set the silicon-based intermediate layer into the blind groove structure 104 through the organic adhesive film 106.

[0141] Specifically, the organic adhesive film 106 utilizes the thermal expansion coefficient of the organic material to be relatively matched with the first dielectric layer 103 of the packaging substrate, and utilizes the characteristic that the organic material will solidify after heating, so that the silicon-based intermediate layer is more firmly fixed on the packaging substrate.

[0142] In one embodiment, the silicon-based intermediate layer is placed in the blind groove structure 104 by mounting. After the silicon-based intermediate layer is placed, the obtained package substrate structure is heated in an oven at 80 to 150° C. for 10 to 30 minutes to solidify the organic adhesive film 106 .

[0143] The present invention integrates passive devices into a silicon-based intermediate layer and buries the passive devices into a packaging substrate, so that the packaging substrate can not only mount passive devices on the surface but also mount passive devices inside, thereby achieving sufficient passive device settings in a smaller space to ensure chip power and signal integrity, or having higher design flexibility for passive devices in the same packaging substrate surface area, while improving the integrated interconnection density of the packaging substrate, and achieving a smaller package.

[0144] Then, if Figure 6-Figure 11 As shown, step 5 is performed to respectively set a multilayer interconnection structure on the upper surface and the lower surface of the packaging substrate after setting the silicon-based intermediate layer, and the multilayer interconnection structure forms an effective electrical connection with the interconnection layer of the silicon-based intermediate layer and the circuit layer 102 of the packaging substrate.

[0145] In one embodiment, a method for preparing a multi-layer interconnect structure includes:

[0146] like Figure 6 As shown, the first dielectric build-up layer 107 is pressed onto the upper surface and the lower surface of the packaging substrate after the silicon-based intermediate layer is provided;

[0147] A CCD (Charge Coupled Device) camera is used to identify the actual position of the interconnection layer of the silicon-based intermediate layer, and position data correction is performed for the position offset generated when the silicon-based intermediate layer is set;

[0148] like Figure 7 As shown, a first via hole 108 is set on the first dielectric build-up layer 107 according to the corrected position data;

[0149] like Figure 8 As shown, metal is deposited in the first via hole 108 to obtain a first circuit build-up layer 109;

[0150] like Figure 9-11As shown, the above steps are repeated to obtain a second dielectric build-up layer 110 and a second circuit build-up layer 112 disposed in the second via 111. The first dielectric build-up layer 107, the second dielectric build-up layer 110, the first circuit build-up layer 109, and the second circuit build-up layer 112 together constitute a multi-layer interconnection structure.

[0151] In one embodiment, multiple dielectric build-up layers and circuit build-up layers may be provided to obtain a multi-layer interconnect structure with different interconnect densities.

[0152] In one embodiment, the material of the first dielectric build-up layer 107 and / or the second dielectric build-up layer 110 is ABF (Ajinomoto Build-up Film).

[0153] In one embodiment, the first circuit build-up layer 109 and / or the second circuit build-up layer 112 are obtained by depositing metal by sputtering, chemical plating, and electroplating.

[0154] Finally, if Fig.12 As shown, step 6 is performed to respectively set solder resist layers 113 on the upper surface and the lower surface of the packaging substrate after the multi-layer interconnection structure is set, thereby obtaining a packaging substrate structure including a silicon-based intermediate layer.

[0155] The present invention adopts a method of placing a silicon-based intermediate layer by using a blind groove. Since the blind groove is located closer to the surface of the packaging substrate, the interconnection layer of the silicon-based intermediate layer can be connected to the surface of the packaging substrate structure through a multi-layer interconnection structure with only a small number of alignment steps.

[0156] Embodiment 2:

[0157] The present invention provides a method for preparing a packaging substrate structure, the preparation method comprising:

[0158] Step 1: providing a packaging substrate, the packaging substrate comprising a core board layer 101, a circuit layer 102 and a first dielectric layer 103, two circuit layers 102 are arranged on two opposite surfaces of the core board layer 101 and penetrate the core board layer 101 for connection, the first dielectric layer 103 covers the circuit layer 102 and the exposed upper surface of the core board layer 101 respectively, the packaging substrate comprises a first surface and a second surface arranged oppositely, the first surface is close to the upper surface of the core board layer 101;

[0159] Step 2: providing a silicon-based intermediate layer, the silicon-based intermediate layer comprising a passive surface and an active surface arranged opposite to each other, a passive device layer being arranged on the passive surface of the silicon-based intermediate layer, and the silicon-based intermediate layer comprising an interconnection layer, the interconnection layer being located on a surface of the silicon-based intermediate layer close to the active surface;

[0160] Step 3: a through-groove structure 304 is provided on the packaging substrate, the through-groove structure 304 penetrates the packaging substrate, and the cross-sectional area of ​​the through-groove structure 304 parallel to the core board layer 101 is larger than the cross-sectional area of ​​the silicon-based intermediate layer parallel to the core board layer 101;

[0161] Step 4: thinning the first dielectric layer 103 located on the second surface of the package substrate to expose the circuit layer 102;

[0162] Step 5: Laminating a barrier layer 305 on the thinned second surface of the packaging substrate;

[0163] Step 6: Disposing the active surface of the silicon-based intermediate layer on the barrier layer 305 in the through-groove structure 304 of the packaging substrate;

[0164] Step 7: Laminating the sixth dielectric layer 306 on the packaging substrate after the silicon-based intermediate layer is provided;

[0165] Step 8: removing the barrier layer 305 to expose the interconnection layer of the silicon-based intermediate layer and the circuit layer 102 of the packaging substrate;

[0166] Step 9: a multi-layer interconnection structure is respectively arranged on the first surface and the second surface of the packaging substrate after removing the barrier layer 305, and the multi-layer interconnection structure forms an effective electrical connection with the interconnection layer of the silicon-based intermediate layer and the circuit layer 102 of the packaging substrate;

[0167] Step 10: Solder resist layers 113 are respectively provided on the first surface and the second surface of the package substrate after the multi-layer interconnection structure is provided, thereby obtaining a package substrate structure including a silicon-based intermediate layer.

[0168] The preparation method of the packaging substrate structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the packaging substrate structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0169] First, if Fig.13 As shown, step 1 is performed to provide a packaging substrate, the packaging substrate including a core board layer 101, a circuit layer 102 and a first dielectric layer 103, the two circuit layers 102 are arranged on two opposite surfaces of the core board layer 101 and penetrate the core board layer 101 for connection, the first dielectric layer 103 respectively covers the circuit layer 102 and the exposed upper surface of the core board layer 101, the packaging substrate includes a first surface and a second surface arranged oppositely, and the first surface is close to the upper surface of the core board layer 101.

[0170] In one embodiment, the material of the first dielectric layer 103 of the package substrate is a semi-transparent organic material.

[0171] In one embodiment, a main component of the first dielectric layer 103 is epoxy resin.

[0172] The present invention sets the first dielectric layer 103 of the packaging substrate as a translucent organic material so that the position of the interconnection layer pins of the silicon-based intermediate layer can be more accurately determined by camera photography, thereby avoiding the position deviation of the pins and holes due to process reasons when drilling using standard materials, and realizing high-precision through-hole preparation.

[0173] Then, step 2 is performed to provide a silicon-based intermediate layer, the silicon-based intermediate layer includes a passive surface and an active surface arranged opposite to each other, a passive device layer is arranged on the passive surface of the silicon-based intermediate layer, and the silicon-based intermediate layer includes an interconnection layer, which is located on the surface of the silicon-based intermediate layer close to the active surface.

[0174] In one embodiment, the passive device includes any combination of one or more of a silicon-based capacitor, a silicon-based resistor, and / or a silicon-based inductor.

[0175] In one embodiment, when multiple passive devices are simultaneously arranged in a silicon-based intermediate layer, the multiple passive devices can be arranged in the same layer, or vertically stacked, or simultaneously laid flat in the same layer and vertically stacked.

[0176] In one embodiment, Figure 2 The method for preparing the silicon-based intermediate layer shown includes:

[0177] Providing a first substrate 208, wherein the lower surface of the first substrate 208 serves as a passive surface of the silicon-based intermediate layer, and a first oxide layer 205 is disposed on the first substrate 208;

[0178] A deep hole is provided to penetrate the first oxide layer 205 and extend into the first substrate 208;

[0179] A first electrode layer 207 is disposed on the first oxide layer 205, and the first electrode layer 207 covers the first oxide layer 205 and the surface exposed by the deep holes; a second dielectric layer 201 is disposed on the first electrode layer 207, and the second dielectric layer 201 covers the surface of the first electrode layer 207; a second electrode layer 202 is disposed on the second dielectric layer 201, and the second electrode layer 202 covers the surface of the second dielectric layer 201 and fills the deep holes;

[0180] The second electrode layer 202 is planarized, and a first through hole is set to penetrate the second electrode layer 202 and the second dielectric layer 201; a second oxide layer 204 is set on the second electrode layer 202, and the second oxide layer 204 fills the first through hole; a second through hole is set on the second oxide layer 204, the second through hole is set in the first through hole and penetrates the first through hole, and the second through hole and the second electrode layer 202 and the second dielectric layer 201 are isolated by the second oxide layer 204; a third through hole is set on the second oxide layer 204, the third through hole is set at a position where the first through hole is not set, and the third through hole penetrates the second electrode layer 202; a first metal layer 203 is set on the second oxide layer 204, the first metal layer 203 is connected to the first electrode layer 207 through the second through hole, and the first metal layer 203 is connected to the second electrode layer 202 through the third through hole;

[0181] The first metal layer 203 is patterned, and the third dielectric layer 206 is filled in the patterned gaps of the first metal layer 203. The first metal layer 203 and the third dielectric layer 206 form a first interconnect layer, and the upper surface of the first interconnect layer serves as the active surface of the silicon-based intermediate layer.

[0182] Specifically, the above method is a method for preparing a structure in which a silicon-based capacitor is integrated in a silicon-based intermediate layer.

[0183] Specifically, the above method is a method for preparing a structure in which a silicon-based capacitor is integrated in a silicon-based intermediate layer.

[0184] In one embodiment, the first oxide layer 205 is prepared by thermal oxidation, and the material of the first oxide layer 205 is silicon dioxide.

[0185] In one embodiment, the deep holes are prepared by deep silicon etching.

[0186] In one embodiment, the first electrode layer 207 is formed by atomic layer deposition, the second dielectric layer 201 is formed by sputtering, and the second electrode layer 202 is formed by electroplating.

[0187] In one embodiment, chemical mechanical polishing is used to planarize the second electrode layer 202 .

[0188] In one embodiment, the second oxide layer 204 is formed by sputtering.

[0189] In one embodiment, the first metal layer 203 is formed by sputtering or electroplating.

[0190] In one embodiment, the third dielectric layer 206 is formed by sputtering or electroplating, and the material of the third dielectric layer 206 is silicon dioxide.

[0191] In one embodiment, after the third dielectric layer 206 is provided, the first interconnect layer is planarized by chemical mechanical polishing to expose the first metal layer 203 .

[0192] In one embodiment, Figure 3 The method for preparing the silicon-based intermediate layer shown includes:

[0193] Providing a second substrate 406, and disposing a third oxide layer 404 on the second substrate 406;

[0194] Disposing a resistance metal layer 401 on the third oxide layer 404;

[0195] A fourth dielectric layer 405 is disposed on the resistance metal layer 401 , and a fourth through hole is disposed on the fourth dielectric layer 405 , wherein the fourth through hole is located above the resistance metal layer 401 and penetrates the fourth dielectric layer 405 ;

[0196] Disposing a second metal layer 402 on the fourth dielectric layer 405;

[0197] The second metal layer 402 is patterned and the fifth dielectric layer 403 is filled in the patterned gap of the second metal layer 402 . The second metal layer 402 and the fifth dielectric layer 403 form a second interconnect layer.

[0198] Specifically, the above method is a method for preparing a structure in which a silicon-based resistor is integrated in a silicon-based intermediate layer.

[0199] In one embodiment, the third oxide layer 404 is prepared by thermal oxidation, and the material of the third oxide layer 404 is silicon dioxide.

[0200] In one embodiment, the resistive metal layer 401 is formed by atomic layer deposition, sputtering or doping.

[0201] In one embodiment, the material of the resistance metal layer 401 is titanium nitride, nickel-chromium alloy or heavily doped semiconductor.

[0202] In one embodiment, the fourth dielectric layer 405 is deposited by plasma enhanced chemical vapor deposition.

[0203] In one embodiment, the fourth through hole is provided by ion beam etching.

[0204] In one embodiment, the second metal layer 402 is formed by atomic layer deposition, sputtering or electroplating.

[0205] In one embodiment, after the fifth dielectric layer 403 is provided, the second interconnect layer is planarized by chemical mechanical polishing to expose the second metal layer 402 .

[0206] The present invention avoids the step of repeatedly mounting passive components on the surface of a packaging substrate by integrating the preparation method of passive components in a silicon-based intermediate layer. Since the silicon-based intermediate layer can be prepared in batches in advance, the preparation process and preparation cost of the packaging substrate can be reduced, and the preparation efficiency can be effectively improved.

[0207] Then, if Fig.14 As shown, step 3 is performed to set a through groove structure 304 on the packaging substrate. The through groove structure 304 penetrates the packaging substrate, and the cross-sectional area of ​​the through groove structure 304 parallel to the core board layer 101 is larger than the cross-sectional area of ​​the silicon-based intermediate layer parallel to the core board layer 101.

[0208] In one embodiment, the through-slot structure 304 is provided by mechanical drilling, laser drilling, or stamping.

[0209] Then, if Fig.15 As shown, step 4 is performed to thin the first dielectric layer 103 located on the second surface of the package substrate to expose the circuit layer 102 .

[0210] In one embodiment, the thinning step may also be performed after removing the barrier layer 305. Specifically, it may be determined according to the connection strength between the barrier layer 305 and the first dielectric layer 103 and the connection strength between the barrier layer 305 and the circuit layer 102. If the connection strength between the barrier layer 305 and the circuit layer 102 is large, the thinning step is performed after providing the through-groove structure 304. If the connection strength between the barrier layer 305 and the first dielectric layer 103 is large, the thinning step is performed after removing the barrier layer 305.

[0211] Then, if Fig.16 As shown, step 5 is performed to laminate a barrier layer 305 on the second surface of the package substrate after thinning.

[0212] Then, if Fig.17 As shown, step 6 is performed to dispose the active surface of the silicon-based intermediate layer on the barrier layer 305 in the through-groove structure 304 of the package substrate.

[0213] In one embodiment, an organic adhesive film 106 is disposed on the active surface of the silicon-based intermediate layer, so that the silicon-based intermediate layer and the organic adhesive film 106 are adhered to each other.

[0214] The present invention integrates passive devices into a silicon-based intermediate layer and buries the passive devices into a packaging substrate, so that the packaging substrate can not only mount passive devices on the surface but also mount passive devices inside, thereby achieving sufficient passive device settings in a smaller space to ensure chip power and signal integrity, or having higher design flexibility for passive devices in the same packaging substrate surface area, while improving the integrated interconnection density of the packaging substrate, and achieving a smaller package.

[0215] Then, if Fig.18 As shown, step 7 is performed to laminate the sixth dielectric layer 306 on the packaging substrate after the silicon-based intermediate layer is provided.

[0216] Then, if Fig.19 As shown, step 8 is performed to remove the barrier layer 305 to expose the interconnect layer of the silicon-based intermediate layer and the circuit layer 102 of the packaging substrate.

[0217] Then, if Figure 20-Figure 25 As shown, step 9 is performed to respectively set a multilayer interconnection structure on the first surface and the second surface of the packaging substrate after removing the barrier layer 305, and the multilayer interconnection structure forms an effective electrical connection with the interconnection layer of the silicon-based intermediate layer and the circuit layer 102 of the packaging substrate.

[0218] In one embodiment, a method for preparing a multi-layer interconnect structure includes:

[0219] like Fig. 20 As shown, the first dielectric build-up layer 107 is pressed onto the second surface of the packaging substrate after the silicon-based intermediate layer is provided;

[0220] A CCD (Charge Coupled Device) camera is used to identify the actual position of the interconnection layer of the silicon-based intermediate layer, and position data correction is performed for the position offset generated when the silicon-based intermediate layer is set;

[0221] like Fig.21 As shown, the first via hole 108 is set on the first dielectric build-up layer 107 and the sixth dielectric layer 306 according to the corrected position data;

[0222] like Fig. 22 As shown, metal is deposited in the first via hole 108 to obtain a first circuit build-up layer 109;

[0223] like Figure 23-Figure 25 As shown, the above steps are repeated to obtain a second dielectric build-up layer 110 and a second circuit build-up layer 112 disposed in the second via 111. The first dielectric build-up layer 107, the second dielectric build-up layer 110, the first circuit build-up layer 109, and the second circuit build-up layer 112 together constitute a multi-layer interconnection structure.

[0224] In one embodiment, multiple dielectric build-up layers and circuit build-up layers may be provided to obtain a multi-layer interconnect structure with different interconnect densities.

[0225] In one embodiment, the material of the first dielectric build-up layer 107 and / or the second dielectric build-up layer 110 is ABF (Ajinomoto Build-up Film).

[0226] In one embodiment, the thickness of the first dielectric build-up layer 107 in this embodiment is approximately twice the thickness of the first dielectric build-up layer 107 in the first embodiment to compensate for the height difference between the package substrate structure generated by the through-groove structure 304 and the blind-groove structure 104 .

[0227] In one embodiment, the first circuit build-up layer 109 and / or the second circuit build-up layer 112 are obtained by depositing metal by sputtering, chemical plating, and electroplating.

[0228] Finally, if Fig.26 As shown, step 10 is performed to respectively set solder resist layers 113 on the first surface and the second surface of the package substrate after the multi-layer interconnection structure is set, thereby obtaining a package substrate structure including a silicon-based intermediate layer.

[0229] The present invention provides a method for placing a silicon-based intermediate layer by setting a through-groove structure 304 and a barrier layer 305. Compared with the blind hole preparation method in Example 1, the manufacturing process is simpler. However, since the position of the through-groove structure 304 is far away from the surface of the packaging substrate, multiple alignments are required to achieve high-precision conductive interconnection. Therefore, it is necessary to cooperate with the aforementioned translucent first dielectric layer 103 as the dielectric layer of the packaging substrate to more accurately determine the position of the interconnection layer pins of the silicon-based intermediate layer through camera photography, thereby achieving high-precision blind hole preparation.

[0230] Embodiment three:

[0231] The present invention also provides a packaging substrate structure, and the packaging substrate structure is obtained by using any one of the preparation methods in the first embodiment or the second embodiment.

[0232] In summary, the package substrate structure and preparation method of the present invention can improve the mounting space on the surface of the package substrate by integrating the passive device into the silicon-based intermediate layer and burying it in the package substrate, thereby improving the flexibility of circuit design, while avoiding the steps of mounting the device multiple times, reducing the process flow and cost; in addition, by using the design of burying the passive device in the package substrate, the integrated interconnection density of the package is improved and the package size is reduced; finally, with the help of the semi-transparent dielectric layer, the alignment accuracy of the patterning is improved. .

[0233] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0234] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging substrate structure, characterized in that: The preparation method comprises: Step 1: providing a packaging substrate, the packaging substrate comprising a core board layer, a circuit layer and a first dielectric layer, wherein two circuit layers are respectively arranged on two opposite surfaces of the core board layer, the two circuit layers penetrate the core board layer to achieve mutual connection, the first dielectric layer respectively covers the circuit layer and the exposed upper surface of the core board layer, and the circuit layer comprises a blocking structure; Step 2: providing a silicon-based intermediate layer, wherein the silicon-based intermediate layer comprises a passive surface and an active surface which are arranged opposite to each other, a passive device is arranged on the passive surface of the silicon-based intermediate layer, and the silicon-based intermediate layer comprises an interconnection layer, and the interconnection layer is located on a side of the silicon-based intermediate layer close to the active surface; Step 3: forming a blind groove structure on the first dielectric layer of the packaging substrate, wherein a blocking structure in the circuit layer is exposed below the blind groove structure, and a cross-sectional area of ​​the blind groove structure parallel to the core layer is larger than a cross-sectional area of ​​the blocking structure parallel to the core layer; Step 4: Arranging an organic adhesive film on the passive surface of the silicon-based intermediate layer, and arranging the silicon-based intermediate layer into the blind groove structure through the organic adhesive film; Step 5: a multi-layer interconnection structure is respectively arranged on the upper surface and the lower surface of the packaging substrate after the silicon-based intermediate layer is arranged, and the multi-layer interconnection structure forms an effective electrical connection with the interconnection layer of the silicon-based intermediate layer and the circuit layer of the packaging substrate; Step 6: After the multi-layer interconnection structure is provided, solder resist layers are respectively provided on the upper surface and the lower surface of the packaging substrate, thereby obtaining the packaging substrate structure including the silicon-based intermediate layer.

2. The method for preparing a packaging substrate structure according to claim 1, characterized in that: The passive device includes one or any combination of silicon-based capacitors, silicon-based resistors and / or silicon-based inductors.

3. The method for preparing a packaging substrate structure according to claim 1, characterized in that: The method for preparing the silicon-based intermediate layer comprises: Providing a first substrate, wherein the lower surface of the first substrate serves as a passive surface of the silicon-based intermediate layer, and a first oxide layer is disposed on the first substrate; Setting a deep hole penetrating through the first oxide layer and extending into the first substrate; A first electrode layer is disposed on the first oxide layer, the first electrode layer covers the first oxide layer and the surface exposed by the deep hole; a second dielectric layer is disposed on the first electrode layer, the second dielectric layer covers the surface of the first electrode layer; a second electrode layer is disposed on the second dielectric layer, the second electrode layer covers the surface of the second dielectric layer and fills the deep hole; The second electrode layer is planarized, and a first through hole is set to penetrate the second electrode layer and the second dielectric layer; a second oxide layer is set on the second electrode layer, and the second oxide layer fills the first through hole; a second through hole is set on the second oxide layer, and the second through hole is set in the first through hole and penetrates the first through hole, and the second through hole and the second electrode layer and the second dielectric layer are isolated by the second oxide layer; a third through hole is set on the second oxide layer, and the third through hole is set at a position where the first through hole is not set, and the third through hole penetrates the second electrode layer; a first metal layer is set on the second oxide layer, and the first metal layer is connected to the first electrode layer through the second through hole, and the first metal layer is connected to the second electrode layer through the third through hole; The first metal layer is patterned, and a third dielectric layer is filled in the patterned gaps of the first metal layer. The first metal layer and the third dielectric layer form a first interconnect layer, and the upper surface of the first interconnect layer serves as the active surface of the silicon-based intermediate layer.

4. The method for preparing a packaging substrate structure according to claim 1, characterized in that: The method for preparing the silicon-based intermediate layer comprises: Providing a second substrate, and disposing a third oxide layer on the second substrate; Disposing a resistance metal layer on the third oxide layer; A fourth dielectric layer is disposed on the resistive metal layer, and a fourth through hole is disposed on the fourth dielectric layer, wherein the fourth through hole is located above the resistive metal layer and penetrates the fourth dielectric layer; Disposing a second metal layer on the fourth dielectric layer; The second metal layer is patterned and a fifth dielectric layer is filled in the gaps of the patterned second metal layer. The second metal layer and the fifth dielectric layer form a second interconnection layer.

5. A method for preparing a packaging substrate structure, characterized in that: The preparation method comprises: Step 1: providing a packaging substrate, the packaging substrate comprising a core board layer, a circuit layer and a first dielectric layer, wherein the two circuit layers are arranged on two oppositely arranged surfaces of the core board layer and penetrate the core board layer for connection, the first dielectric layer respectively covers the circuit layer and the exposed upper surface of the core board layer, the packaging substrate comprises a first surface and a second surface arranged oppositely, the first surface is close to the upper surface of the core board layer; Step 2: providing a silicon-based intermediate layer, wherein the silicon-based intermediate layer comprises a passive surface and an active surface which are arranged opposite to each other, a passive device layer is arranged on the passive surface of the silicon-based intermediate layer, and the silicon-based intermediate layer comprises an interconnection layer, and the interconnection layer is located on a surface of the silicon-based intermediate layer close to the active surface; Step 3: a through-groove structure is provided on the packaging substrate, wherein the through-groove structure penetrates the packaging substrate, and a cross-sectional area of ​​the through-groove structure parallel to the core plate layer is larger than a cross-sectional area of ​​the silicon-based intermediate layer parallel to the core plate layer; Step 4: thinning the first dielectric layer located on the second surface of the packaging substrate to expose the circuit layer; Step 5: Laminating a barrier layer on the second surface of the packaging substrate after thinning; Step 6: disposing the active surface of the silicon-based intermediate layer on the barrier layer in the through-groove structure of the packaging substrate; Step 7: Laminating a sixth dielectric layer on the packaging substrate after the silicon-based intermediate layer is provided; Step 8: removing the barrier layer to expose the interconnection layer of the silicon-based intermediate layer and the circuit layer of the packaging substrate; Step 9: a multi-layer interconnection structure is respectively arranged on the first surface and the second surface of the packaging substrate after the barrier layer is removed, wherein the multi-layer interconnection structure forms an effective electrical connection with the interconnection layer of the silicon-based intermediate layer and the circuit layer of the packaging substrate; Step 10: After the multi-layer interconnection structure is provided, solder resist layers are respectively provided on the first surface and the second surface of the packaging substrate, thereby obtaining the packaging substrate structure including the silicon-based intermediate layer.

6. The method for preparing a packaging substrate structure according to claim 5, characterized in that: The passive device includes one or any combination of silicon-based capacitors, silicon-based resistors and / or silicon-based inductors.

7. The method for preparing a packaging substrate structure according to claim 5, characterized in that: The method for preparing the silicon-based intermediate layer comprises: Providing a first substrate, wherein the lower surface of the first substrate serves as a passive surface of the silicon-based intermediate layer, and a first oxide layer is disposed on the first substrate; Setting a deep hole penetrating through the first oxide layer and extending into the first substrate; A first electrode layer is disposed on the first oxide layer, the first electrode layer covers the first oxide layer and the surface exposed by the deep hole; a second dielectric layer is disposed on the first electrode layer, the second dielectric layer covers the surface of the first electrode layer; a second electrode layer is disposed on the second dielectric layer, the second electrode layer covers the surface of the second dielectric layer and fills the deep hole; The second electrode layer is planarized, and a first through hole is set to penetrate the second electrode layer and the second dielectric layer; a second oxide layer is set on the second electrode layer, and the second oxide layer fills the first through hole; a second through hole is set on the second oxide layer, the second through hole is set in the first through hole and penetrates the first through hole, and the second through hole and the second electrode layer and the second dielectric layer are isolated by the second oxide layer; a third through hole is set on the second oxide layer, the third through hole is set at a position where the first through hole is not set, and the third through hole penetrates the second electrode layer; a first metal layer is set on the second oxide layer, the first metal layer is connected to the first electrode layer through the second through hole, and the first metal layer is connected to the second electrode layer through the third through hole; The first metal layer is patterned, and a third dielectric layer is filled in the patterned gaps of the first metal layer. The first metal layer and the third dielectric layer form a first interconnect layer, and the upper surface of the first interconnect layer serves as the active surface of the silicon-based intermediate layer.

8. The method for preparing a packaging substrate structure according to claim 5, characterized in that: The method for preparing the silicon-based intermediate layer comprises: Providing a second substrate, and disposing a third oxide layer on the second substrate; Disposing a resistance metal layer on the third oxide layer; A fourth dielectric layer is disposed on the resistive metal layer, and a fourth through hole is disposed on the fourth dielectric layer, wherein the fourth through hole is located above the resistive metal layer and penetrates the fourth dielectric layer; Disposing a second metal layer on the fourth dielectric layer; The second metal layer is patterned and a fifth dielectric layer is filled in the gaps of the patterned second metal layer. The second metal layer and the fifth dielectric layer form a second interconnection layer.

9. The method for preparing a packaging substrate structure according to claim 5, characterized in that: The material of the first dielectric layer of the packaging substrate is a semi-transparent organic substance.

10. A packaging substrate structure, characterized in that: The packaging substrate structure is obtained by the preparation method described in any one of claims 1-9.

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