Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a wafer which comprises an isolation region and a device region; forming a device structure on the device region, wherein the device structure comprises a first layer structure and a second layer structure on the first layer structure; an isolation structure located on the wafer is formed, the isolation structure is located on the isolation area and located on the area outside the device structure in the device area, and the device structure is located in the isolation structure; acquiring whether the second-layer structure and the first-layer structure have electrical failure or not; if the second-layer structure and the first-layer structure are in electrical failure, obtaining offset conditions of the second-layer structure and the first-layer structure in a first direction; and according to the offset condition of the second layer structure and the first layer structure in the first direction, carrying out laser annealing treatment on the wafer to enable the second layer structure and the first layer structure to recover electrical connection. According to the method, the stress condition of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In IC design and manufacturing, some special structural layouts are designed based on customer needs, and pattern loading effects often exist, thus affecting the performance of semiconductor devices.

[0003] Therefore, there is a need to improve this situation. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the stress influence of a wafer.

[0005] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a wafer, the wafer comprising an isolation region and a device region, the isolation region and the device region being distributed along a first direction parallel to the surface of the wafer; forming a device structure located on the device region, the device structure comprising a first layer structure and a second layer structure located on the first layer structure; forming an isolation structure located on the wafer, the isolation structure being located on the isolation region and on an area outside the device structure in the device region, the device structure being located within the isolation structure; obtaining whether the second layer structure and the first layer structure have electrical failures; if the second layer structure and the first layer structure have electrical failures, obtaining the offset of the second layer structure and the first layer structure in the first direction; performing laser annealing on the wafer according to the offset of the second layer structure and the first layer structure in the first direction, so that the second layer structure and the first layer structure are restored to electrical connection.

[0006] Optionally, the edge of the wafer has a positioning groove; the laser beam used for the laser annealing process has a projection spot on the surface of the wafer, the projection spot extends along the edge of the wafer to the center of the wafer, and the projection spot has a center line along the radius of the wafer; the positioning groove and the center of the wafer have a first connecting line.

[0007] Optionally, the offset conditions of the second layer structure and the first layer structure in the first direction include: an offset degree and an offset direction, wherein the offset degree includes a severe offset condition or a mild offset condition, and the offset direction includes an offset in a direction away from the isolation region or an offset in a direction toward the isolation region; the absolute value range of the offset in the severe offset condition is: 30 nanometers to 48 nanometers; the absolute value range of the offset in the mild offset condition is: 12 nanometers to 30 nanometers.

[0008] Optionally, laser annealing is performed on the wafer according to the offset of the second layer structure and the first layer structure in the first direction, including: adjusting the angle of the laser in the laser annealing process according to the offset degree and offset direction of the second layer structure and the first layer structure in the first direction, and performing laser annealing on the wafer.

[0009] Optionally, when the second layer structure and the first layer structure are seriously offset, a first laser annealing process is performed on the wafer.

[0010] Optionally, the first laser annealing treatment includes: performing a first treatment and a second treatment on the wafer; the first treatment includes: taking a first position as an initial point, rotating the wafer to perform the first treatment on the wafer, and a first angle is formed between the center line of the light spot at the first position and the first line; the second treatment includes: taking a second position as an initial point, rotating the wafer to perform a second treatment on the wafer, and a second angle is formed between the center line of the light spot at the second position and the first line.

[0011] Optionally, the absolute value of the difference between the first angle and the second angle is 180 degrees.

[0012] Optionally, when the offset directions of the second layer structure and the first layer structure are offset in a direction away from the isolation region, the first angle ranges from 10 degrees to 45 degrees, and the second angle ranges from 190 degrees to 225 degrees.

[0013] Optionally, when the offset directions of the second layer structure and the first layer structure are offset in a direction toward the isolation region, the first angle ranges from 100 degrees to 135 degrees, and the second angle ranges from 280 degrees to 335 degrees.

[0014] Optionally, when the second layer structure and the first layer structure are slightly offset, a second laser annealing process is performed on the wafer.

[0015] Optionally, the second laser annealing treatment includes: performing a third treatment and a fourth treatment on the wafer; the third treatment includes: taking the third position as the initial point, rotating the wafer to perform the third treatment on the wafer, and a third angle is formed between the center line of the light spot at the third position and the first line; the fourth treatment includes: taking the fourth position as the initial point, rotating the wafer to perform the fourth treatment on the wafer, and a fourth angle is formed between the center line of the light spot at the fourth position and the first line.

[0016] Optionally, the absolute value of the difference between the third angle and the fourth angle is 180 degrees.

[0017] Optionally, when the offset directions of the second layer structure and the first layer structure are offset in a direction toward the isolation region, the third angle ranges from 90 degrees to 100 degrees, and the fourth angle ranges from 270 degrees to 280 degrees.

[0018] Optionally, when the offset directions of the second layer structure and the first layer structure are offset in a direction away from the isolation region, the third angle ranges from 0 degrees to 10 degrees, and the fourth angle ranges from 180 degrees to 190 degrees.

[0019] Optionally, the first layer structure includes: a gate structure located on the wafer and source-drain doped regions located in the wafer on both sides of the gate structure, and the source-drain doped regions are located on both sides of the gate structure along a first direction; the second layer structure includes: a conductive plug located on the source-drain doped regions, and the conductive plug is electrically connected to the source-drain doped regions.

[0020] Optionally, obtaining whether the second layer structure and the first layer structure have electrical failure includes: if the conductive plug and the gate structure are offset in a first direction so that the conductive plug and the gate structure are bridged, then the second layer structure and the first layer structure are electrically failed.

[0021] Optionally, the first layer structure includes: a first metal layer located on the wafer, and an extension direction of the first metal layer is perpendicular to the first direction; the second layer structure includes: a connecting plug located on the first metal layer.

[0022] Optionally, obtaining whether the second layer structure and the first layer structure have electrical failure includes: if the connecting plug and the first metal layer are offset in a first direction so that the connecting plug and the first metal layer are not in contact, then the second layer structure and the first layer structure have electrical failure.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] The technical solution of the present invention, after the second layer structure and the first layer structure fail electrically, obtain the offset of the second layer structure and the first layer structure in the first direction, and then perform laser annealing on the wafer according to the offset of the second layer structure and the first layer structure in the first direction. The method performs targeted laser annealing on the wafer according to the offset of the second layer structure and the first layer structure in the first direction, and can neutralize the stress in the stress area on the wafer, reduce the stress from different directions, and correspondingly improve the electrical failure state in different directions, so that the second layer structure and the first layer structure are restored from the electrical failure state to the electrical connection state. The method is simple to operate, has little impact on the process, and has little impact on the relevant parameters of the semiconductor process.

[0025] Furthermore, according to the degree and direction of the offset of the second layer structure and the first layer structure in the first direction, the angle of the laser in the laser annealing process is adjusted, and the wafer is subjected to laser annealing process, which can flexibly adjust the offset in different directions and improve the negative impact of stress.

[0026] Furthermore, the offset of the second layer structure and the first layer structure in the first direction includes: an offset degree and an offset direction, wherein the offset degree includes a severe offset or a slight offset, and the offset direction includes an offset in a direction away from the isolation region or an offset in a direction toward the isolation region. According to the offset degree and the offset direction, the wafer is subjected to laser annealing treatment in a targeted manner to neutralize stress in the stress region on the wafer, thereby restoring the second layer structure and the first layer structure from an electrically failed state to an electrically connected state.

[0027] Furthermore, the absolute value of the difference between the first angle and the second angle is 180 degrees, and the absolute value of the difference between the third angle and the fourth angle is 180 degrees. Thus, the semiconductor structure is subjected to laser annealing on both the front and back sides, thereby avoiding uneven force on the front and back sides of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 7 is a schematic diagram of a process for forming a semiconductor structure in one embodiment;

[0029] Figure 8 is a schematic flow chart of a process for forming a semiconductor structure in an embodiment of the present invention;

[0030] Fig. 9 and Fig.10 is a schematic diagram of a process for forming a semiconductor structure in one embodiment of the present invention;

[0031] Fig.11 and Fig.12 is a schematic diagram of a process for forming a semiconductor structure in another embodiment of the present invention;

[0032] Fig.13 and Fig.14 is a schematic diagram of a process for forming a semiconductor structure in another embodiment of the present invention;

[0033] Fig.15 and Fig.16 is a schematic diagram of a process for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, there is a pattern loading effect that affects the performance of semiconductor devices, which will now be analyzed and explained in conjunction with specific embodiments.

[0035] Figures 1 to 7is a schematic diagram of a process of forming a semiconductor structure in one embodiment.

[0036] Please refer to Figures 1 to 3 , Figure 1 is a schematic diagram of a layout of a certain area on the wafer 100. Figure 2 for Figure 1 An enlarged schematic diagram of the device structure 103 on the middle device region, Figure 3 for Figure 2 The cross-sectional structure schematic diagram along the section line AA1 direction, the semiconductor structure includes: a wafer 100, the wafer 100 includes an isolation region 101 and a device region 102, the isolation region 101 and the device region 102 are distributed along a first direction X parallel to the surface of the wafer 100, the device region 102 includes an active region; a device structure 103 located on the active region; an isolation structure 107 located on the wafer 100, the isolation structure 107 is located on the isolation region 101, and is located in an area outside the device structure 103 in the device region 102, and the device structure 103 is located in the isolation structure 107.

[0037] The device structure 103 includes a first layer structure and a second layer structure located on the first layer structure.

[0038] Please continue to refer to Figure 2 and Figure 3 In this embodiment, the first layer structure includes: a gate structure 104 located on the wafer 100 and source-drain doped regions 105 located in the wafer 100 on both sides of the gate structure 104, and the source-drain doped regions 105 are located on both sides of the gate structure 104 along the first direction X; the second layer structure includes: a conductive plug 106 located on the source-drain doped regions 105, and the conductive plug 106 is electrically connected to the source-drain doped regions 105.

[0039] In this embodiment, the device region 102 includes a substrate (not shown) and a fin structure (not shown) located on the substrate, and the active region is the fin structure.

[0040] Please refer to Figure 4 , Figure 4Schematic diagram of stress distribution of wafer 100 after multiple processes. In the semiconductor structure, since there is a large isolation region 101 in the first direction X, and there is no device structure filled in the isolation region 101, the isolation structure 107 filled in the isolation region 101 will generate a large amount of stress, making the stress in some areas of the wafer 100 more concentrated. The edge of the wafer 100 has a positioning groove Notch, and the positioning groove Notch and the center of the wafer 100 have a first connection line. After the wafer 100 has undergone multiple processes, whether it is <110> Crystal direction or <100> In terms of crystal orientation, the wafer 100 presents a stress direction F with an angle of about 45° with the first connecting line, that is, the stress of the wafer 100 is more concentrated in a region 108 with an angle of about 45° with the first connecting line.

[0041] The isolation structure 107 filled on the isolation region 101 generates a large amount of stress, which is reflected in the second semiconductor structure in this embodiment as follows: the stress causes the active region of the device region 102 to be displaced and deformed, thereby causing the position of the conductive plug 106 to shift in the first direction X, and finally causing the conductive plug 106 to bridge with the gate structure 104 ( Figure 2 (shown in area B).

[0042] Please refer to Figure 5 After the wafer 100 has gone through multiple processes, a laser annealing process is usually used to anneal the wafer to eliminate stress defects. Laser annealing is a CO2 laser annealing method with a wavelength of 9.2 to 10.8 μm. Usually, a laser with a width of 80 μm is scanned at a high temperature of 75° Brewster angle θ, gradually covering the surface of the wafer 100. Figure 5 L1 is a normal line perpendicular to the surface of the wafer 100, and the angle between the light spot Laser and L1 is a Brewster angle θ of 75°. The laser annealing process includes two methods: single scan and dual scan. Single scan means scanning the wafer only once, and dual scan means scanning the wafer twice at different angles.

[0043] Please refer to Figure 6 and Figure 7 , Figure 6 and Figure 7 The schematic diagram of the double scanning process is that the commonly used double scanning method uses an angle of 45° / 225°. The specific working principle is: the laser spot direction does not move, the wafer 100 rotates clockwise, the first scan is performed at an angle of 45° to the first line, and then the second scan is performed at an angle of 225° to the first line. The positioning groove Notch and the center of the wafer 100 have a first connecting line N1, Figure 6 The angle between the middle spot laser and the first connecting line N1 is α1, α1 is 45°, Figure 7 The included angle between the middle light spot laser and the first connecting line N2 is α2, and α2 is 225°.

[0044] go through Figure 6 and Figure 7 After the double scanning of the laser annealing, the stress area generated in the wafer 100 after the laser annealing overlaps with the stress area of ​​the wafer 100 after multiple processes, which will further aggravate the stress level of the stress area on the wafer 100. After the stress superposition effect, it will further aggravate the bridge between the conductive plug 106 and the gate structure 104 mentioned above.

[0045] In order to improve the stress phenomenon of the wafer 100, on the one hand, a large number of dummy active areas are designed in the isolation area 101, and dummy device structures are formed on the dummy active areas. However, due to the limitations of design rules, the changes in the isolation area 101 are limited. On the other hand, the layout can be redesigned, that is, no large area of ​​isolation area is left, but this method is costly and has limited effect on improving stress.

[0046] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, after the second layer structure and the first layer structure fail electrically, the offset of the second layer structure and the first layer structure in the first direction is obtained, and then the wafer is laser annealed according to the offset of the second layer structure and the first layer structure in the first direction. The method performs targeted laser annealing on the wafer according to the offset of the second layer structure and the first layer structure in the first direction, and can neutralize the stress in the stress area on the wafer, reduce the stress from different directions, and correspondingly improve the electrical failure state in different directions, so that the second layer structure and the first layer structure are restored from the electrical failure state to the electrical connection state. The method is simple to operate, has little impact on the process, and has little impact on the relevant parameters of the semiconductor process.

[0047] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figure 8 is a schematic flow chart of a process for forming a semiconductor structure in an embodiment of the present invention; Fig. 9 and Fig.10 is a schematic diagram of a process for forming a semiconductor structure in one embodiment of the present invention.

[0049] Please refer to Figure 8 , the formation process of the semiconductor structure includes:

[0050] Step S10: providing a wafer, wherein the wafer comprises an isolation region and a device region, wherein the isolation region and the device region are distributed along a first direction parallel to a surface of the wafer;

[0051] Step S20: forming a device structure located on the device region, wherein the device structure includes a first layer structure and a second layer structure located on the first layer structure;

[0052] Step S30: forming an isolation structure on the wafer, wherein the isolation structure is located on the isolation region and on an area outside the device structure in the device region, wherein the device structure is located within the isolation structure;

[0053] Step S40: obtaining whether electrical failure occurs in the second layer structure and the first layer structure;

[0054] Step S50: if the second layer structure and the first layer structure are electrically failed, obtaining the offset of the second layer structure and the first layer structure in the first direction;

[0055] Step S60: performing laser annealing on the wafer according to the offset of the second layer structure and the first layer structure in the first direction, so that the second layer structure and the first layer structure are restored to be electrically connected.

[0056] The method performs targeted laser annealing on the wafer 100 according to the offset of the second layer structure and the first layer structure in the first direction X, and can neutralize the stress in the stress area on the wafer 100, reduce the stress from different directions, and correspondingly improve the electrical failure state in different directions, so that the second layer structure and the first layer structure are restored from the electrical failure state to the electrical connection state. The method is simple to operate, has little impact on the process, and has little impact on the relevant parameters of the semiconductor process.

[0057] Next, each step is analyzed and explained.

[0058] Please combine Figures 1 to 3 Continue to refer Figure 8 , perform step S10: provide a wafer 100, the wafer 100 includes an isolation region 101 and a device region 102, the isolation region 101 and the device region 102 are distributed along a first direction X parallel to the surface of the wafer 100; step S20: form a device structure 103 located on the device region 102, the device structure 103 includes a first layer structure and a second layer structure located on the first layer structure; step S30: form an isolation structure 107 located on the wafer 100, the isolation structure 103 is located on the isolation region 101, and on an area outside the device structure 103 in the device region 102, and the device structure 103 is located within the isolation structure 107.

[0059] Please continue to refer to Figure 2 and Figure 3In this embodiment, the first layer structure includes: a gate structure 104 located on the wafer 100 and source-drain doped regions 105 located in the wafer 100 on both sides of the gate structure 104, and the source-drain doped regions 105 are located on both sides of the gate structure 104 along the first direction X; the second layer structure includes: a conductive plug 106 located on the source-drain doped regions 105, and the conductive plug 106 is electrically connected to the source-drain doped regions 105.

[0060] In this embodiment, the device region 102 includes an active region, the device structure 103 is located on the active region, the device region 102 includes a substrate (not shown) and a fin structure (not shown) located on the substrate, and the active region is the fin structure.

[0061] In this embodiment, the material of the wafer 100 is silicon.

[0062] In other embodiments, the material of the wafer includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0063] In another embodiment, the first layer structure includes: a first metal layer located on the wafer, and an extension direction of the first metal layer is perpendicular to the first direction; the second layer structure includes: a connecting plug located on the first metal layer.

[0064] Please continue to refer to Figure 8 , executing step S40: obtaining whether electrical failure occurs in the second layer structure and the first layer structure.

[0065] In this embodiment, whether the second layer structure and the first layer structure are electrically failed includes: if the conductive plug 106 and the gate structure 104 are offset in the first direction X so that the conductive plug 106 and the gate structure 104 are bridged, then the second layer structure and the first layer structure are electrically failed.

[0066] In another embodiment, the first layer structure includes: a first metal layer located on the wafer, the extension direction of the first metal layer is perpendicular to the first direction; the second layer structure includes: a connection plug located on the first metal layer. Whether the second layer structure and the first layer structure are electrically failed includes: if the connection plug and the first metal layer are offset in the first direction so that the connection plug and the first metal layer are not in contact, then the second layer structure and the first layer structure are electrically failed.

[0067] Obtaining whether the second-layer structure and the first-layer structure have electrical failure includes: performing an electrical test on the semiconductor structure; if the electrical test result of the semiconductor structure fails, obtaining the offset of the second-layer structure and the first-layer structure; if the second-layer structure and the first-layer structure are offset in a first direction, the second-layer structure and the first-layer structure have electrical failure.

[0068] If the electrical test result of the semiconductor structure fails, and the second layer structure and the first layer structure are not offset in the first direction, it means that the failure of the electrical test result of the semiconductor structure is not caused by the second layer structure and the first layer structure, and other means need to be found to solve the problem of the failure of the electrical test result.

[0069] Please continue to refer to Figure 8 , executing step S50: if the second layer structure and the first layer structure are electrically failed, obtaining the offset of the second layer structure and the first layer structure in the first direction X.

[0070] The offset conditions of the second layer structure and the first layer structure in the first direction X include: an offset degree and an offset direction, wherein the offset degree includes a severe offset or a slight offset, and the offset direction includes an offset in a direction away from the isolation region 101 or an offset in a direction toward the isolation region 101.

[0071] The method performs laser annealing on the wafer 100 in a targeted manner according to the degree and direction of the offset to neutralize the stress in the stress area on the wafer, thereby restoring the second layer structure and the first layer structure from an electrically failed state to an electrically connected state.

[0072] In this embodiment, the absolute value range of the offset in the severe offset situation is 30 nanometers to 48 nanometers; the absolute value range of the offset in the mild offset situation is 12 nanometers to 30 nanometers.

[0073] Please continue to refer to Figure 8 , executing step S60: performing laser annealing treatment on the wafer 100 according to the offset of the second layer structure and the first layer structure in the first direction, so that the second layer structure and the first layer structure are restored to be electrically connected.

[0074] The offset condition includes an offset degree and an offset direction. According to the offset degree and offset direction of the second layer structure and the first layer structure in the first direction, the wafer 100 is subjected to laser annealing, including: adjusting the angle of the laser in the laser annealing, and performing laser annealing on the wafer 100. Thus, the offset conditions in different directions can be flexibly adjusted to improve the negative effects caused by stress.

[0075] In this embodiment, the second layer structure and the first layer structure recover from the electrical failure state to the electrical connection state, that is, the conductive plug 106 and the gate structure 104 are not bridged, and the distance between the conductive plug 106 and the gate structure 104 is within a safe range.

[0076] In other embodiments, in this embodiment, the connection plug is in contact with the first metal layer to achieve an electrical connection function.

[0077] The edge of the wafer 100 has a positioning groove Notch; the laser beam used in the laser annealing process has a projection spot on the surface of the wafer, the projection spot extends along the edge of the wafer 100 to the center of the wafer, and the projection spot has a center line Laser along the radius of the wafer; the positioning groove Notch and the center of the wafer 100 have a first connecting line.

[0078] Please refer to Fig. 9 and Fig.10 , Fig. 9 and Fig.10 is a schematic diagram of the wafer 100 undergoing a first laser annealing process. Fig. 9 For the first treatment, Fig.10 For the second treatment.

[0079] In this embodiment, the second layer structure and the first layer structure are in a serious offset situation, and the wafer 100 is subjected to a first laser annealing process. The absolute value range of the offset in the serious offset situation is: 30 nanometers to 48 nanometers.

[0080] The first laser annealing process includes: performing a first process and a second process on the wafer 100 .

[0081] Please continue to refer to Fig. 9 The first processing includes: taking the first position as the initial point, rotating the wafer 100 clockwise to perform the first processing on the wafer 100, and there is a first angle α1 between the center line Laser of the light spot at the first position and the first connecting line N1.

[0082] Please continue to refer to Fig.10 The second processing includes: taking the second position as the initial point, rotating the wafer 100 clockwise to perform the second processing on the wafer 100, and there is a second angle α2 between the center line Laser of the light spot at the second position and the first line N2.

[0083] In this embodiment, the absolute value of the difference between the first angle α1 and the second angle α2 is 180 degrees, so that the semiconductor structure is subjected to laser annealing on both the front and back sides, thereby avoiding uneven force on the front and back sides of the semiconductor structure.

[0084] In this embodiment, the offset direction of the second layer structure and the first layer structure is offset in a direction away from the isolation region 101, the first angle α1 ranges from 10 degrees to 45 degrees, and the second angle α2 ranges from 190 degrees to 225 degrees.

[0085] In this embodiment, the first treatment is performed first, and then the second treatment is performed. The first angle of the first treatment is smaller than the second angle of the second treatment. The wafer rotates clockwise, and the wafer rotates at a small angle first and then at a large angle along the wafer rotation direction, which can reduce the wafer rotation time and improve production efficiency.

[0086] In other embodiments, the second process can be performed first and then the first process.

[0087] from Fig. 9 and Fig.10 It can be seen that F is the stress direction of the wafer 100 after multiple process treatments and before the first laser annealing treatment, and the angle between F and the first connecting line is 45 degrees; F' is the stress direction generated by the wafer 100 after the first laser annealing treatment, and the angle between F' and F does not overlap, so the first laser annealing treatment with adjusted direction can neutralize and disperse the stress in the stress area on the wafer 100, thereby reducing the stress impact and restoring the second layer structure and the first layer structure from an electrically failed state to an electrically connected state.

[0088] Fig.11 and Fig.12 is a schematic diagram of a process for forming a semiconductor structure in another embodiment of the present invention.

[0089] Please combine Figure 8 refer to Fig.11 and Fig.12 , Fig.11 and Fig.12 is a schematic diagram of the wafer 100 undergoing a first laser annealing process. Fig.11 For the first treatment, Fig.12 For the second treatment.

[0090] In this embodiment, the second layer structure and the first layer structure are in a serious offset situation, and the wafer 100 is subjected to a first laser annealing process. The absolute value range of the offset in the serious offset situation is: 30 nanometers to 48 nanometers.

[0091] The first laser annealing process includes: performing a first process and a second process on the wafer 100 .

[0092] Please continue to refer to Fig.11The first processing includes: taking the first position as the initial point, rotating the wafer 100 clockwise to perform the first processing on the wafer 100, and there is a first angle α1 between the center line Laser of the light spot at the first position and the first connecting line N1.

[0093] Please continue to refer to Fig.12 The second processing includes: taking the second position as the initial point, rotating the wafer 100 clockwise to perform the second processing on the wafer 100, and there is a second angle α2 between the center line Laser of the light spot at the second position and the first line N2.

[0094] In this embodiment, the absolute value of the difference between the first angle α1 and the second angle α2 is 180 degrees, so that the semiconductor structure is subjected to laser annealing on both the front and back sides, thereby avoiding uneven force on the front and back sides of the semiconductor structure.

[0095] In this embodiment, the offset directions of the second layer structure and the first layer structure are offset in the direction toward the isolation region, the first angle α1 ranges from 100 degrees to 135 degrees, and the second angle α2 ranges from 280 degrees to 335 degrees.

[0096] In this embodiment, the first treatment is performed first, and then the second treatment is performed. The first angle of the first treatment is smaller than the second angle of the second treatment. The wafer rotates clockwise, and the wafer rotates at a small angle first and then at a large angle along the wafer rotation direction, which can reduce the wafer rotation time and improve production efficiency.

[0097] In other embodiments, the second process can be performed first and then the first process.

[0098] from Fig.11 and Fig.12 It can be seen that F is the stress direction of the wafer 100 after multiple process treatments and before the first laser annealing treatment, and the angle between F and the first connecting line is 45 degrees; F' is the stress direction generated by the wafer 100 after the first laser annealing treatment, and the angle between F' and F does not overlap, so the first laser annealing treatment with adjusted direction can neutralize and disperse the stress in the stress area on the wafer 100, thereby reducing the stress impact and restoring the second layer structure and the first layer structure from an electrically failed state to an electrically connected state.

[0099] Fig.13 and Fig.14 is a schematic diagram of a process for forming a semiconductor structure in another embodiment of the present invention.

[0100] Please combine Figure 8 refer to Fig.13 and Fig.14 , Fig.13 and Fig.14is a schematic diagram of the wafer 100 undergoing a second laser annealing process. Fig.13 For the first treatment, Fig.14 For the second treatment.

[0101] In this embodiment, the second layer structure and the first layer structure are slightly offset, and the wafer is subjected to a second laser annealing process. The absolute value range of the offset in the slight offset is 12 nanometers to 30 nanometers.

[0102] The second laser annealing process includes: performing a third process and a fourth process on the wafer 100 .

[0103] Please continue to refer to Fig.13 The third processing includes: taking the third position as the initial point, rotating the wafer 100 clockwise to perform the third processing on the wafer 100, and there is a third angle α3 between the center line Laser of the light spot at the third position and the first connecting line N3.

[0104] Please continue to refer to Fig.14 The fourth processing includes: taking the fourth position as the initial point, rotating the wafer 100 clockwise to perform the fourth processing on the wafer 100, and a fourth angle α4 is formed between the center line Laser of the light spot at the fourth position and the first connecting line N4.

[0105] In this embodiment, the absolute value of the difference between the third angle α3 and the fourth angle α4 is 180 degrees, so that the semiconductor structure is subjected to laser annealing on both the front and back sides, thereby avoiding uneven force on the front and back sides of the semiconductor structure.

[0106] In this embodiment, the offset directions of the second layer structure and the first layer structure are offset in the direction toward the isolation region 101 , the third angle α3 is in the range of 90 degrees to 100 degrees, and the fourth angle α4 is in the range of 270 degrees to 280 degrees.

[0107] In this embodiment, the third process is performed first, and then the fourth process. The third angle of the third process is smaller than the fourth angle of the fourth process. The wafer rotates clockwise, and the wafer rotates at a small angle first and then at a large angle along the wafer rotation direction, which can reduce the wafer rotation time and improve production efficiency.

[0108] In other embodiments, the fourth process can be performed first and then the third process.

[0109] from Fig.13 and Fig.14It can be seen that F is the stress direction of the wafer 100 after multiple process treatments and before the second laser annealing treatment, and the angle between F and the first connecting line is 45 degrees; F' is the stress direction generated by the wafer 100 after the second laser annealing treatment, and the angle between F' and F does not overlap, so the second laser annealing treatment with adjusted direction can neutralize and disperse the stress in the stress area on the wafer 100, thereby reducing the stress impact and restoring the second layer structure and the first layer structure from an electrically failed state to an electrically connected state.

[0110] Fig.15 and Fig.16 is a schematic diagram of a process for forming a semiconductor structure in another embodiment of the present invention.

[0111] Please combine Figure 8 refer to Fig.15 and Fig.16 , Fig.15 and Fig.16 is a schematic diagram of the wafer 100 undergoing a second laser annealing process. Fig.15 For the first treatment, Fig.16 For the second treatment.

[0112] In this embodiment, the second layer structure and the first layer structure are slightly offset, and the wafer is subjected to a second laser annealing process. The absolute value range of the offset in the slight offset is 12 nanometers to 30 nanometers.

[0113] The second laser annealing process includes: performing a third process and a fourth process on the wafer 100 .

[0114] Please continue to refer to Fig.15 The third processing includes: taking the third position as the initial point, rotating the wafer 100 clockwise to perform the third processing on the wafer 100, and there is a third angle α3 between the center line Laser of the light spot at the third position and the first connecting line N3.

[0115] Please continue to refer to Fig.16 The fourth processing includes: taking the fourth position as the initial point, rotating the wafer 100 clockwise to perform the fourth processing on the wafer 100, and a fourth angle α4 is formed between the center line Laser of the light spot at the fourth position and the first connecting line N4.

[0116] In this embodiment, the absolute value of the difference between the third angle α3 and the fourth angle α4 is 180 degrees, so that the semiconductor structure is subjected to laser annealing on both the front and back sides, thereby avoiding uneven force on the front and back sides of the semiconductor structure.

[0117] In this embodiment, the offset directions of the second layer structure and the first layer structure are offset in a direction away from the isolation region 101 , the third angle α3 ranges from 0 degrees to 10 degrees, and the fourth angle α4 ranges from 180 degrees to 190 degrees.

[0118] In this embodiment, the third process is performed first, and then the fourth process. The third angle of the third process is smaller than the fourth angle of the fourth process. The wafer rotates clockwise, and the wafer rotates at a small angle first and then at a large angle along the wafer rotation direction, which can reduce the wafer rotation time and improve production efficiency.

[0119] In other embodiments, the fourth process can be performed first and then the third process.

[0120] from Fig.15 and Fig.16 It can be seen that F is the stress direction of the wafer 100 after multiple process treatments and before the second laser annealing treatment, and the angle between F and the first connecting line is 45 degrees; F' is the stress direction generated by the wafer 100 after the second laser annealing treatment, and the angle between F' and F does not overlap, so the second laser annealing treatment with adjusted direction can neutralize and disperse the stress in the stress area on the wafer 100, thereby reducing the stress impact and restoring the second layer structure and the first layer structure from an electrically failed state to an electrically connected state.

[0121] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a wafer, the wafer comprising an isolation region and a device region, wherein the isolation region and the device region are distributed along a first direction parallel to a surface of the wafer; forming a device structure located on the device region, wherein the device structure includes a first layer structure and a second layer structure located on the first layer structure; forming an isolation structure on the wafer, the isolation structure being located on the isolation region and on an area outside the device structure in the device region, the device structure being located within the isolation structure; Obtaining whether electrical failure occurs in the second layer structure and the first layer structure; If the second layer structure and the first layer structure are electrically failed, obtaining the offset of the second layer structure and the first layer structure in the first direction; According to the offset of the second layer structure and the first layer structure in the first direction, the wafer is subjected to laser annealing treatment to restore the electrical connection between the second layer structure and the first layer structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The edge of the wafer has a positioning groove; the laser beam used for the laser annealing process has a projection spot on the surface of the wafer, the projection spot extends along the edge of the wafer to the center of the wafer, and the projection spot has a center line along the radius of the wafer; the positioning groove and the center of the wafer have a first connecting line.

3. The method for forming a semiconductor structure according to claim 2, wherein: The offset conditions of the second layer structure and the first layer structure in the first direction include: an offset degree and an offset direction, wherein the offset degree includes a severe offset condition or a mild offset condition, and the offset direction includes an offset in a direction away from the isolation region or an offset in a direction toward the isolation region; the absolute value range of the offset in the severe offset condition is: 30 nanometers to 48 nanometers; the absolute value range of the offset in the mild offset condition is: 12 nanometers to 30 nanometers.

4. The method for forming a semiconductor structure according to claim 3, wherein: According to the offset of the second layer structure and the first layer structure in the first direction, the wafer is subjected to laser annealing, including: according to the offset degree and offset direction of the second layer structure and the first layer structure in the first direction, the angle of the laser in the laser annealing is adjusted, and the wafer is subjected to laser annealing.

5. The method for forming a semiconductor structure according to claim 4, wherein: When the second layer structure and the first layer structure are seriously offset, a first laser annealing process is performed on the wafer.

6. The method for forming a semiconductor structure according to claim 5, wherein: The first laser annealing treatment includes: performing a first treatment and a second treatment on the wafer; the first treatment includes: taking a first position as an initial point, rotating the wafer to perform the first treatment on the wafer, and a first angle is formed between the center line of the light spot at the first position and the first connecting line; the second treatment includes: taking a second position as an initial point, rotating the wafer to perform the second treatment on the wafer, and a second angle is formed between the center line of the light spot at the second position and the first connecting line.

7. The method for forming a semiconductor structure according to claim 6, wherein: The absolute value of the difference between the first angle and the second angle is 180 degrees.

8. The method for forming a semiconductor structure according to claim 7, wherein: When the offset directions of the second layer structure and the first layer structure are offset in a direction away from the isolation region, the first angle ranges from 10 degrees to 45 degrees, and the second angle ranges from 190 degrees to 225 degrees.

9. The method for forming a semiconductor structure according to claim 7, wherein: When the offset directions of the second layer structure and the first layer structure are offset in a direction toward the isolation region, the first angle ranges from 100 degrees to 135 degrees, and the second angle ranges from 280 degrees to 335 degrees.

10. The method for forming a semiconductor structure according to claim 4, wherein: When the second layer structure and the first layer structure are slightly offset, a second laser annealing process is performed on the wafer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The second laser annealing treatment includes: performing a third treatment and a fourth treatment on the wafer; the third treatment includes: taking the third position as the initial point, rotating the wafer to perform the third treatment on the wafer, and a third angle is formed between the center line of the light spot at the third position and the first connecting line; the fourth treatment includes: taking the fourth position as the initial point, rotating the wafer to perform the fourth treatment on the wafer, and a fourth angle is formed between the center line of the light spot at the fourth position and the first connecting line.

12. The method for forming a semiconductor structure according to claim 11, wherein: The absolute value of the difference between the third angle and the fourth angle is 180 degrees.

13. The method for forming a semiconductor structure according to claim 12, wherein: When the offset directions of the second layer structure and the first layer structure are offset in a direction toward the isolation region, the third angle ranges from 90 degrees to 100 degrees, and the fourth angle ranges from 270 degrees to 280 degrees.

14. The method for forming a semiconductor structure according to claim 12, wherein: When the offset directions of the second layer structure and the first layer structure are offset in a direction away from the isolation region, the third angle ranges from 0 degrees to 10 degrees, and the fourth angle ranges from 180 degrees to 190 degrees.

15. The method for forming a semiconductor structure according to claim 1, wherein: The first layer structure includes: a gate structure located on a wafer and source / drain doped regions located in the wafer on both sides of the gate structure, wherein the source / drain doped regions are located on both sides of the gate structure along a first direction; the second layer structure includes: a conductive plug located on the source / drain doped regions, wherein the conductive plug is electrically connected to the source / drain doped regions.

16. The method for forming a semiconductor structure according to claim 15, wherein: The step of obtaining whether the second layer structure and the first layer structure have electrical failure includes: if the conductive plug and the gate structure are offset in a first direction so that the conductive plug and the gate structure are bridged, then the second layer structure and the first layer structure have electrical failure.

17. The method for forming a semiconductor structure according to claim 1, wherein: The first layer structure includes: a first metal layer located on the wafer, wherein an extension direction of the first metal layer is perpendicular to a first direction; the second layer structure includes: a connection plug located on the first metal layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The step of obtaining whether the second layer structure and the first layer structure have electrical failure includes: if the connecting plug and the first metal layer are offset in a first direction so that the connecting plug and the first metal layer are not in contact, then the second layer structure and the first layer structure have electrical failure.

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