Current limiting circuit based on MOS characteristics and control method

Abstract

The invention provides a current limiting circuit based on MOS characteristics and a control method, the current limiting circuit comprises a mos transistor Q1, a power supply and a load, an S pole of the mos transistor Q1 is connected with the power supply, a D pole of the mos transistor Q1 is connected with the load, a G pole of the mos transistor Q1 is connected with a port 1 of an operational amplifier A2, a port 2 of the operational amplifier A2 is connected with a sampling circuit, and a port 3 of the operational amplifier A2 is connected with a reference circuit. According to the invention, the stability of the output current can be improved after the MOS tube is switched to the constant current region.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply, and in particular to a current limiting circuit and a control method based on MOS characteristics. Background Art

[0002] When the power supply is in normal working state, the MOS tube connected in series at the output end of the power supply needs to work in the deep variable resistance area so that it can be used as a load switch. When the output current of the power supply increases and enters the current limiting control, in order to improve the stability of the output current, under normal circumstances, a differential circuit is used to make VGS follow the value change of VDS so that the MOS enters the constant current area. However, in conventional power supply circuits, when the MOS tube is in the constant current area, the VGS value needs to be dynamically adjusted to follow the value change of VDS. At the same time, the load may be unstable when the MOS tube enters the constant current area. The above situations will all lead to low current stability. Summary of the invention

[0003] In view of this, the problem to be solved by the present invention is to provide a current limiting circuit and a control method based on MOS characteristics, which can improve the stability of the output current after the MOS tube is switched to the constant current region.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A current limiting circuit based on MOS characteristics comprises a MOS tube Q1, wherein the S pole of the MOS tube Q1 is connected to a power supply, the D pole of the MOS tube Q1 is connected to a load, the G pole of the MOS tube Q1 is connected to port 1 of an operational amplifier A2, the port 2 of the operational amplifier A2 is connected to a sampling circuit, and the port 3 of the operational amplifier A2 is connected to a reference circuit.

[0006] Furthermore, the sampling circuit includes an operational amplifier A1 and a resistor Rs, and the resistor Rs is connected in series between the D pole of the MOS tube Q1 and the load;

[0007] Port 3 of the operational amplifier A1 is connected to the load, a resistor R1 is connected in series between port 2 of the operational amplifier A1 and the D pole of the mosfet Q1, port 1 of the operational amplifier A1 is connected to the G pole of the mosfet Q2, the S pole of the mosfet Q2 is connected to port 2 of the operational amplifier A1, the D pole of the mosfet Q2 is connected to port 2 of the operational amplifier A2, and a resistor R2 is connected in series between the D pole of the mosfet Q2 and the ground pole.

[0008] Furthermore, the resistance value of the resistor R1 is equal to the resistance value of the resistor R2.

[0009] Furthermore, the reference circuit includes a control module MCU and a digital-to-analog conversion module DAC, and the digital-to-analog conversion module DAC is connected in series between the control module MCU and the 3-port of the operational amplifier A2.

[0010] Further, the digital-to-analog conversion module DAC is connected to the 3rd port of operational amplifier A2 through operational amplifier A3. The 3rd port of operational amplifier A3 is connected to the digital-to-analog conversion module DAC. The 2nd port and the 1st port of operational amplifier A3 are short-circuited, and the 1st port of operational amplifier A3 is connected to the 3rd port of operational amplifier A2.

[0011] A current limiting circuit control method based on MOS characteristics includes that a reference circuit generates and outputs a threshold voltage VREF according to a power supply threshold, a sampling circuit continuously acquires the supply current I0 of a power supply, converts it and outputs a sampling voltage V3, and sets the supply voltage of operational amplifier A2 to be on the same voltage rail as the power supply voltage Vo, so that VG(max) = Vo;

[0012] Operational amplifier A2 adjusts the G-pole voltage of MOS transistor Q1 based on the ratio of the threshold voltage VREF to the supply voltage V3. When V3 < VREF, it adjusts the G-pole voltage of MOS transistor Q1 to be used as a switch; when V3 ≥ VREF, it adjusts the G-pole voltage of MOS transistor Q1 to satisfy Vo > VG - VGS(th), and MOS transistor Q1 operates in the constant current region to keep the D-pole current of MOS transistor Q1 constant.

[0013] The advantages and positive effects of the present invention are:

[0014] A MOS transistor Q1 and a resistor RS are connected in series between the power supply and the load in sequence. The voltage across resistor R1 is compared with the threshold voltage VREF to judge whether the supply current I0 exceeds the current threshold. If so, operational amplifier A2 automatically adjusts the G-pole voltage of MOS transistor Q1 to stabilize it in the constant current region. The entire process of adjusting the G-pole voltage is automatically reversed by the hardware circuit, without signal processing and feedback processes, greatly reducing the feedback delay and improving the stability of the current when entering the constant current region. Since the supply voltage of operational amplifier A2 is consistent with the power supply output voltage rail, Vo > VG - VGS(th) always holds, which can keep MOS transistor Q1 in the constant current region and improve the stability of the current. Description of the Drawings

[0015] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation to the present invention. In the drawings:

[0016] Figure 1 is the overall circuit diagram of a current limiting circuit based on MOS characteristics of the present invention. Detailed Embodiments

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0019] The present invention provides a current limiting circuit based on MOS characteristics, such as Figure 1 As shown, it includes a power supply for providing electric energy and a load for consuming electric energy, and a MOS tube Q1 and a resistor Rs are connected in series between the power supply and the load in sequence. The D pole of the MOS tube Q1 is connected to the power supply, the S pole of the MOS tube Q1 is connected to one end of the resistor Rs, and the other end is connected to the load. The power supply current Io of the power supply is determined by the voltage across the resistor Rs. When the power supply current exceeds the current threshold, the G pole voltage of the MOS tube Q1 is automatically adjusted to switch it to the constant current region, thereby improving the stability of the power supply current Io.

[0020] When the supply current Io does not exceed the current threshold, the G-pole voltage of the MOS tube Q1 is adjusted to be in the variable resistance area, and the MOS tube Q1 is used as a low-loss switch; when the supply current Io exceeds the current threshold, the G-pole voltage of the MOS tube Q1 is automatically adjusted to stabilize it in the constant current area, and the current output by the power supply is clamped at the set current threshold to keep the supply current Io constant.

[0021] In order to facilitate the adjustment of the G pole voltage of the MOS tube Q1, the G pole of the MOS tube Q1 is connected to the 1 port of the operational amplifier A2, and the 2 port of the operational amplifier A2 is connected to the sampling circuit. The sampling circuit is used to collect the power supply current Io connected to the resistor RS and convert it into a sampling voltage V3; the 3 port of the operational amplifier A2 is connected to the reference circuit, and the reference circuit generates a threshold voltage VREF according to the current threshold.

[0022] The sampling circuit includes an operational amplifier A1, wherein port 3 of the operational amplifier A1 is connected to the load, a resistor R1 is connected in series between port 2 of the operational amplifier A1 and the D pole of the mosfet Q1, port 1 of the operational amplifier A1 is connected to the G pole of the mosfet Q2, the S pole of the mosfet Q2 is connected to port 2 of the operational amplifier A1, the D pole of the mosfet Q2 is connected to port 2 of the operational amplifier A2, and a resistor R2 is connected in series between the D pole of the mosfet Q2 and the ground pole.

[0023] The resistor R1 is connected in parallel with the resistor RS through the operational amplifier A1. When the operational amplifier A1 is in the virtual short state, the voltages at the 2nd port and the 3rd port of the operational amplifier A1 are the same. Therefore, the voltages across the resistor R1 and the resistor RS are the same. The operational amplifier A1 controls the MOS transistor Q2 to conduct, connecting the resistor R1 and the resistor R2 in series, so that the currents flowing through the resistor R1 and the resistor R2 are the same. Define the D - pole voltage of the MOS transistor Q2 as the sampling voltage V3 and input it to the 2nd port of the operational amplifier A2.

[0024] An embodiment of the present application is that the resistance value of the resistor R1 is equal to that of the resistor R2, which can make the sampling voltage V3 equal to the voltage across the resistor R1 or the resistor RS.

[0025] The reference circuit includes a control module MCU and a digital - to - analog conversion module DAC. The digital - to - analog conversion module DAC is connected in series between the control module MCU and the 3rd port of the operational amplifier A2. The supply voltage of the operational amplifier A2 is adjusted according to the supply voltage Vo. The supply voltage of the operational amplifier A2 is used to limit the voltage range output at its 1st port, making the voltage range consistent with the supply voltage Vo of the power supply. The control module MCU generates a digital signal according to the supply threshold, and the digital - to - analog conversion module DAC converts the digital signal into a threshold voltage VREF and applies it to the 3rd port of the operational amplifier A2.

[0026] An embodiment of the present application is that the digital - to - analog conversion module DAC is connected to the 3rd port of the operational amplifier A2 through the operational amplifier A3. The operational amplifier A3 is used to improve the stability of the threshold voltage VREF. The specific circuit structure is: the 3rd port of the operational amplifier A3 is connected to the digital - to - analog conversion module DAC, the 2nd port of the operational amplifier A3 is short - circuited with the 1st port, and the 1st port of the operational amplifier A3 is connected to the 3rd port of the operational amplifier A2.

[0027] A current - limiting circuit control method based on MOS characteristics. The reference circuit generates a threshold voltage VREF according to the supply threshold, and the sampling circuit continuously acquires the supply current I0 and converts it into a sampling voltage V3;

[0028] Adjust the G - pole voltage of the MOS transistor Q1 based on the ratio of the threshold voltage VREF to the supply voltage V3. When V3 < VREF, adjust the G - pole voltage of the MOS transistor Q1 to make it used as a switch; when V3 ≥ VREF, adjust the G - pole voltage of the MOS transistor Q1 to always satisfy Vo > VG - VGS(th), and the MOS transistor Q1 operates in the constant - current region, keeping the D - pole current of the MOS transistor Q1 constant.

[0029] The principle is as follows: Set the input voltage of the resistor Rs as V1, the output voltage as V2, the voltage at the 2nd port of the operational amplifier A1 as V -, and the input voltage of the load as Vload.

[0030] The supply current Io is: Io=(V1-V2) / Rs, so we can get: V1-V2=Io×Rs; since V-=V2, the current of resistor R1=(V1-V-) / R1=(Io×Rs) / R1.

[0031] Since the current flowing through R1 = the current of resistor R2, the sampling voltage V3 of the D pole of MOS tube Q2 can be obtained: V3 = Io×Rs×(R2 / R1), R2 / R1 is the current sampling gain coefficient, and the gain between the sampling voltage V3 and the voltage of resistor Rs is determined by the ratio between resistor R2 and resistor R1.

[0032] Assuming R2 / R1=1, then V3=Io×Rs; V1=V2+Io×Rs=Vload+Io×Rs; the driving voltage VGS of MOSFET Q1=VG-V1=VG-Vload-V3.

[0033] When the voltage between the three poles of MOS tube Q1 satisfies: VDS>VGS-VGS(th), MOS tube Q1 works in the constant current region, where VGS(th) is the maximum value set by VGS, which is determined based on the performance of the MOS tube itself. Substitute the voltage of the three poles of MOS tube Q1 into the constant current region formula: Vo-V1>VG-Vload-V3-VGS(th)→Vo-Vload-V3>VG-Vload-V3-VGS(th); convert it to: Vo>VG-VGS(th),

[0034] Therefore, the condition for the MOS tube Q1 in this circuit to work in the constant current region is Vo>VG-VGS(th), VG is provided by port 1 of the operational amplifier A2, so that the supply voltage of the operational amplifier A2 and the supply voltage Vo of the power supply are in the same voltage rail, and VG(max)=Vo can be obtained. When the output current of the power supply exceeds the power supply threshold, VG=Vo, and then Vo>VG-VGS(th) is always established, the MOS tube Q1 always works in the constant current region, and the current flowing through the power supply is clamped at the set current limit threshold.

[0035] The embodiments of the present invention are described in detail above, but the contents described are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of this patent.

Claims

1. A current limiting circuit based on MOS characteristics, characterized in that: It includes an MOS transistor Q1. The D pole of the MOS transistor Q1 is connected to a power supply. The S pole of the MOS transistor Q1 is connected to a load. The G pole of the MOS transistor Q1 is connected to the 1 port of an operational amplifier A2. The 2 port of the operational amplifier A2 is connected to a sampling circuit. The sampling circuit includes an operational amplifier A1 and a resistor Rs. A resistor Rs is connected in series between the D pole of the MOS transistor Q1 and the load. The 3 port of the operational amplifier A1 is connected to the load. A resistor R1 is connected in series between the 2 port of the operational amplifier A1 and the D pole of the MOS transistor Q1. The 1 port of the operational amplifier A1 is connected to the G pole of an MOS transistor Q2. The S pole of the MOS transistor Q2 is connected to the 2 port of the operational amplifier A1. The D pole of the MOS transistor Q2 is connected to the 2 port of the operational amplifier A2. A resistor R2 is connected in series between the D pole of the MOS transistor Q2 and the ground electrode.

2. A current limiting circuit based on MOS characteristics according to claim 1, characterized in that: The resistance value of the resistor R1 is equal to the resistance value of the resistor R2.

3. A current limiting circuit based on MOS characteristics according to claim 1, characterized in that: The 3 port of the operational amplifier A2 is connected to a reference circuit. The reference circuit includes a control module MCU and a digital-to-analog conversion module DAC. A digital-to-analog conversion module DAC is connected in series between the control module MCU and the 3 port of the operational amplifier A2.

4. A current limiting circuit based on MOS characteristics according to claim 3, characterized in that: The digital-to-analog conversion module DAC is connected to the 3 port of the operational amplifier A2 through an operational amplifier A3. The 3 port of the operational amplifier A3 is connected to the digital-to-analog conversion module DAC. The 2 port of the operational amplifier A3 is short-circuited with the 1 port. The 1 port of the operational amplifier A3 is connected to the 3 port of the operational amplifier A2.

5. A method for controlling a current limiting circuit based on MOS characteristics, based on a current limiting circuit based on MOS characteristics as claimed in any one of claims 1 to 4, characterized in that: It includes that the reference circuit generates a threshold voltage VREF according to a power supply threshold. The sampling circuit continuously samples the supply current I0 of the power supply and generates a sampling voltage V3. The supply voltage of the operational amplifier A2 and the supply voltage Vo of the power supply are on the same voltage rail, so that the gate voltage VG(max) of the MOS transistor Q1 = Vo. The operational amplifier A2 adjusts the gate voltage VG of the MOS transistor Q1 based on the ratio of the threshold voltage VREF to the supply voltage V3. When V3 < VREF, it adjusts the gate voltage of the MOS transistor Q1 to make it a switch. When V3 ≥ VREF, it adjusts the gate voltage of the MOS transistor Q1 to always satisfy Vo > VG - VGS(th). The MOS transistor Q1 operates in the constant current region to keep the D pole current of the MOS transistor Q1 constant.

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