A power-down reset circuit based on an sram array

Abstract

The application discloses a power-down reset circuit based on an SRAM array, which comprises a starting control circuit, a starting circuit, a current reference circuit, a current mirror and an SRAM array. The starting control circuit generates a starting signal according to a power supply voltage; the starting circuit makes the current reference circuit work stably to get rid of degenerate points according to the starting signal; the current reference circuit generates a load current of the SRAM according to the power supply voltage under the influence of the starting circuit; the current mirror copies the load current to each SRAM in the SRAM array; each SRAM compares the load current and the latch current of its own latch respectively, and outputs respective comparison results; and an output logic circuit outputs a control signal according to all the comparison results to control whether the FPGA chip is reset. The starting control circuit and the starting circuit are introduced to get rid of degenerate points; the comparison between the load current and the SRAM latch current is adopted to change the SRAM output value, and the reference voltage and the resistance string are omitted, so that the circuit area is reduced and the power consumption is lowered.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of power management integrated circuits, and particularly relates to a power-down reset circuit based on an SRAM array. BACKGROUND

[0002] In the power management system of an FPGA (Field Programmable Gate Array) chip, a brown-out reset circuit can be used to provide a power drop warning signal for the FPGA. Once it is found that the VCC power supply has dropped to a certain threshold (trip point), the FPGA is reset in time to prevent the system from losing control. The main purpose is to ensure that the FPGA can recover to the initial state after power failure, thereby avoiding problems such as uncertain circuit state or data loss caused by power failure.

[0003] The existing power-down reset circuit mainly uses a comparator structure to compare the power supply voltage. When the power supply voltage drops to the trip point, the comparator flips and generates a reset signal to provide to the circuit. However, the existing comparator needs a reference voltage when comparing the power supply voltage, and uses a resistor string for voltage division, which requires a large power consumption and area. In addition, in the circuit with a power supply-independent reference current, there is a "degeneracy point" problem, that is: for the reference current generation circuit, if all transistors transmit zero current when the power is on, since the branches on both sides of the loop allow zero current, they can remain off indefinitely. This situation is difficult to predict. SUMMARY

[0004] In order to solve the above problems in the prior art, the present application provides a power-down reset circuit based on an SRAM array. The technical problem to be solved by the present application is solved by the following technical scheme:

[0005] The present application provides a power-down reset circuit based on an SRAM array, comprising:

[0006] a start control circuit, a start circuit, a current reference circuit, a current mirror, an SRAM array, and an output logic circuit; the SRAM array comprises a plurality of SRAMs; wherein,

[0007] The start control circuit is configured to generate a start signal startup according to the power supply voltage VCC.

[0008] The start circuit is configured to enable the current reference circuit to work stably to escape from the degeneracy point according to the start signal startup.

[0009] The current reference circuit is configured to generate a load current of the SRAM according to the power supply voltage VCC under the influence of the start circuit.

[0010] The current mirror is used to copy the load current to each SRAM in the SRAM array;

[0011] The SRAM array is used to compare the load current and the latch current of its own latch using each SRAM, and output the comparison results respectively.

[0012] The output logic circuit is used to output a reset signal por_n based on all comparison results, so as to control whether the FPGA chip is reset.

[0013] The beneficial effects of this invention are:

[0014] The solution provided by this invention introduces a startup control circuit and a startup circuit, which can drive the current reference circuit to get rid of the degeneracy point when the power supply is powered on, so that the current reference circuit can work stably, and the startup circuit can be shut down after the circuit starts normally. The SRAM output value is changed by comparing the load current with the SRAM latch current in the SRAM array, and then a reset signal is given. The reference voltage and the resistor string used for voltage division are omitted, thereby greatly reducing the circuit area. After enabling the power supply voltage detection to be turned off, it serves as a low-power circuit for detecting the drop in power supply voltage, thereby reducing power consumption. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a power-down reset circuit based on an SRAM array provided in an embodiment of the present invention;

[0016] Figure 2 A schematic diagram illustrating a degeneracy point;

[0017] Figure 3 This is a partial structural diagram of an SRAM detection circuit with an added startup circuit provided in an embodiment of the present invention.

[0018] Figure 4 This is a schematic diagram of a startup control circuit provided in an embodiment of the present invention;

[0019] Figure 5 This is a schematic diagram illustrating how the startup signal changes with VCC, provided in an embodiment of the present invention.

[0020] Figure 6 This is a schematic diagram of the structure of an output logic circuit provided in an embodiment of the present invention;

[0021] Figure 7 This is a schematic diagram of the power supply and circuit output provided in an embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0023] This invention provides a power-down reset circuit based on an SRAM array, such as... Figure 1 As shown, it may include:

[0024] The circuit includes a startup control circuit, a startup circuit, a current reference circuit, a current mirror, an SRAM array, and an output logic circuit; the SRAM array comprises multiple SRAMs; among which,

[0025] The startup control circuit is used to generate a startup signal based on the power supply voltage VCC.

[0026] The startup circuit is used to stabilize the current reference circuit and get it out of the degeneracy point based on the startup signal.

[0027] The current reference circuit is used to generate the load current of the SRAM based on the power supply voltage VCC under the influence of the startup circuit.

[0028] A current mirror is used to copy the load current to each SRAM in an SRAM array.

[0029] The SRAM array is used to compare the load current and the latch current of its own latch with each SRAM, and output the comparison results respectively.

[0030] The output logic circuit is used to output a reset signal por_n based on all comparison results, in order to control whether the FPGA chip is reset.

[0031] After a chip powers on, the power detection circuit is usually turned off to save power. This invention uses an SRAM (Static Random-Access Memory) array to detect a drop in power supply voltage. The main purpose of designing the SRAM array to detect the VCC power supply is to detect a drop in power supply voltage after the power supply voltage detection circuit is turned off following power-on. A crucial issue in circuits with a reference current independent of the power supply is the existence of a "degenerate point," such as... Figure 2As shown, for a reference current generation circuit, if all transistors carry zero current when the power supply is on, they can remain off indefinitely due to the zero current allowed by the branches on both sides of the loop, making this situation difficult to predict. In other words, the circuit can stabilize in two different operating states; this problem is called the circuit startup problem, which can be solved by introducing a startup control circuit and a startup circuit. When the power supply is on, the current reference circuit can be driven out of its degeneracy point, allowing it to operate stably. The startup circuit can be shut down after the circuit starts normally. The SRAM output value is changed by comparing the load current with the SRAM latch current in the SRAM array, thus providing a reset signal. This eliminates the need for a reference voltage and a resistor string for voltage division, significantly reducing the circuit area. After enabling / disabling power supply voltage detection, it functions as a low-power circuit for detecting power supply voltage drops, thereby reducing power consumption.

[0032] Figure 3 This is a partial structural diagram of an SRAM detection circuit with an added startup circuit. Figure 4 This is a schematic diagram of a start-up control circuit provided in an embodiment of the present invention. For ease of understanding, it will be described below in conjunction with... Figure 3 and Figure 4 The various modules of the SRAM array-based power-down reset circuit provided in the embodiments of the present invention will be described.

[0033] Start-up control circuit

[0034] Start-up control circuit, such as Figure 4 As shown, it may include:

[0035] MOSFETs M1, M2, and M3; first inverter T1; second inverter T2; coupling capacitors C1, C2, and C3; voltage divider resistors R1 and R2; among which,

[0036] The source of MOSFET M1 is connected to the power supply voltage VCC, the gate is connected to its own source, and the drain is connected to the second terminal of the coupling capacitor C1.

[0037] The source of MOSFET M2 is grounded, the gate is connected to the first terminal of coupling capacitor C2, and the drain is connected to the second terminal of coupling capacitor C1.

[0038] The source of MOSFET M3 is connected to the source of MOSFET M2, the gate is connected to its own source, and the drain is used as the output terminal of the start-up control circuit.

[0039] The input terminal of the first inverter T1 is connected to the drain of the MOSFET M3, and the output terminal is connected to the second terminal of the coupling capacitor C1. The first terminal is connected to the power supply voltage VCC, and the second terminal is grounded.

[0040] The input terminal of the second inverter T2 is connected to the second terminal of the coupling capacitor C1, and the output terminal is connected to the drain of the MOSFET M3. The first terminal is connected to the power supply voltage VCC, and the second terminal is grounded.

[0041] The first terminal of the coupling capacitor C1 is connected to the source of the MOSFET M1;

[0042] The first end of the coupling capacitor C2 is connected to the second end of the voltage divider resistor R1, and the second end is connected to the source of the MOSFET M2.

[0043] The first end of the coupling capacitor C3 is connected to the drain of the MOSFET M3, and the second end is connected to the source of the MOSFET M3.

[0044] The first terminal of voltage divider resistor R1 is connected to the power supply voltage VCC, and the second terminal is connected to the first terminal of voltage divider resistor R2.

[0045] The second terminal of the voltage divider resistor R2 is connected to the second terminal of the coupling capacitor C2.

[0046] The startup control circuit is used to generate a startup signal based on the power supply voltage VCC. Specifically, Figure 5 This is a schematic diagram illustrating the variation of the startup signal with VCC according to an embodiment of the present invention. Figure 5 As can be seen, the startup control circuit uses a cross inverter to control the latch structure, voltage divider resistors, and coupling capacitors, causing the startup signal to change during power-up as follows: Figure 5 As shown, Figure 5 In the middle, low_level indicates a low level.

[0047] Start-up circuit

[0048] Start-up circuit such as Figure 3 As shown, it may include:

[0049] MOSFETs M4, M5, M6, M7, and M8; among them,

[0050] The source of the MOSFET M4 is connected to the power supply voltage VCC, the gate is connected to the startup signal, and the drain is connected to the source of the MOSFET M5.

[0051] The gate of the MOS transistor M5 is connected to its own drain, and its drain is connected to the drain of the MOS transistor M7.

[0052] The source of the MOSFET M6 is grounded, its gate is connected to the gate of the MOSFET M7, and its drain serves as the output terminal of the startup circuit.

[0053] The source of the MOS transistor M7 is connected to the source of the MOS transistor M8, and the gate is connected to its own drain.

[0054] The source of the MOS transistor M8 is connected to the source of the MOS transistor M6, the gate is connected to the start-up signal, and the drain is connected to the gate of the MOS transistor M7.

[0055] The startup circuit is used to stabilize the current reference circuit and allow it to escape the degeneracy point based on the startup signal. Specifically, the startup signal remains low during the initial power-up phase, turning on PMOS transistors M4 and M5. This generates a small current in the rightmost branch of the startup circuit, which is replicated into the current reference circuit through the current mirror formed by NMOS transistors M6 and M7, forcing the circuit to escape zero current. As the power supply voltage VCC rises sufficiently, the startup signal, based on the increased power supply voltage VCC, turns off PMOS transistors M4 and M5 and turns on NMOS transistor M8 below the current mirror, thereby shutting down the startup circuit. It is understood that this embodiment of the invention, by introducing a startup control circuit and a startup circuit, can drive the current reference circuit to escape the degeneracy point when the power supply is powered on, enabling the current reference circuit to operate stably, and can shut down the startup circuit after the circuit has started normally.

[0056] Current reference circuit

[0057] Current reference circuit, such as Figure 3 As shown, it may include:

[0058] MOSFETs M9, M10, NMs, and NMb, and resistor R3; among them,

[0059] The source of MOSFET M9 is connected to the source of MOSFET M10, the gate is connected to the gate of MOSFET M10, and the drain is connected to the drain of MOSFET NMs.

[0060] The source of MOSFET M10 is connected to the power supply voltage VCC, the gate is connected to its own drain, and the drain is connected to the drain of MOSFET NMb.

[0061] The source of MOSFET NMs is grounded, and its gate is connected to the gate of MOSFET NMb.

[0062] The source of the MOSFET NMb is connected to the first end of resistor R3, the gate is connected to the current mirror, and the drain is connected to the output of the startup circuit.

[0063] The second terminal of resistor R3 is grounded.

[0064] The current reference circuit is used to generate the SRAM load current based on the power supply voltage VCC under the influence of the startup circuit. Specifically, the SRAM load current is very small, generated by a current reference circuit independent of the power supply voltage, and then replicated as the SRAM load current through a current mirror. This current is generated by two MOSFETs (NMs and NMb) of different sizes and resistors. The size of MOSFET NMs is smaller than that of MOSFET NMb, and the different MOSFET sizes produce a gate-source voltage difference ΔVgs. The source series resistance of the larger MOSFET is R3, which is the source series resistance of MOSFET NMb. Therefore, Vgs(NMb) = Vgs(NMs) + I*R3 ， We get I = ΔVgs / R3 ； Among them, Vgs(NMb) 表示 The gate-source voltage of the MOSFET NMb is represented by Vgs(NMs). Based on the circuit structure and dimensions, this current is very small, approximately 320nA. Because ΔVgs is very small, a large aspect ratio (W / L) should be chosen in the circuit design to reduce the impact of mismatch.

[0065] Current mirror

[0066] Current mirror Figure 3 As shown, it may include:

[0067] MOSFETs M11, M12, M13, M14, M15, M16, M17, and M18; among them,

[0068] The source of MOSFET M11 is connected to the source of MOSFET M9 and connected to the power supply voltage VCC. The gate of MOSFET M11 is connected to the gate of MOSFET M13, and the drain of MOSFET M12 is connected to the drain of MOSFET M12.

[0069] The source of MOSFET M12 is connected to the source of MOSFET NMs, the gate is connected to the gate of MOSFET NMs, and the drain is connected to the gate of MOSFET M11.

[0070] The source of MOSFET M13 is connected to the source of MOSFET M11, the gate is connected to the drain of MOSFET M11, and the drain is connected to the SRAM array accordingly.

[0071] The source of MOSFET M14 is connected to the source of MOSFET M12, the gate is connected to the gate of MOSFET M12, and the drain is connected to the SRAM array accordingly.

[0072] The source of MOSFET M15 is connected to the source of MOSFET M13, the gate is connected to the gate of MOSFET M13, and the drain is connected to the SRAM array accordingly.

[0073] The source of MOSFET M16 is connected to the source of MOSFET M14, the gate is connected to the gate of MOSFET M14, and the drain is connected to the SRAM array accordingly.

[0074] The source of MOSFET M17 is connected to the source of MOSFET M15, the gate is connected to the gate of MOSFET M15, and the drain is connected to the SRAM array accordingly.

[0075] The source of MOSFET M18 is connected to the source of MOSFET M16, the gate is connected to the gate of MOSFET M16, and the drain is connected to the SRAM array.

[0076] A current mirror is used to copy the load current to each SRAM in an SRAM array.

[0077] SRAM array

[0078] SRAM arrays such as Figure 3 As shown, it may include:

[0079] SRAM1, SRAM2, and SRAM3; among which...

[0080] The d terminal of SRAM1 is connected to the source of MOSFET M11, the dn terminal is connected to the source of MOSFET M12, the qb terminal is connected to the drain of MOSFET M13, and the q terminal is connected to the drain of MOSFET M14.

[0081] The d terminal of SRAM2 is connected to the source of MOSFET M13, the dn terminal is connected to the source of MOSFET M14, the qb terminal is connected to the drain of MOSFET M15, and the q terminal is connected to the drain of MOSFET M16.

[0082] The d terminal of SRAM3 is connected to the source of MOSFET M15, the dn terminal is connected to the source of MOSFET M16, the qb terminal is connected to the drain of MOSFET M17, and the q terminal is connected to the drain of MOSFET M18.

[0083] The SRAM array is used to compare the load current and the latch current of its own latch using each SRAM, and output the comparison results. Specifically, in this embodiment of the invention, the main function of the SRAM array for detecting the power supply voltage VCC is to detect the drop in power supply voltage after the power supply voltage detection circuit is turned off after power-on.

[0084] Output logic circuit

[0085] Output logic circuits such as Figure 6 As shown, it may include:

[0086] First NOR gate, AND gate, and second NOR gate; among which...

[0087] The first input terminal of the first NOR gate is connected to the q terminal of SRAM1, the second input terminal is connected to the q terminal of SRAM2, the third input terminal is connected to the q terminal of SRAM3, and the output terminal is connected to the first input terminal of the second NOR gate.

[0088] The first input of the AND gate is connected to the qb terminal of SRAM1, the second input is connected to the qb terminal of SRAM2, the third input is connected to the qb terminal of SRAM3, and the output is connected to the second input of the second NOR gate.

[0089] The output of the second NOR gate serves as the output of the output logic circuit, outputting the reset signal por_n.

[0090] The output logic circuit is used to output a reset signal por_n based on all comparison results, in order to control whether the FPGA chip is reset.

[0091] Specifically, after the FPGA chip powers on, the addr0 signal of the SRAM array is low. The SRAM in the circuit functions as a storage device. The three SRAM array outputs q1 = q2 = q3 = 1.2 (the high level of VCC is 1.2), q1b = q2b = q3b = 0 (the low level of VCC is 0). Their output relationship satisfies... Figure 6 The output logic circuit diagram shown indicates that the reset signal por_n = 1.2, thus releasing the FPGA chip from its reset state and allowing it to operate normally. The SRAM output has a load current, with a pull-down current at the q terminal and a pull-up current at qb. When the power supply voltage drops, the load current of the SRAM is compared with the current capability of the latch in the SRAM. When the driving capability of the load current is greater than that of the latch, the output value of the SRAM will change, pulling down the current at the q terminal and raising the current at the qb terminal, i.e., q1 = q2 = q3 = 0, q1b = q2b = q3b = 1.2, and the reset signal por_n = 0. When the power supply voltage drops to the trip point, the FPGA chip is reset. It is understandable that this embodiment of the invention uses a three-channel SRAM array to ensure that the SRAM eliminates the risk of accidental state changes that might occur when using only one channel, i.e., soft errors could cause unexpected SRAM flips. Specifically, when designing the layout, a single-channel SRAM requires eight SRAMdummies to surround it at the center. All three SRAMs use this layout, placing them as far apart as possible to avoid the risk of soft errors causing unexpected SRAM flipping. The SRAM cells and load current are initialized after power-on, so the SRAM does not detect the VCC power-on process. Figure 7 This is a schematic diagram of the power supply and circuit output provided in an embodiment of the present invention. Figure 7As can be seen, during the power-on process, its output rises with the power supply voltage VCC. When VCC falls and reaches the SRAM switching point, it outputs a low-level reset signal por_n to control the FPGA chip to reset.

[0092] Understandably, modeling SRAM flip-flops is very difficult. This invention's embodiment is based on the SRAM's leakage current. The SRAM leakage current is quite small, but it varies significantly with changes in process, power supply voltage, and temperature. The load current generated by the reference current generation method in this invention's embodiment is significantly larger than the SRAM leakage current, thus facilitating SRAM flip-flop detection. Most existing methods generate reference current through a bandgap reference circuit. Compared to this invention's embodiment, these existing methods generate a much larger reference current. Furthermore, the reference current generated by the bandgap needs to be replicated to the SRAM through several current mirrors, resulting in significantly larger area and power consumption compared to this invention, negating the initial goal of power saving. The bandgap circuit also requires bipolar junction transistors (BJTs) and clamping structures, necessitating a higher power supply voltage. The dynamic range of the SRAM's power supply voltage VCC does not meet the requirements of the bandgap structure; therefore, generating the reference current using the bandgap structure requires an additional, higher power supply voltage. If the bandgap is forced to shut down, the circuit loses its detection function. This invention, through the introduction of a startup control circuit and a startup circuit, enables the current reference circuit to escape the degeneracy point when the power supply is powered on, allowing the current reference circuit to operate stably. Furthermore, the startup circuit can be shut down after the circuit has started normally. The SRAM output value is changed by comparing the load current with the SRAM latch current in the SRAM array, thereby providing a reset signal. This eliminates the need for a reference voltage and a resistor string for voltage division, significantly reducing the circuit area. When the power supply voltage detection is enabled or disabled, it functions as a low-power circuit for detecting a drop in power supply voltage, thus reducing power consumption.

[0093] It should be noted that, in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0094] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A power-down reset circuit based on an SRAM array, characterized in that, include: Startup control circuit, startup circuit, current reference circuit, current mirror, SRAM array and output logic circuit; The SRAM array includes multiple SRAMs; wherein... The startup control circuit is used to generate a startup signal based on the power supply voltage VCC. The startup circuit is used to stabilize the current reference circuit to overcome the degeneracy point according to the startup signal startup; the startup circuit includes: MOSFETs M4, M5, M6, M7, and M8; among them, The source of the MOSFET M4 is connected to the power supply voltage VCC, the gate is connected to the startup signal, and the drain is connected to the source of the MOSFET M5. The gate of the MOS transistor M5 is connected to its own drain, and its drain is connected to the drain of the MOS transistor M7. The source of the MOSFET M6 is grounded, its gate is connected to the gate of the MOSFET M7, and its drain serves as the output terminal of the startup circuit. The source of the MOS transistor M7 is connected to the source of the MOS transistor M8, and the gate is connected to its own drain. The source of the MOSFET M8 is connected to the source of the MOSFET M6, the gate is connected to the start-up signal, and the drain is connected to the gate of the MOSFET M7. The current reference circuit is used to generate the load current of the SRAM based on the power supply voltage VCC under the influence of the startup circuit. The current mirror is used to copy the load current to each SRAM in the SRAM array; the current mirror includes: MOSFETs M11, M12, M13, M14, M15, M16, M17, and M18; among them, The source of the MOSFET M11 is connected to the power supply voltage VCC, the gate is connected to the gate of the MOSFET M13, and the drain is connected to the drain of the MOSFET M12. The source of the MOS transistor M12 is grounded, its gate is connected to the output terminal of the current reference circuit, and its drain is connected to the gate of the MOS transistor M11. The source of the MOS transistor M13 is connected to the source of the MOS transistor M11, the gate is connected to the drain of the MOS transistor M11, and the drain is connected to the SRAM array. The source of the MOS transistor M14 is connected to the source of the MOS transistor M12, the gate is connected to the gate of the MOS transistor M12, and the drain is connected to the SRAM array. The source of the MOS transistor M15 is connected to the source of the MOS transistor M13, the gate is connected to the gate of the MOS transistor M13, and the drain is connected to the SRAM array accordingly. The source of the MOS transistor M16 is connected to the source of the MOS transistor M14, the gate is connected to the gate of the MOS transistor M14, and the drain is connected to the SRAM array accordingly. The source of the MOS transistor M17 is connected to the source of the MOS transistor M15, the gate is connected to the gate of the MOS transistor M15, and the drain is connected to the SRAM array accordingly. The source of the MOS transistor M18 is connected to the source of the MOS transistor M16, the gate is connected to the gate of the MOS transistor M16, and the drain is connected to the SRAM array accordingly. The SRAM array is used to compare the load current and the latch current of its own latch using each SRAM, and output the comparison result respectively; the SRAM array includes: SRAM1, SRAM2, and SRAM3; among which... The d terminal of the SRAM1 is connected to the source of the MOS transistor M11, the dn terminal is connected to the source of the MOS transistor M12, the qb terminal is connected to the drain of the MOS transistor M13, and the q terminal is connected to the drain of the MOS transistor M14. The d terminal of the SRAM2 is connected to the source of the MOS transistor M13, the dn terminal is connected to the source of the MOS transistor M14, the qb terminal is connected to the drain of the MOS transistor M15, and the q terminal is connected to the drain of the MOS transistor M16. The d terminal of the SRAM3 is connected to the source of the MOS transistor M15, the dn terminal is connected to the source of the MOS transistor M16, the qb terminal is connected to the drain of the MOS transistor M17, and the q terminal is connected to the drain of the MOS transistor M18. The output logic circuit is used to output a reset signal por_n based on all comparison results, so as to control whether the FPGA chip is reset.

2. The power-down reset circuit based on an SRAM array according to claim 1, characterized in that, The start-up control circuit includes: MOSFETs M1, M2, and M3; first inverter T1; second inverter T2; coupling capacitors C1, C2, and C3; voltage divider resistors R1 and R2; among which, The source of the MOS transistor M1 is connected to the power supply voltage VCC, the gate is connected to its own source, and the drain is connected to the second end of the coupling capacitor C1. The source of the MOS transistor M2 is grounded, the gate is connected to the first end of the coupling capacitor C2, and the drain is connected to the second end of the coupling capacitor C1. The source of the MOS transistor M3 is connected to the source of the MOS transistor M2, the gate is connected to its own source, and the drain is used as the output terminal of the startup control circuit. The input terminal of the first inverter T1 is connected to the drain of the MOSFET M3, and the output terminal is connected to the second terminal of the coupling capacitor C1. The first terminal is connected to the power supply voltage VCC, and the second terminal is grounded. The input terminal of the second inverter T2 is connected to the second terminal of the coupling capacitor C1, the output terminal is connected to the drain of the MOSFET M3, the first terminal is connected to the power supply voltage VCC, and the second terminal is grounded. The first terminal of the coupling capacitor C1 is connected to the source of the MOS transistor M1; The first end of the coupling capacitor C2 is connected to the second end of the voltage divider resistor R1, and the second end is connected to the source of the MOS transistor M2. The first end of the coupling capacitor C3 is connected to the drain of the MOS transistor M3, and the second end is connected to the source of the MOS transistor M3. The first terminal of the voltage divider resistor R1 is connected to the power supply voltage VCC, and the second terminal is connected to the first terminal of the voltage divider resistor R2. The second end of the voltage divider resistor R2 is connected to the second end of the coupling capacitor C2.

3. The power-down reset circuit based on an SRAM array according to claim 1, characterized in that, The current reference circuit includes: MOSFETs M9, M10, NMs, and NMb, and resistor R3; among them, The source of the MOS transistor M9 is connected to the source of the MOS transistor M10, the gate is connected to the gate of the MOS transistor M10, and the drain is connected to the drain of the MOS transistor NMs. The source of the MOS transistor M10 is connected to the power supply voltage VCC, the gate is connected to its own drain, and the drain is connected to the drain of the MOS transistor NMb. The source of the MOS transistor NMs is grounded, and its gate is connected to the gate of the MOS transistor NMb. The source of the MOS transistor NMb is connected to the first end of the resistor R3, the gate is connected to the current mirror, and the drain is connected to the output of the startup circuit. The second terminal of resistor R3 is grounded.

4. The power-down reset circuit based on an SRAM array according to claim 1, characterized in that, The output logic circuit includes: First NOR gate, AND gate, and second NOR gate; among which... The first input terminal of the first NOR gate is connected to the q terminal of SRAM1, the second input terminal is connected to the q terminal of SRAM2, the third input terminal is connected to the q terminal of SRAM3, and the output terminal is connected to the first input terminal of the second NOR gate. The first input terminal of the AND gate is connected to the qb terminal of SRAM1, the second input terminal is connected to the qb terminal of SRAM2, the third input terminal is connected to the qb terminal of SRAM3, and the output terminal is connected to the second input terminal of the second NOR gate. The output terminal of the second NOR gate serves as the output terminal of the output logic circuit, outputting a reset signal por_n.

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