Semiconductor device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system. The manufacturing method comprises the following steps: providing a first semiconductor layer, an etching stop layer and a first laminated structure which are stacked in sequence, wherein the first laminated structure comprises a first conductive layer and an interlayer insulating layer which are alternately stacked; forming a capacitance hole which penetrates through the first laminated structure and extends into the etching stop layer; sequentially forming a first electrode, a dielectric layer and a second electrode in the capacitor hole to form a capacitor; wherein the first electrode comprises a plurality of sub-electrodes which are arranged at intervals in the stacking direction, and each sub-electrode is connected with the first conductive layer; and removing the first semiconductor layer and the etching stop layer, and removing at least part of the first electrode and the dielectric layer in the etching stop layer to expose at least part of the second electrode in the etching stop layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a memory system. Background Art

[0002] With the continuous improvement of semiconductor manufacturing technology, the process feature size is getting smaller and smaller, and the storage density of memory is getting higher and higher. However, with the improvement of the storage density of memory, the manufacturing process of memory is becoming more and more complicated.

[0003] Therefore, how to optimize the manufacturing process of memory becomes an urgent problem to be solved. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and a memory system.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0007] Providing a first semiconductor layer, an etch stop layer and a first stacked structure stacked in sequence, wherein the first stacked structure comprises first conductive layers and interlayer insulating layers stacked alternately;

[0008] forming a capacitor hole penetrating through the first stacked structure and extending into the etch stop layer;

[0009] A first electrode, a dielectric layer and a second electrode are sequentially formed in the capacitor hole to form a capacitor; wherein the first electrode comprises a plurality of sub-electrodes spaced apart along a stacking direction, and each of the sub-electrodes is connected to the first conductive layer;

[0010] The first semiconductor layer, the etch stop layer, and at least a portion of the first electrode and the dielectric layer located in the etch stop layer are removed to expose at least a portion of the second electrode located in the etch stop layer.

[0011] In some embodiments, two opposite ends of the second electrode arranged along the stacking direction are respectively connected to the first transistor and the second transistor.

[0012] In some embodiments, after sequentially forming a first electrode, a dielectric layer, and a second electrode in the capacitor hole to form a capacitor, the method further includes:

[0013] forming a first transistor connected to the second electrode;

[0014] After removing the first semiconductor layer, the etch stop layer, and removing at least a portion of the first electrode and the dielectric layer in the etch stop layer to expose at least a portion of the second electrode in the etch stop layer, the manufacturing method further includes:

[0015] A second transistor connected to the second electrode is formed; wherein the capacitor, the first transistor and the second transistor together form a first semiconductor structure.

[0016] In some embodiments, forming a first transistor connected to the second electrode includes:

[0017] forming a read transistor connected to the second electrode; wherein a gate of the read transistor is connected to the second electrode;

[0018] The forming of a second transistor connected to the second electrode comprises:

[0019] A write transistor connected to the second electrode is formed; wherein a source or a drain of the write transistor is connected to the second electrode.

[0020] In some embodiments, forming a first transistor connected to the second electrode includes:

[0021] forming a write transistor connected to the second electrode; wherein a source or a drain of the write transistor is connected to the second electrode;

[0022] The forming of a second transistor connected to the second electrode comprises:

[0023] A read transistor connected to the second electrode is formed; wherein a gate of the read transistor is connected to the second electrode.

[0024] In some embodiments, the manufacturing method further comprises:

[0025] Providing a second semiconductor structure, the second semiconductor structure comprising a second semiconductor layer and a peripheral circuit located on the second semiconductor layer;

[0026] After forming the first transistor connected to the second electrode, the manufacturing method further includes:

[0027] The first semiconductor structure and the second semiconductor structure are bonded; wherein the first transistor is located between the capacitor and the peripheral circuit.

[0028] In some embodiments, the manufacturing method further comprises:

[0029] Providing a second semiconductor structure, the second semiconductor structure comprising a second semiconductor layer and a peripheral circuit located on the second semiconductor layer;

[0030] After forming the second transistor connected to the second electrode, the manufacturing method further includes:

[0031] The first semiconductor structure and the second semiconductor structure are bonded; wherein the second transistor is located between the capacitor and the peripheral circuit.

[0032] In some embodiments, forming a read transistor connected to the second electrode includes:

[0033] forming a second stacked structure on the first stacked structure; the second stacked structure comprises a second conductive layer;

[0034] forming a first channel hole penetrating the second stacked structure and extending into the second electrode;

[0035] A first channel layer, a first gate dielectric layer and a first gate layer are formed in the first channel hole; wherein the first channel layer is connected to the second conductive layer, and the first gate layer is connected to the second electrode.

[0036] In some embodiments, two opposite ends of the first channel layer along the stacking direction respectively form the source and drain of the read transistor; wherein the source of the read transistor is connected to the second conductive layer, and the drain of the read transistor is connected to the first bit line.

[0037] In some embodiments, forming a write transistor connected to the second electrode includes:

[0038] forming a third stacked structure on the first stacked structure; the third stacked structure comprising a third conductive layer;

[0039] forming a second channel hole penetrating the third stacked structure and extending into the second electrode;

[0040] A second gate dielectric layer and a second channel layer are formed in the second channel hole; wherein the second channel layer is connected to the second electrode.

[0041] In some embodiments, two ends of the second channel layer opposite to each other along the stacking direction respectively form the source and drain of the write transistor; wherein the source or drain of the write transistor is connected to the second electrode, and the drain or source of the write transistor is connected to the second bit line.

[0042] In some embodiments, the material of the first channel layer includes indium gallium zinc oxide (IGZO); and / or,

[0043] The material of the second channel layer includes IGZO; and / or,

[0044] The material of the dielectric layer includes ferroelectric material.

[0045] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising: a first semiconductor structure, the first semiconductor structure comprising:

[0046] A first stacked structure includes first conductive layers and interlayer insulating layers that are alternately stacked;

[0047] A capacitor running through the first stacked structure, the capacitor comprising a first electrode, a dielectric layer, and a second electrode; wherein the first electrode comprises a plurality of sub-electrodes spaced apart along a stacking direction, each of the sub-electrodes being connected to the first conductive layer; and the second electrode comprises a first end and a second end oppositely disposed along the stacking direction;

[0048] a first transistor connected to the first end of the second electrode;

[0049] A second transistor connected to the second end of the second electrode; wherein the dielectric layer is in contact with the second transistor.

[0050] In some embodiments, the first transistor is a read transistor, and the second transistor is a write transistor; or,

[0051] The first transistor is a write transistor, and the second transistor is a read transistor; wherein a gate of the read transistor is connected to the second electrode, and a source or a drain of the write transistor is connected to the second electrode.

[0052] In some embodiments, the semiconductor device further comprises:

[0053] A second semiconductor structure bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second semiconductor layer and a peripheral circuit located on the second semiconductor layer; wherein the first transistor is located between the capacitor and the peripheral circuit; or, the second transistor is located between the capacitor and the peripheral circuit.

[0054] In some embodiments, the first semiconductor structure further comprises:

[0055] A second stacked structure and a third stacked structure, wherein the second stacked structure and the third stacked structure are respectively located on two opposite sides of the first stacked structure;

[0056] A first transistor located in the second stacked structure; a gate of the first transistor is connected to a second electrode of the capacitor;

[0057] A second transistor is located in the third stacked structure; a source or a drain of the second transistor is connected to the second electrode of the capacitor.

[0058] In some embodiments, the second stacked structure includes a second conductive layer; and the first transistor includes:

[0059] A first channel structure that penetrates the second stacked structure and extends into the second electrode; the first channel structure includes a first channel layer, a first gate dielectric layer and a first gate layer; the first channel layer surrounds the first gate dielectric layer, and the first gate dielectric layer surrounds the first gate layer; wherein two ends of the first channel layer that are relatively arranged along the stacking direction respectively form the source and drain of the first transistor; the source of the first transistor is connected to the second conductive layer, and the drain of the first transistor is connected to the first bit line; the first gate layer is connected to the second electrode.

[0060] In some embodiments, the third stacked structure includes a third conductive layer; and the second transistor includes:

[0061] A second channel structure that penetrates the third stacked structure and extends into the second electrode; the second channel structure includes a second gate dielectric layer and a second channel layer; the second gate dielectric layer surrounds the second channel layer; the third conductive layer surrounds the second gate dielectric layer; wherein two ends of the second channel layer that are oppositely arranged along the stacking direction respectively form the source and drain of the second transistor; the source or drain of the second transistor is connected to the second electrode, and the drain or source of the second transistor is connected to the second bit line.

[0062] In some embodiments, the first semiconductor structure further comprises:

[0063] A second stacked structure and a third stacked structure, wherein the second stacked structure and the third stacked structure are respectively located on two opposite sides of the first stacked structure;

[0064] a second transistor located in the second stacked structure; a gate of the second transistor being connected to a second electrode of the capacitor;

[0065] A first transistor is located in the third stacked structure; a source or a drain of the first transistor is connected to the second electrode of the capacitor.

[0066] In some embodiments, the material of the first channel layer includes IGZO; and / or,

[0067] The material of the second channel layer includes IGZO; and / or,

[0068] The material of the dielectric layer includes ferroelectric material.

[0069] In a third aspect, an embodiment of the present disclosure provides a memory system, the memory system comprising:

[0070] The semiconductor device as described in the above technical solution; and

[0071] A controller is coupled to the semiconductor device, the controller being configured to control the semiconductor device.

[0072] The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof, and a memory system. The manufacturing method includes: providing a first semiconductor layer, an etch stop layer, and a first stacked structure stacked in sequence, wherein the first stacked structure includes a first conductive layer and an interlayer insulating layer stacked alternately; forming a capacitor hole that penetrates the first stacked structure and extends into the etch stop layer; forming a first electrode, a dielectric layer, and a second electrode in the capacitor hole in sequence to form a capacitor; wherein the first electrode includes a plurality of sub-electrodes spaced apart in the stacking direction, and each of the sub-electrodes is connected to the first conductive layer; removing the first semiconductor layer, the etch stop layer, and removing at least part of the first electrode and the dielectric layer located in the etch stop layer to expose at least part of the second electrode located in the etch stop layer. In the embodiment of the present disclosure, etching forms a capacitor hole that penetrates the first stacked structure and extends into the etch stop layer, and sequentially forms a first electrode, a dielectric layer, and a second electrode in the capacitor hole, and by removing the etch stop layer, both ends of the second electrode of the capacitor that are arranged oppositely in the stacking direction are exposed, so that the first transistor and the second transistor can be formed later and connected to the two ends of the second electrode that are arranged oppositely in the stacking direction. Compared to the process of forming the transistor first and then the capacitor, it is necessary to remove the dielectric material layer covering the bottom of the capacitor hole through the capacitor hole. In the embodiment of the present disclosure, the etch stop layer is removed to expose the dielectric layer covering the bottom of the capacitor hole and at least part of the dielectric layer can be removed. In this way, the manufacturing difficulty of the semiconductor device can be reduced, which is beneficial to increase the number of stacking layers of the first stacking structure and improve the integration of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device provided as an example;

[0074] Figure 2 A schematic diagram of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0075] FIG. 3A to FIG. 3E A schematic diagram of a cross-sectional structure of a semiconductor device during a manufacturing process provided by an embodiment of the present disclosure;

[0076] Figure 4A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present disclosure;

[0077] Figure 5 A block diagram of a memory system provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0078] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0079] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0080] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0081] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0082] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0083] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0084] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0085] refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device provided as an example. Figure 1 As shown, the semiconductor device 100 includes a first transistor 101, a capacitor 102 and a second transistor 103 which are stacked in sequence, the capacitor 102 includes a first electrode 104, a dielectric layer 105 and a second electrode 106, the source 107 or the drain 108 of the first transistor (i.e., the write transistor) is connected to the second electrode 106 of the capacitor 102, and the gate 109 of the second transistor (i.e., the read transistor) is connected to the second electrode 106 of the capacitor 102.

[0086] Exemplarily, the process of forming the above-mentioned semiconductor device may include the following steps: forming a first transistor 101 on a substrate 110, the first transistor 101 may, for example, include a semiconductor column 111 extending in a direction perpendicular to the substrate 110, the semiconductor column 111 including a source 107, a drain 108 and a channel region 112 located between the source 107 and the drain 108 along the extending direction. Forming a stacked structure 113 on the first transistor 101, the stacked structure 113 including conductive layers 114 and insulating layers 115 alternately stacked; etching to form a conductive layer 114 that penetrates the stacked structure 113 and exposes the source 107 or the drain 108 of the first transistor (for example, Figure 1 107 of the first transistor is schematically shown in the figure; a dielectric material layer covering the bottom and sidewall of the capacitor hole 116 is formed; the dielectric material covering the bottom of the capacitor is removed to form a dielectric layer 105; a conductive material is filled in the capacitor hole 116 to form a second electrode 106; wherein the capacitor 102 includes a first electrode 104, a dielectric layer 105 and a second electrode 106, the second electrode 106 has two opposite ends arranged in a direction perpendicular to the substrate 110, the source 107 of the first transistor is connected to one end of the second electrode 106; each conductive layer 114 forms a sub-electrode 117, and a plurality of sub-electrodes 117 together form the first electrode 104 of the capacitor 102. A second transistor 103 is formed on the capacitor 102, and the gate 109 of the second transistor is connected to the other end of the second electrode 106.

[0087] In addition, before forming the stacked structure 113 on the first transistor 101 , a contact plug 118 may be formed on the source 107 of the first transistor, so that a capacitor hole 116 penetrating the stacked structure 113 and exposing the contact plug 118 may be formed by etching.

[0088] It should be noted that after etching to form the capacitor hole, it is necessary to remove the dielectric material layer covering the bottom of the capacitor hole through the capacitor hole so that the second electrode is connected to the source of the first transistor. In this way, in the process of removing the dielectric material layer covering the bottom of the capacitor hole, it is necessary to perform deep hole etching on the dielectric material layer covering the bottom of the capacitor hole through the capacitor hole in a direction perpendicular to the substrate. As the number of stacked layers of the stacked structure increases, it becomes increasingly difficult to remove the dielectric material layer covering the bottom of the capacitor hole through the capacitor hole, which is not conducive to increasing the number of stacked layers of the stacked structure and improving the integration of the capacitor.

[0089] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and a memory system.

[0090] refer to Figure 2 , Figure 2 The flowchart of the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure is as follows. Figure 2As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0091] Step S201: providing a first semiconductor layer, an etch stop layer and a first stacked structure stacked in sequence, wherein the first stacked structure comprises first conductive layers and interlayer insulating layers stacked alternately;

[0092] Step S202: forming a capacitor hole penetrating the first stacked structure and extending into the etch stop layer;

[0093] Step S203: forming a first electrode, a dielectric layer and a second electrode in the capacitor hole in sequence to form a capacitor; wherein the first electrode comprises a plurality of sub-electrodes spaced apart along the stacking direction, and each sub-electrode is connected to the first conductive layer;

[0094] Step S204: removing the first semiconductor layer, the etch stop layer, and removing at least a portion of the first electrode and the dielectric layer located in the etch stop layer to expose at least a portion of the second electrode located in the etch stop layer.

[0095] In the embodiment of the present disclosure, two opposite ends of the second electrode arranged along the stacking direction are respectively connected to the first transistor and the second transistor.

[0096] In the disclosed embodiment, etching forms a capacitor hole that penetrates the first stacked structure and extends to the etch stop layer, and a first electrode, a dielectric layer, and a second electrode are sequentially formed in the capacitor hole. The etch stop layer is removed so that both ends of the second electrode of the capacitor that are relatively arranged along the stacking direction are exposed, so that the first transistor and the second transistor can be subsequently formed and connected to the two ends of the second electrode that are relatively arranged along the stacking direction. Compared with the process of forming the transistor first and then the capacitor, it is necessary to remove the dielectric material layer covering the bottom of the capacitor hole through the capacitor hole. In the disclosed embodiment, the etch stop layer is removed to expose the dielectric layer covering the bottom of the capacitor hole and at least part of the dielectric layer can be removed. In this way, the manufacturing difficulty of the semiconductor device can be reduced, which is conducive to increasing the number of stacked layers of the first stacked structure and improving the integration of the capacitor.

[0097] In the disclosed embodiment, no deep hole etching process is required, which can further simplify the process and reduce the manufacturing cost. Moreover, because no deep hole etching process is required, the number of stacked layers of the first stacked structure can be increased, thereby improving the integration of the capacitor.

[0098] Before introducing the semiconductor device and the manufacturing method thereof provided by the embodiment of the present disclosure, various directions that may be involved in the embodiment of the present disclosure are first defined. The direction perpendicular to the first semiconductor layer is defined as the Z direction, and the X direction and the Y direction are defined in the plane perpendicular to the Z direction, and the X direction and the Y direction may intersect. In a specific embodiment, the X direction and the Y direction may be perpendicular to each other, so that the X direction, the Y direction and the Z direction are perpendicular to each other.

[0099] refer to FIG. 3A to FIG. 3E , FIG. 3A to FIG. 3E The cross-sectional structure diagram of the semiconductor device provided in the embodiment of the present disclosure during the manufacturing process. FIG. 3A to FIG. 3E The manufacturing process of the semiconductor device provided by the embodiment of the present disclosure is described in detail.

[0100] refer to Figure 3A In step S201, a first semiconductor layer 300 is provided, an etch stop layer 301 is formed on the first semiconductor layer 300, and a first stacked structure 302 is formed on the etch stop layer 301, wherein the first stacked structure 302 includes alternately stacked first conductive layers 303 and interlayer insulating layers 304. Of course, the first stacked structure 302 may also include a sacrificial layer 362, and the sacrificial layer 362 is located on a side away from the first semiconductor layer 300.

[0101] In the embodiment of the present disclosure, the first semiconductor layer can be a substrate, specifically including at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material or other semiconductor materials known in the art.

[0102] The disclosed embodiment has no particular limitation on the number and thickness of the first conductive layer and the interlayer insulating layer included in the first stacked structure, and can be flexibly selected according to actual conditions. In a specific embodiment, the material of the first conductive layer may include but is not limited to metal materials, and the material of the interlayer insulating layer may include but is not limited to oxides.

[0103] In the embodiments of the present disclosure, the formation of the etch stop layer, the first conductive layer and the interlayer insulating layer may be achieved by one or more deposition processes, wherein the deposition process may include but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or any combination thereof.

[0104] refer to Figure 3A In step S202, a capacitor hole 305 is formed by etching along the Z direction, which penetrates the first stacked structure 302 and extends to the etch stop layer 301. The sidewalls of the capacitor hole 305 simultaneously expose the sidewalls of the first conductive layer 303 and the interlayer insulating layer 304 of the first stacked structure 302, and the bottom of the capacitor hole 305 exposes the etch stop layer 301. At this time, along the Z direction, the aperture of the capacitor hole 305 at the first conductive layer 303 and the aperture of the capacitor hole 305 at the interlayer insulating layer 304 are the same, that is, the sidewalls of the capacitor hole 305 are flat.

[0105] Exemplarily, the process of etching to form a capacitor hole may further include the following steps: etching along the Z direction to form a capacitor hole 305 that penetrates the first stacked structure 302 and extends to the etching stop layer 301; etching a portion of the first conductive layer 303 along a direction parallel to the first semiconductor layer (for example, the X direction or the Y direction), so that the aperture of the capacitor hole 305 located at the first conductive layer 303 is larger than the aperture of the capacitor hole 305 located at the interlayer insulating layer 304. In addition, the aperture of the capacitor hole 305 located at the sacrificial layer 362 is larger than the aperture of the capacitor hole 305 located at the interlayer insulating layer 304.

[0106] refer to Figure 3A In step S203, a first electrode 306, a dielectric layer 307, and a second electrode 308 are sequentially formed in the capacitor hole 305 to form a capacitor 309; wherein the first electrode 306 includes a plurality of sub-electrodes 310 spaced apart along the stacking direction, and each sub-electrode 310 is connected to the first conductive layer 303. In addition, a dummy sub-electrode is formed in the capacitor hole 305 at a position corresponding to the sacrificial layer 362, and the dummy sub-electrode is connected to the sacrificial layer 362.

[0107] Exemplarily, forming a capacitor may include the following steps: forming a first electrode 306 covering the bottom and side walls of the capacitor hole 305, the first electrode 306 including a plurality of sub-electrodes 310 spaced apart along the stacking direction, each sub-electrode 310 being connected to the first conductive layer 303; at this time, the side walls of the capacitor hole 305 simultaneously expose the first electrode 306 and the interlayer insulating layer 304, that is, the aperture of the capacitor hole 305 at the first conductive layer 303 (or, the sub-electrode 310) is the same as the aperture of the capacitor hole 305 at the interlayer insulating layer 304; forming a dielectric layer 307 covering the bottom and side walls of the capacitor hole 305; and filling the capacitor hole 305 with a conductive material to form a second electrode 308.

[0108] Exemplarily, the process of forming the second electrode may include the following steps: filling the capacitor hole with a conductive material, wherein the conductive material layer may fill the capacitor hole and cover the surface of the first stacked structure; planarizing the conductive material layer to expose the surface of the first stacked structure, and the conductive material layer located in the capacitor hole forms the second electrode.

[0109] In some embodiments, the second electrode 308 of the capacitor 309 may be a single layer of conductive material. In other embodiments, the second electrode 308 of the capacitor 309 may be a composite conductive material layer. Figure 3A As shown in the dotted box, the second electrode 308 includes a titanium nitride layer 311 covering the bottom and sidewalls of the capacitor hole 305 and a tungsten layer 312 filling the capacitor hole 305 ; wherein the titanium nitride layer 311 is in contact with the dielectric layer 307 covering the bottom and sidewalls of the capacitor hole 305 .

[0110] In some embodiments, materials of the first conductive layer, the first electrode, and the second electrode are all conductive materials; and materials of the dielectric layer may include insulating materials.

[0111] For ease of explanation, Figure 3A Only two first conductive layers 303 are shown, and the sub-electrodes 310 of the first electrode 306 may be formed at positions corresponding to the first conductive layers 303. In some embodiments, the material of the first conductive layer 303 may be the same as or different from the material of the sub-electrodes 310. The sub-electrodes 310 of the first electrode 306 of the capacitor 309 may be electrically connected to the first conductive layer 303, and the sub-electrodes 310 may be controlled by an electrical signal applied to the first conductive layer 303.

[0112] In a specific embodiment, the material of the dielectric layer may include a ferroelectric material, and the capacitor may be a ferroelectric capacitor.

[0113] like Figure 3A As shown, the second electrode 308 of the capacitor 309 has two ends arranged opposite to each other along the stacking direction, namely, a first end 313 and a second end 314 (as shown in FIG. Figure 3A At this time, the first end 313 of the second electrode 308 is substantially flush with the surface of the first stacked structure 302, that is, the first end 313 of the second electrode 308 is exposed, and the second end 314 of the second electrode 308 is located in the etching stop layer 301, that is, the second end 314 of the second electrode 308 is not exposed.

[0114] In the embodiment of the present disclosure, after step S203, the following steps are further included:

[0115] A first transistor 315 connected to the second electrode 308 is formed.

[0116] In the embodiment of the present disclosure, a first transistor 315 connected to the second electrode 308 is formed, including:

[0117] A read transistor 316 connected to the second electrode 308 is formed; wherein a gate of the read transistor 316 is connected to the second electrode 308 .

[0118] like Figure 3B As shown, a first transistor 315 connected to the first end 313 of the second electrode 308 may be formed. The first transistor 315 may be, for example, a read transistor 316, and a gate of the read transistor (eg, the first gate layer 323) is connected to the first end 313 of the second electrode 308.

[0119] like Figure 3B As shown, in the embodiment of the present disclosure, a read transistor 316 connected to the second electrode 308 is formed, including:

[0120] A second stacked structure 318 is formed on the first stacked structure 302; the second stacked structure 318 includes a second conductive layer 319;

[0121] forming a first channel hole 320 penetrating the second stacked structure 318 and extending into the second electrode 308;

[0122] A first channel layer 321 , a first gate dielectric layer 322 and a first gate layer 323 are formed in the first channel hole 320 ; wherein the first channel layer 321 is connected to the second conductive layer 319 , and the first gate layer 323 is connected to the second electrode 308 .

[0123] Exemplarily, forming the read transistor 316 may include the following steps: forming a second stacked structure 318 on the first stacked structure 302, wherein the second stacked structure 318 includes a first insulating layer 324, a second conductive layer 319, a second insulating layer 325, and a first isolation layer 326 stacked in sequence, and the first insulating layer 324 contacts the first end 313 of the second electrode 308. Etching is performed along the Z direction to form a first sub-channel hole 327 (such as Figure 3B The first channel material layer covering the bottom and sidewalls of the first sub-channel hole 327 is formed; the first channel material layer covering the bottom of the first sub-channel hole 327 is removed to form a first channel layer 321; wherein the first channel layer 321 only covers the sidewalls of the first sub-channel hole 327. Through the first sub-channel hole 327, a second sub-channel hole 328 (as shown in the Z direction) is formed by etching through the first insulating layer 324 and extending to the second electrode 308. Figure 3BThe first sub-channel hole 327 and the second sub-channel hole 328 are connected, and the first sub-channel hole 327 and the second sub-channel hole 328 together form the first channel hole 320. A first gate dielectric material layer covering the bottom and sidewalls of the first channel hole 320 is formed; the first gate dielectric material layer covering the bottom of the first channel hole is removed to form a first gate dielectric layer 322; wherein the first gate dielectric layer 322 only covers the sidewalls of the first channel hole 320. A conductive material is filled in the first channel hole 320 to form a first gate layer 323; wherein the first gate layer 323 may include a covering composite gate layer, for example, the first gate layer 323 may include a first gate sublayer 329 covering the bottom and sidewalls of the first channel hole 320 and a second gate sublayer 330 filling the first channel hole 320.

[0124] In some embodiments, the materials of the first insulating layer, the second insulating layer and the first isolation layer may include, but are not limited to, insulating materials, such as oxides. In some embodiments, the material of the second conductive layer may include conductive materials.

[0125] In some embodiments, the deposition process for forming the first insulating layer, the second insulating layer, the first isolation layer, and the second conductive layer may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0126] In a specific embodiment, the first gate layer may include a composite gate layer, for example, the first gate layer may include a first gate sublayer covering the bottom and sidewalls of the first channel hole and a second gate sublayer filling the first channel hole. The material of the first gate sublayer may include titanium nitride, and the material of the second gate sublayer may include tungsten.

[0127] In the present disclosure, Figure 3B As shown in the dotted box, two opposite ends of the first channel layer 321 along the stacking direction (ie, the Z direction) respectively form the source 335 of the read transistor (eg, Figure 3B The dotted circle in the middle) and the drain 336 of the read transistor (as shown in Figure 3B The source 335 of the read transistor is connected to the second conductive layer 319, and the drain 336 of the read transistor is connected to the first bit line 332. For the convenience of illustrating the source 335 and the drain 336 of the read transistor, Figure 3B The dotted box in FIG. 3 only illustrates the first channel layer 321 and the first bit line 332 in the first channel hole 320 , and does not illustrate other structures in the first channel hole 320 .

[0128] Exemplarily, part of the first gate dielectric layer 322 and part of the first gate layer 323 may be removed so that the remaining surfaces of the first gate dielectric layer 322 and the first gate layer 323 are lower than the surface of the first channel layer 321. In other words, part of the first gate dielectric layer 322 and part of the first gate layer 323 are removed so that the remaining surfaces of the first gate dielectric layer 322 and the first gate layer 323 are substantially flush with the surface of the second insulating layer 325. A third insulating layer 331 and a first bit line 332 are formed in the first channel hole 320, and the surface of the first bit line 332 is substantially flush with the surface of the first channel layer 321.

[0129] Exemplarily, a first contact hole 333 can be formed by etching through the first isolation layer 326 and the second insulating layer 325 and extending to the second conductive layer 319; wherein the second conductive layer 319 can form a source line of the first transistor 315; a conductive material is filled in the first contact hole 333 to form a first contact structure 334, and the first contact structure 334 is used to lead out an electrical signal of the source line. Of course, the first contact structure 334 can be a composite structure, for example, the first contact structure 334 can include a titanium nitride layer covering the bottom and sidewalls of the first contact hole 333 and a tungsten layer filling the first contact hole.

[0130] In some embodiments, the material of the third insulating layer may include an insulating material.

[0131] Figure 3B It is shown that the second conductive layer 319 surrounds the first channel layer 321, and the portion of the first channel layer 321 contacting the second conductive layer 319 forms the source 335 of the read transistor; Figure 3B It is also shown that the first channel layer 321 surrounds the first bit line 332 , and a portion of the first channel layer 321 in contact with the first bit line 332 forms a drain 336 of the read transistor. Figure 3B It is shown that the first channel layer 321 surrounds the first gate layer 323 , and the read transistor 316 is a Channel-All-Around (CAA) transistor.

[0132] In the embodiment of the present disclosure, the manufacturing method further includes:

[0133] Providing a second semiconductor structure 337, the second semiconductor structure 337 comprising a second semiconductor layer 338 and a peripheral circuit 339 located on the second semiconductor layer 338;

[0134] After forming the first transistor 315 connected to the second electrode 308, the manufacturing method further includes:

[0135] The first semiconductor structure 341 and the second semiconductor structure 337 are bonded; wherein the first transistor 315 is located between the capacitor 309 and the peripheral circuit 339 .

[0136] like Figure 3C As shown, a second semiconductor structure 337 is provided, and the second semiconductor structure 337 includes a second semiconductor layer 338 and a peripheral circuit 339 located on the second semiconductor layer 338; after forming the first transistor 315 (i.e., the read transistor 316), the second semiconductor structure 337 is bonded to the second stacked structure 318. At this time, the peripheral circuit 339 of the second semiconductor structure 337 is located on the front side of the first semiconductor layer 300, that is, the read transistor 316 is located between the capacitor 309 and the peripheral circuit 339.

[0137] Combination Figure 3C and Figure 3D In step S204 , the first semiconductor layer 300 , the etch stop layer 301 , and at least a portion of the first electrode 306 and the dielectric layer 307 located in the etch stop layer 301 are removed to expose at least a portion of the second electrode 308 located in the etch stop layer 301 .

[0138] In the disclosed embodiment, part of the first electrode and part of the dielectric layer in the etch stop layer can be removed along the Z direction to expose the second end of part of the second electrode. All of the first electrode and all of the dielectric layer in the etch stop layer can also be removed along the Z direction to expose the second end of the second electrode. It should be noted that the purpose of exposing the second end of the second electrode is to enable the second transistor formed in the subsequent process to be electrically connected to the second end of the second electrode. Therefore, part of the first electrode and part of the dielectric layer in the etch stop layer can be removed so that the second transistor formed in the subsequent process is in contact with the dielectric layer, and all of the first electrode and all of the dielectric layer in the etch stop layer can be removed so that the second transistor formed in the subsequent process is not in contact with the dielectric layer. Figure 3D It is schematically shown that all the first electrodes 306 and all the dielectric layers 307 in the etch stop layer 301 are removed, which does not constitute a limitation on the protection scope of the present disclosure.

[0139] In the embodiment of the present disclosure, after step S204 , a second transistor 340 connected to the second electrode 308 is formed; wherein the capacitor 309 , the first transistor 315 and the second transistor 340 together form a first semiconductor structure 341 .

[0140] The semiconductor device provided by the embodiment of the present disclosure includes a first transistor, a second transistor and a capacitor, forming a structure of two transistors and one capacitor (2T1C). In the embodiment of the present disclosure, a capacitor hole can be etched to penetrate the first stacked structure and extend to the etch stop layer, and a first electrode, a dielectric layer and a second electrode are sequentially formed in the capacitor hole, and the second electrode of the capacitor is exposed at both ends relatively arranged along the stacking direction by removing the etch stop layer. Therefore, the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure is conducive to increasing the number of stacked layers of the first stacked structure and improving the integration of the capacitor. In the embodiment of the present disclosure, it is possible to support the formation of capacitors with more stacked layers, that is, the first electrode forming the capacitor includes a larger number of sub-electrodes. In other words, the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure can form a structure of two transistors and X capacitors (2TXC). Wherein, the value of X can be flexibly selected according to actual conditions.

[0141] In the embodiment of the present disclosure, a second transistor 340 connected to the second electrode 308 is formed, including:

[0142] A write transistor 342 connected to the second electrode 308 is formed; wherein a source 352 or a drain 351 of the write transistor 342 is connected to the second electrode.

[0143] like Figure 3E As shown, a second transistor 340 connected to the second end 314 of the second electrode 308 may be formed. The second transistor 340 may be, for example, a write transistor 342, and a source 352 (eg, Figure 3E The dotted circle shown in the middle) or the drain 351 of the write transistor (as shown in the middle Figure 3E The second end 314 of the second electrode 308 is connected to the second end 314 of the second electrode 308. Figure 3E It is shown that the source 352 of the write transistor is connected to the second end 314 of the second electrode 308 .

[0144] like Figure 3E As shown, in the embodiment of the present disclosure, after step S204, a write transistor 342 connected to the second electrode 308 is formed, including:

[0145] A third stacked structure 343 is formed on the first stacked structure 302; the third stacked structure 343 includes a third conductive layer 344;

[0146] forming a second channel hole 345 penetrating through the third stacked structure 343 and extending into the second electrode 308;

[0147] A second gate dielectric layer 346 and a second channel layer 347 are formed in the second channel hole 345 ; wherein the second channel layer 347 is connected to the second electrode 308 .

[0148] Exemplarily, forming the write transistor 342 may include the following steps: forming a third stacked structure 343 on the first stacked structure 302, wherein the third stacked structure 343 includes a fourth insulating layer 348, a third conductive layer 344 and a fifth insulating layer 349 stacked in sequence, and the fourth insulating layer 348 is in contact with the first stacked structure 302. Etching along the Z direction to form a second channel hole 345 penetrating the third stacked structure 343 and extending to the second end 314 of the second electrode 308; forming a second gate dielectric material layer covering the bottom and sidewalls of the second channel hole 345; removing the second gate dielectric material layer covering the bottom of the second channel hole, retaining the second gate dielectric material layer covering the sidewalls of the second channel hole to form a second gate dielectric layer 346; and forming a second channel layer 347 and a filling layer 350 in the second channel hole.

[0149] In the embodiment of the present disclosure, the two ends of the second channel layer 346 that are relatively arranged along the stacking direction (i.e., the Z direction) respectively form the source 352 and the drain 351 of the write transistor; wherein the source 352 or the drain 351 of the write transistor is connected to the second electrode 308, and the drain 351 or the source 352 of the write transistor is connected to the second bit line.

[0150] Exemplarily, forming the second channel layer 347 may include the following steps: forming a second channel material layer covering the bottom and sidewalls of the second channel hole 345, wherein the second channel material layer is in contact with the second gate dielectric layer 346; filling the second channel hole with an insulating material to form a filling material layer; etching and removing a portion of the filling material layer to form a filling layer 350; wherein the surface of the filling layer 350 is lower than the surface of the fifth insulating layer 349; and continuing to fill the second channel material in the second channel hole 345 to form the second channel layer 347. At this time, the second channel layer 347 surrounds the filling layer 350, and the second channel layer 347 covers two opposite ends of the filling layer 350 arranged along the Z direction.

[0151] Figure 3E It is shown that the third conductive layer 344 surrounds the second gate dielectric layer 346, and the second gate dielectric layer 346 surrounds the second channel layer 347; wherein the third conductive layer 344 can form the gate 358 of the write transistor. That is, Figure 3E It is shown that the gate 358 of the write transistor surrounds the second channel layer 347 , and the write transistor 342 is a gate-all-around (GAA) transistor. Figure 3E It is also shown that the second channel layer 347 has two opposite ends along the direction, and a portion of the second channel layer 347 extending into the second electrode 308 can form a source 352 of the write transistor.

[0152] Exemplarily, a sixth insulating layer 353 may be formed on the third stacked structure 343, and the sixth insulating layer 353 is in contact with the fifth insulating layer 349; a second contact hole 354 is formed by etching along the Z direction to penetrate the sixth insulating layer 353 and expose the surface of the second channel layer 347, and a third contact hole 355 is formed by etching along the Z direction to penetrate the sixth insulating layer 353 and the fifth insulating layer 349 and extend to the third conductive layer 344; a conductive material is filled in the second contact hole 354 and the third contact hole 355 to form a second contact structure 356 and a third contact structure 357, wherein the second contact structure 356 is electrically connected to the drain 351 of the write transistor, and the second contact structure 356 can be used to lead out the electrical signal of the second bit line. The third contact structure 357 is electrically connected to the gate 358 of the write transistor, and the third contact structure 357 can be used to lead out the electrical signal of the word line of the write transistor 342.

[0153] In some embodiments, materials of the first gate dielectric layer and the second gate dielectric layer may include insulating materials, such as oxide.

[0154] In some embodiments, the material of the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may include, but is not limited to, an insulating material, such as an oxide. In some embodiments, the material of the third conductive layer may include a conductive material.

[0155] In some embodiments, the deposition process for forming the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the third conductive layer may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0156] In the embodiment of the present disclosure, the material of the first channel layer 321 and the second channel layer 347 may include indium gallium zinc oxide (IGZO).

[0157] Compared with the ferroelectric random access memory (FerroelectricRAM, FeRAM) of 1T1C or multi-C architecture in the related technical solutions, the ferroelectric effect of ferroelectric materials is used to realize data storage. Specifically, a certain electric field is applied to the ferroelectric crystal, and the central atom of the crystal moves under the action of the electric field and reaches a stable state; when the electric field is removed, the central atom of the crystal will still remain in its original position, so that the ferroelectric memory has non-volatile storage characteristics. In other words, the ferroelectric memory realizes the data storage function not through the charge stored on the capacitor, but through the central atom position of the ferroelectric crystal in the capacitor. The reading operation process is as follows: a certain electric field is applied to the capacitor. If the original position of the central atom of the crystal and the direction of the applied electric field make the central atom of the crystal the same as the position to be reached by the central atom of the crystal, then the central atom of the crystal will not move; if the opposite is true, then the central atom of the crystal will move. According to whether the central atom of the crystal moves, it can be judged whether the capacitor stores "1" or "0". During the reading operation, the position of the central atom of the crystal may move. In short, the reading operation is destructive, and a write-back operation is required after the reading operation.

[0158] In the disclosed embodiment, the source of the write transistor is connected to the second electrode of the capacitor, and the gate of the read transistor is connected to the second electrode of the capacitor; wherein the connection node between the source of the write transistor, the gate of the read transistor and the second electrode of the capacitor forms a floating node. During the write operation, a write voltage Vw is applied to the gate of the write transistor, so that the write transistor is turned on. At this time, the voltage at the floating node is the write voltage Vw, so that it is in a certain storage state, thereby completing the write operation; during the read operation, the write transistor is turned off, and the input voltage Vin is applied to the first electrode of the capacitor, so that the voltage at the floating node is (Vin+Vw), and the output voltage Vout is applied to the source of the read transistor. An output current is generated in the read transistor, and the magnitude of the output current will be affected by the voltage at the floating node. In other words, when the input voltage Vin remains unchanged, the write voltage Vw determines the output current. Therefore, the storage state can be determined based on the output current value.

[0159] The read operation in the semiconductor device provided by the present disclosure is non-destructive, and data is read by reading the output current value. However, in this read operation, the write transistor needs to be completely turned off, that is, this read operation has a high requirement on the leakage of the write transistor.

[0160] Here, IGZO has a lower leakage than monocrystalline silicon and polycrystalline silicon due to its wide bandgap, and the write transistor can be completely turned off during the read operation. And IGZO is used as the material of the first channel layer and the second channel layer, so that the formation of the read transistor and the write transistor does not include a high-temperature processing process, that is, IGZO is a full low-temperature process. In this way, even if the capacitor is formed first and then the read transistor and the write transistor are formed, the process of forming the read transistor or the write transistor will not cause damage to the capacitor, so that the selection range of ferroelectric materials for forming the dielectric layer is wider.

[0161] FIG. 3A to FIG. 3E Only an optional embodiment of a method for manufacturing a semiconductor device is illustrated, and the manufacturing method includes the following steps: forming a capacitor 309; performing a front process to form a first transistor 315 (for example, a read transistor 316) connected to the second electrode 308 of the capacitor 309; front bonding a second semiconductor structure 337; performing a back process to form a second transistor 340 (for example, a write transistor 342) connected to the second electrode 308 of the capacitor 309.

[0162] It should be noted that the front process can be used to form the read transistor and the back process can be used to form the write transistor, or the front process can be used to form the write transistor and the back process can be used to form the read transistor. That is, the first transistor can be a read transistor or a write transistor, and correspondingly, the second transistor can be a write transistor or a read transistor. The process of forming the read transistor and the write transistor can refer to FIG. 3A to FIG. 3E The relevant description will not be repeated here.

[0163] In an embodiment of the present disclosure, forming a first transistor connected to a second electrode includes:

[0164] forming a write transistor connected to the second electrode; wherein a source or a drain of the write transistor is connected to the second electrode;

[0165] Forming a second transistor connected to the second electrode, comprising:

[0166] A read transistor connected to the second electrode is formed; wherein a gate of the read transistor is connected to the second electrode.

[0167] It should be noted that the second semiconductor structure can be bonded on the front side or on the back side. That is, the first transistor can be located between the capacitor and the peripheral circuit, or the second transistor can be located between the capacitor and the peripheral circuit. The process of bonding the first semiconductor structure and the second semiconductor structure can refer to FIG. 3A to FIG. 3E The relevant description will not be repeated here.

[0168] In the embodiment of the present disclosure, the manufacturing method further includes:

[0169] Providing a second semiconductor structure, the second semiconductor structure comprising a second semiconductor layer and a peripheral circuit located on the second semiconductor layer;

[0170] After forming the second transistor connected to the second electrode, the manufacturing method further includes:

[0171] The first semiconductor structure and the second semiconductor structure are bonded; wherein the second transistor is located between the capacitor and the peripheral circuit.

[0172] In some embodiments, a capacitor is formed; a front process is performed to form a first transistor (e.g., a write transistor) connected to a second electrode of the capacitor; a second semiconductor structure is bonded to the front side; and a back process is performed to form a second transistor (e.g., a read transistor) connected to the second electrode of the capacitor.

[0173] In some embodiments, a capacitor is formed; a front process is performed to form a first transistor (e.g., a read transistor) connected to a second electrode of the capacitor; a back process is performed to form a second transistor (e.g., a write transistor) connected to the second electrode of the capacitor; and a second semiconductor structure is back-bonded.

[0174] In some embodiments, a capacitor is formed; a front process is performed to form a first transistor (e.g., a write transistor) connected to a second electrode of the capacitor; a back process is performed to form a second transistor (e.g., a read transistor) connected to the second electrode of the capacitor; and a second semiconductor structure is back-bonded.

[0175] refer to Figure 4 , Figure 4 The cross-sectional structure diagram of a semiconductor device provided by an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the embodiment of the present disclosure provides a semiconductor device 359, the semiconductor device 359 includes: a first semiconductor structure 341, the first semiconductor structure 341 includes:

[0176] The first stacked structure 302 includes first conductive layers 303 and interlayer insulating layers 304 that are alternately stacked;

[0177] The capacitor 309 that runs through the first stacked structure includes a first electrode 306, a dielectric layer 307, and a second electrode 308; wherein the first electrode 306 includes a plurality of sub-electrodes 310 that are spaced apart along the stacking direction (i.e., the Z direction), and each sub-electrode 310 is connected to the first conductive layer 303; the second electrode 308 has a first end 313 and a second end 314 that are oppositely disposed along the stacking direction (i.e., the Z direction). Figure 4 The dotted box shows the middle part);

[0178] A first transistor 315 connected to a first terminal 313 of the second electrode 308;

[0179] A second transistor 340 is connected to the second end 314 of the second electrode 308 ; wherein the dielectric layer 307 is in contact with the second transistor 340 .

[0180] In the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure, a back side process is performed to remove part of the first electrode and part of the dielectric layer located in the etch stop layer, so that the second transistor formed in the subsequent process is in contact with the dielectric layer. Alternatively, all of the first electrode and all of the dielectric layer located in the etch stop layer are removed, so that the second transistor formed in the subsequent process is not in contact with the dielectric layer.

[0181] Correspondingly, in the semiconductor device provided by the embodiment of the present disclosure, after removing part of the first electrode and part of the dielectric layer located in the etch stop layer, part of the second electrode protruding from the surface of the first stacked structure can be in contact with the dielectric layer, so that the second transistor formed subsequently can be in contact with the dielectric layer; after removing all of the first electrodes and all of the dielectric layers located in the etch stop layer, part of the second electrode protruding from the surface of the first stacked structure may not be in contact with the dielectric layer, so that the second transistor formed subsequently does not contact with the dielectric layer. Figure 4 It is illustrated that part of the second electrode protruding from the surface of the first stacked structure may not be in contact with the dielectric layer, and the second transistor does not contact with the dielectric layer, which does not constitute a limitation on the protection scope of the present disclosure.

[0182] In some embodiments, the first transistor 315 may be a read transistor 316 and the second transistor 340 may be a write transistor 342; or,

[0183] The first transistor 315 is a write transistor, and the second transistor 340 is a read transistor; wherein the gate of the read transistor (ie, the first gate layer 323 ) is connected to the second electrode 308 , and the source 352 of the write transistor or the drain 351 of the write transistor is connected to the second electrode 308 .

[0184] For ease of explanation, Figure 4 Only the first transistor 315 is schematically shown as a read transistor 316, and the second transistor 340 is a write transistor 342; wherein the source 352 of the write transistor is connected to the second electrode 308 (eg Figure 4 shown in the dashed box). Figure 4 The case where the first transistor is a write transistor and the second transistor is a read transistor is not illustrated.

[0185] In the embodiment of the present disclosure, the semiconductor device 359 further includes:

[0186] The second semiconductor structure 337 is bonded to the first semiconductor structure 341, and the second semiconductor structure 337 includes a second semiconductor layer 338 and a peripheral circuit 339 located on the second semiconductor layer 338; wherein the first transistor 315 is located between the capacitor 309 and the peripheral circuit 339; or, the second transistor is located between the capacitor and the peripheral circuit.

[0187] For ease of explanation, Figure 4 Only the front-side bonding of the second semiconductor structure 337 is shown. At this time, the first transistor 315 is located between the capacitor 309 and the peripheral circuit 339 . Figure 4 The back-side bonding of the second semiconductor structure, ie, the second transistor being located between the capacitor and the peripheral circuit, is not shown.

[0188] In the embodiment of the present disclosure, the first semiconductor structure 341 further includes:

[0189] A second stacked structure 318 and a third stacked structure 343, wherein the second stacked structure 318 and the third stacked structure 343 are respectively located on two opposite sides of the first stacked structure 302;

[0190] A first transistor 315 is located in the second stacked structure 318; a gate of the first transistor 315 (ie, the first gate layer 323) is connected to the second electrode 308 of the capacitor 309;

[0191] The second transistor 340 is located in the third stacked structure 343 ; the source 352 or the drain 351 of the second transistor 340 is connected to the second electrode 308 of the capacitor 309 .

[0192] Here, the first transistor 315 is a read transistor 316 , and the second transistor 340 is a write transistor 342 .

[0193] In the embodiment of the present disclosure, the second stacked structure 318 includes a second conductive layer 319; the first transistor 315 includes:

[0194] A first channel structure 360 ​​that penetrates the second stacked structure 318 and extends to the second electrode 308; the first channel structure 360 ​​includes a first channel layer 321, a first gate dielectric layer 322, and a first gate layer 323; the first channel layer 321 surrounds the first gate dielectric layer 322, and the first gate dielectric layer 322 surrounds the first gate layer 323; Figure 4 As shown in the dotted line box, two opposite ends of the first channel layer 321 arranged along the stacking direction respectively form the source 335 (eg, Figure 4 The drain 336 (shown in the dashed circle in the middle) of the first transistor (ie, the read transistor) Figure 4The source 335 of the first transistor (i.e., the read transistor) is connected to the second conductive layer 319, and the drain 336 of the first transistor (i.e., the read transistor) is connected to the first bit line 332; the first gate layer 323 is connected to the second electrode 308, and the gate of the first transistor (i.e., the read transistor) (i.e., the first gate layer 323) is connected to the second electrode 308 of the capacitor 309. For the convenience of illustrating the source 335 and the drain 336 of the read transistor, Figure 4 The dot-and-dash box only illustrates the first channel layer 321 and the first bit line 332 in the first channel hole 320 , but does not illustrate other structures in the first channel hole 320 .

[0195] Here, the second stacked structure 318 includes a first insulating layer 324, a second conductive layer 319, a second insulating layer 325, and a first isolation layer 326, which are stacked in sequence; wherein the first insulating layer 324 is in contact with the first stacked structure 302, and the second conductive layer 319 can form a source line of the first transistor 315. Along the Z direction, the first channel layer 321 sequentially penetrates the first isolation layer 326, the second insulating layer 325, and the second conductive layer 319, and the portion of the first channel layer 321 in contact with the second conductive layer 319 can form a source 335 of the first transistor (i.e., a read transistor).

[0196] Here, the first semiconductor structure 341 may include a first contact structure 334 , which penetrates the first isolation layer 326 and the second insulating layer 325 and extends into the second conductive layer 319 ; wherein the first contact structure 334 may be used to lead out an electrical signal of a source line.

[0197] Here, the first semiconductor structure 341 may include a third insulating layer 331 and a first bit line 332; wherein the surfaces of the first gate dielectric layer 322 and the first gate layer 323 are lower than the surface of the first channel layer 321, and the third insulating layer 331 and the first bit line 332 are arranged in the first channel hole 320; wherein the portion of the first channel layer 321 in contact with the first bit line 332 can form a drain 336 of the first transistor (i.e., a read transistor).

[0198] In the embodiment of the present disclosure, the third stacked structure 343 includes a third conductive layer 344; the second transistor 340 includes:

[0199] A second channel structure 361 that penetrates the third stacked structure 343 and extends to the second electrode 308; the second channel structure 361 includes a second gate dielectric layer 346 and a second channel layer 347; the second gate dielectric layer 346 surrounds the second channel layer 347; the third conductive layer 344 surrounds the second gate dielectric layer 346; wherein two ends of the second channel layer 347 that are oppositely arranged along the stacking direction respectively form a source 352 and a drain 351 (such as Figure 4 The source 352 or the drain 351 of the second transistor 340 is connected to the second electrode 308, and the drain 351 or the source 352 of the second transistor 340 is connected to the second bit line.

[0200] Here, the third stacked structure 343 includes a fourth insulating layer 348, a third conductive layer 344, and a fifth insulating layer 349 stacked in sequence; wherein the fourth insulating layer 348 contacts the first stacked structure 302, and the third conductive layer 344 can form a gate 358 (i.e., a word line) of a second transistor (i.e., a write transistor). Along the Z direction, the second channel layer 347 sequentially penetrates the fifth insulating layer 349 and the third conductive layer 344 and extends into the second electrode 308 of the capacitor 309, and the portion of the second channel layer 347 in contact with the second electrode 308 can form a source 352 of the second transistor (i.e., a write transistor).

[0201] Here, the first semiconductor structure 341 may include a sixth insulating layer 353 and a second contact structure 356; wherein the sixth insulating layer 353 is in contact with the fifth insulating layer 349, and the second contact structure 356 penetrates the sixth insulating layer 353 and is in contact with the second channel layer 347; wherein the portion of the second channel layer 347 in contact with the second contact structure 356 forms a drain 351 of a second transistor (i.e., a write transistor), and the second contact structure 356 can be used to lead out an electrical signal of a second bit line.

[0202] Here, the first semiconductor structure 341 may include a third contact structure 357; wherein the third contact structure 357 penetrates the sixth insulating layer 353 and the fifth insulating layer 349 and extends into the third conductive layer 344, the third contact structure 357 is electrically connected to the gate 358 of the second transistor (i.e., the write transistor), and the third contact structure 357 can be used to lead out the electrical signal of the word line of the second transistor 340.

[0203] In the embodiment of the present disclosure, the first semiconductor structure further includes:

[0204] A second stacked structure and a third stacked structure, wherein the second stacked structure and the third stacked structure are respectively located on two opposite sides of the first stacked structure;

[0205] A second transistor is located in the second stacked structure; the gate of the second transistor is connected to the second electrode of the capacitor;

[0206] A first transistor is located in the third stacked structure; a source or a drain of the first transistor is connected to the second electrode of the capacitor.

[0207] Here, the first transistor may be a write transistor, and the second transistor may be a read transistor.

[0208] In the embodiment of the present disclosure, the materials of the first channel layer and the second channel layer may include IGZO.

[0209] In the embodiment of the present disclosure, the material of the dielectric layer includes ferroelectric material.

[0210] refer to Figure 5 , Figure 5 A block diagram of a memory system provided by an embodiment of the present disclosure. Figure 5 As shown, the embodiment of the present disclosure provides a memory system 500, which includes:

[0211] The semiconductor device 501 in the above technical solution; and

[0212] A controller 502 is coupled to the semiconductor device 501 , and the controller 502 is configured to control the semiconductor device 501 .

[0213] In the embodiment of the present disclosure, the semiconductor device 501 may be a memory; or may be a part of a memory, that is, the semiconductor device 501 includes a memory cell array, and the memory cell array may form a memory together with peripheral circuits.

[0214] The memory system 500 may be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is, the memory system may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0215] In some embodiments, the controller 502 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0216] In other embodiments, the controller 502 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0217] The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof, and a memory system. The manufacturing method includes: providing a first semiconductor layer, an etch stop layer, and a first stacked structure stacked in sequence, the first stacked structure including a first conductive layer and an interlayer insulating layer stacked alternately; forming a capacitor hole that penetrates the first stacked structure and extends into the etch stop layer; forming a first electrode, a dielectric layer, and a second electrode in the capacitor hole in sequence to form a capacitor; wherein the first electrode includes a plurality of sub-electrodes spaced apart along the stacking direction, each sub-electrode being connected to the first conductive layer; removing the first semiconductor layer, the etch stop layer, and removing at least part of the first electrode and the dielectric layer located in the etch stop layer to expose at least part of the second electrode located in the etch stop layer. In the embodiment of the present disclosure, etching forms a capacitor hole that penetrates the first stacked structure and extends into the etch stop layer, and the first electrode, the dielectric layer, and the second electrode are formed in sequence in the capacitor hole, and the two ends of the second electrode of the capacitor that are oppositely arranged along the stacking direction are exposed by removing the etch stop layer, so that the first transistor and the second transistor can be formed later and connected to the two ends of the second electrode that are oppositely arranged along the stacking direction. Compared to the process of forming the transistor first and then the capacitor, it is necessary to remove the dielectric material layer covering the bottom of the capacitor hole through the capacitor hole. In the embodiment of the present disclosure, the etch stop layer is removed to expose the dielectric layer covering the bottom of the capacitor hole and at least part of the dielectric layer can be removed. In this way, the manufacturing difficulty of the semiconductor device can be reduced, which is beneficial to increase the number of stacking layers of the first stacking structure and improve the integration of the capacitor.

[0218] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0219] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Providing a first semiconductor layer, an etch stop layer and a first stacked structure stacked in sequence, wherein the first stacked structure comprises first conductive layers and interlayer insulating layers stacked alternately; forming a capacitor hole penetrating through the first stacked structure and extending into the etch stop layer; A first electrode, a dielectric layer and a second electrode are sequentially formed in the capacitor hole to form a capacitor; wherein the first electrode comprises a plurality of sub-electrodes spaced apart along a stacking direction, and each of the sub-electrodes is connected to the first conductive layer; The first semiconductor layer, the etch stop layer, and at least a portion of the first electrode and the dielectric layer located in the etch stop layer are removed to expose at least a portion of the second electrode located in the etch stop layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Two opposite ends of the second electrode arranged along the stacking direction are respectively connected to the first transistor and the second transistor.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: After sequentially forming a first electrode, a dielectric layer, and a second electrode in the capacitor hole to form a capacitor, the method further includes: forming a first transistor connected to the second electrode; After removing the first semiconductor layer, the etch stop layer, and removing at least a portion of the first electrode and the dielectric layer in the etch stop layer to expose at least a portion of the second electrode in the etch stop layer, the manufacturing method further includes: A second transistor connected to the second electrode is formed; wherein the capacitor, the first transistor and the second transistor together form a first semiconductor structure.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The forming of a first transistor connected to the second electrode comprises: forming a read transistor connected to the second electrode; wherein a gate of the read transistor is connected to the second electrode; The forming of a second transistor connected to the second electrode comprises: A write transistor connected to the second electrode is formed; wherein a source or a drain of the write transistor is connected to the second electrode.

5. The method for manufacturing a semiconductor device according to claim 3, wherein: The forming of a first transistor connected to the second electrode comprises: forming a write transistor connected to the second electrode; wherein a source or a drain of the write transistor is connected to the second electrode; The forming of a second transistor connected to the second electrode comprises: A read transistor connected to the second electrode is formed; wherein a gate of the read transistor is connected to the second electrode.

6. The method for manufacturing a semiconductor device according to claim 3, wherein: The manufacturing method further comprises: Providing a second semiconductor structure, the second semiconductor structure comprising a second semiconductor layer and a peripheral circuit located on the second semiconductor layer; After forming the first transistor connected to the second electrode, the manufacturing method further includes: The first semiconductor structure and the second semiconductor structure are bonded; wherein the first transistor is located between the capacitor and the peripheral circuit.

7. The method for manufacturing a semiconductor device according to claim 3, wherein: The manufacturing method further comprises: Providing a second semiconductor structure, the second semiconductor structure comprising a second semiconductor layer and a peripheral circuit located on the second semiconductor layer; After forming the second transistor connected to the second electrode, the manufacturing method further includes: The first semiconductor structure and the second semiconductor structure are bonded; wherein the second transistor is located between the capacitor and the peripheral circuit.

8. The method for manufacturing a semiconductor device according to claim 4 or 5, characterized in that: The forming of a read transistor connected to the second electrode comprises: forming a second stacked structure on the first stacked structure; the second stacked structure comprises a second conductive layer; forming a first channel hole penetrating the second stacked structure and extending into the second electrode; A first channel layer, a first gate dielectric layer and a first gate layer are formed in the first channel hole; wherein the first channel layer is connected to the second conductive layer, and the first gate layer is connected to the second electrode.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: Two opposite ends of the first channel layer arranged along the stacking direction respectively form the source and drain of the read transistor; wherein the source of the read transistor is connected to the second conductive layer, and the drain of the read transistor is connected to the first bit line.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The forming of a write transistor connected to the second electrode comprises: forming a third stacked structure on the first stacked structure; the third stacked structure comprising a third conductive layer; forming a second channel hole penetrating the third stacked structure and extending into the second electrode; A second gate dielectric layer and a second channel layer are formed in the second channel hole; wherein the second channel layer is connected to the second electrode.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: Two opposite ends of the second channel layer arranged along the stacking direction respectively form the source and drain of the write transistor; wherein the source or drain of the write transistor is connected to the second electrode, and the drain or source of the write transistor is connected to the second bit line.

12. The method for manufacturing a semiconductor device according to claim 10, wherein: The material of the first channel layer includes indium gallium zinc oxide (IGZO); and / or, The material of the second channel layer includes IGZO; and / or, The material of the dielectric layer includes ferroelectric material.

13. A semiconductor device, characterized in that: The semiconductor device comprises: a first semiconductor structure, wherein the first semiconductor structure comprises: A first stacked structure includes first conductive layers and interlayer insulating layers that are alternately stacked; A capacitor running through the first stacked structure, the capacitor comprising a first electrode, a dielectric layer, and a second electrode; wherein the first electrode comprises a plurality of sub-electrodes spaced apart along a stacking direction, each of the sub-electrodes being connected to the first conductive layer; and the second electrode comprises a first end and a second end oppositely disposed along the stacking direction; a first transistor connected to the first end of the second electrode; A second transistor connected to the second end of the second electrode; wherein the dielectric layer is in contact with the second transistor.

14. The semiconductor device according to claim 13, characterized in that The first transistor is a read transistor, and the second transistor is a write transistor; or, The first transistor is a write transistor, and the second transistor is a read transistor; wherein a gate of the read transistor is connected to the second electrode, and a source or a drain of the write transistor is connected to the second electrode.

15. The semiconductor device according to claim 13, wherein: The semiconductor device further comprises: A second semiconductor structure bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second semiconductor layer and a peripheral circuit located on the second semiconductor layer; wherein the first transistor is located between the capacitor and the peripheral circuit; or, the second transistor is located between the capacitor and the peripheral circuit.

16. The semiconductor device according to claim 13, wherein: The first semiconductor structure further comprises: A second stacked structure and a third stacked structure, wherein the second stacked structure and the third stacked structure are respectively located on two opposite sides of the first stacked structure; A first transistor located in the second stacked structure; a gate of the first transistor is connected to a second electrode of the capacitor; A second transistor is located in the third stacked structure; a source or a drain of the second transistor is connected to the second electrode of the capacitor.

17. The semiconductor device according to claim 16, characterized in that The second stacked structure includes a second conductive layer; the first transistor includes: A first channel structure that penetrates the second stacked structure and extends into the second electrode; the first channel structure includes a first channel layer, a first gate dielectric layer and a first gate layer; the first channel layer surrounds the first gate dielectric layer, and the first gate dielectric layer surrounds the first gate layer; wherein two ends of the first channel layer that are relatively arranged along the stacking direction respectively form the source and drain of the first transistor; the source of the first transistor is connected to the second conductive layer, and the drain of the first transistor is connected to the first bit line; the first gate layer is connected to the second electrode.

18. The semiconductor device according to claim 17, characterized in that The third stacked structure includes a third conductive layer; and the second transistor includes: A second channel structure that penetrates the third stacked structure and extends into the second electrode; the second channel structure includes a second gate dielectric layer and a second channel layer; the second gate dielectric layer surrounds the second channel layer; the third conductive layer surrounds the second gate dielectric layer; wherein two ends of the second channel layer that are oppositely arranged along the stacking direction respectively form the source and drain of the second transistor; the source or drain of the second transistor is connected to the second electrode, and the drain or source of the second transistor is connected to the second bit line.

19. The semiconductor device according to claim 13, characterized in that The first semiconductor structure further comprises: A second stacked structure and a third stacked structure, wherein the second stacked structure and the third stacked structure are respectively located on two opposite sides of the first stacked structure; a second transistor located in the second stacked structure; a gate of the second transistor being connected to a second electrode of the capacitor; A first transistor is located in the third stacked structure; a source or a drain of the first transistor is connected to the second electrode of the capacitor.

20. The semiconductor device according to claim 18, wherein: The material of the first channel layer includes IGZO; and / or, The material of the second channel layer includes IGZO; and / or, The material of the dielectric layer includes ferroelectric material.

21. A memory system, characterized in that: The memory system comprises: The semiconductor device according to any one of claims 13 to 20; and A controller is coupled to the semiconductor device, the controller being configured to control the semiconductor device.

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