Transistor and preparation method thereof

Abstract

The invention provides a transistor and a preparation method thereof. The transistor comprises a substrate and an epitaxial structure, the epitaxial structure is located on the substrate, a plurality of micro-channels are arranged on one surface, far away from the epitaxial structure, of the substrate, and the micro-channels are used for allowing a coolant to flow. A plurality of micro-channels are designed on one surface, far away from the epitaxial structure, of the substrate, and a flowing coolant is carried in the micro-channels to dissipate heat of the whole transistor, so that the transistor can still keep a normal temperature under a high-temperature severe working condition. Through the design, the stability and the yield of the transistor can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of light-emitting devices, and in particular to a transistor and a method for preparing the same. Background Art

[0002] High Electron Mobility Transistor (HEMT) is widely used in wireless communications, RF amplification, satellite communications, radar systems, and efficient power management due to its excellent power handling capability and low noise characteristics.

[0003] The related art provides a transistor, which includes a substrate, an epitaxial structure and other structures.

[0004] In the related art, since the transistor power is too large and the heat dissipation performance is poor, the device generates severe heat, which seriously affects the stability and yield of the transistor device. Summary of the invention

[0005] The embodiment of the present disclosure provides a transistor and a method for manufacturing the same, which can significantly improve the crystal heat dissipation problem and enhance the stability and yield of the transistor. The technical solution is as follows:

[0006] In one aspect, a transistor is provided, the transistor comprising: a substrate and an epitaxial structure;

[0007] The epitaxial structure is located on the substrate, and a side of the substrate away from the epitaxial structure has a plurality of microchannels, and the plurality of microchannels are used for the flow of coolant.

[0008] Optionally, the plurality of microchannels are evenly spaced and distributed.

[0009] Optionally, the cross-section of the microchannel is an inverted trapezoid.

[0010] Optionally, the transistor further comprises: a first electrode, a second electrode, a control electrode, a lead oxide layer, a connecting column, a first substrate and a second substrate;

[0011] The first electrode, the second electrode and the control electrode are electrically connected to the epitaxial structure respectively; the lead oxide layer covers the epitaxial structure, the second substrate covers the lead oxide layer, the connecting column connects the first electrode, the second electrode and the control electrode to the second substrate respectively, and the first substrate is bonded to a side of the substrate away from the epitaxial structure, covering the multiple microchannels.

[0012] Optionally, the connecting column is a copper column.

[0013] In another aspect, a method for manufacturing a transistor includes:

[0014] preparing an epitaxial structure on a substrate;

[0015] A plurality of microchannels are formed on a side of the substrate away from the epitaxial structure, and the plurality of microchannels are used for the flow of a coolant.

[0016] Optionally, forming a plurality of microchannels on a side of the substrate away from the epitaxial structure comprises:

[0017] Performing a thinning process on the substrate;

[0018] forming a first photoresist mask on the thinned substrate;

[0019] Under the protection of the first photoresist mask, the substrate is dry-etched to transfer the pattern of the first photoresist mask to the substrate to form a plurality of microchannels.

[0020] Optionally, the method further comprises:

[0021] Manufacturing a first electrode, a second electrode and a control electrode, wherein the first electrode, the second electrode and the control electrode are electrically connected to the epitaxial structure respectively;

[0022] Making connecting posts, wherein the connecting posts are respectively connected to the first electrode, the second electrode and the control electrode;

[0023] Manufacturing a lead oxide layer, wherein the lead oxide layer covers the epitaxial structure, and the connecting column passes through the lead oxide layer;

[0024] Covering the lead oxide layer with a second substrate, wherein the second substrate is connected to the connecting pillar;

[0025] The first substrate is attached to a side of the substrate away from the epitaxial structure to cover the plurality of microchannels.

[0026] Optionally, the manufacturing of the connecting column includes:

[0027] forming an electroplating seed layer on the surface of the epitaxial structure by a sputtering process;

[0028] forming a second photoresist mask on the surface of the epitaxial structure, wherein the second photoresist mask exposes the electroplating seed layer;

[0029] A wet copper electroplating process is adopted to manufacture copper pillars on the electroplating seed layer to obtain the connecting pillars.

[0030] Optionally, the method further comprises:

[0031] After the lead oxide layer is made and before the plurality of microchannels are formed, a bonding agent is coated on the surface of the lead oxide layer and the bonding agent is used to bond the lead oxide layer to a temporary substrate;

[0032] After forming the plurality of microfluidic channels, the lead oxide layer is separated from the temporary substrate.

[0033] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0034] In the disclosed embodiment, multiple microchannels are designed on the side of the substrate away from the epitaxial structure, and the microchannels carry flowing coolant to dissipate heat for the entire transistor, so that the transistor can still maintain a normal temperature under high temperature and harsh working conditions. The above design can improve the stability and yield of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;

[0037] Figure 2 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure;

[0038] Figure 3 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure;

[0039] Figure 4 is a schematic diagram of a structure in a transistor manufacturing process provided by an embodiment of the present disclosure;

[0040] Figure 5 is a schematic diagram of a structure in a transistor manufacturing process provided by an embodiment of the present disclosure;

[0041] Figure 6 is a schematic diagram of a structure in a transistor manufacturing process provided by an embodiment of the present disclosure;

[0042] Figure 7 It is a structural schematic diagram of a transistor manufacturing process provided by an embodiment of the present disclosure.

[0043] The reference numerals are as follows:

[0044] 101: substrate; 102: epitaxial structure; 103: first substrate; 104: first electrode; 105: second electrode; 106: control electrode; 107: lead oxide layer; 108: connecting column; 109: second substrate; 111: microchannel; 1010: insulating layer; 1011: first photoresist mask; 1021: channel layer; 1022: barrier layer; 301: bonding agent; 302: temporary substrate; 303: back gold layer; 401: coolant. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0046] Figure 1 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure. Figure 1 , the transistor comprises: a substrate 101, an epitaxial structure 102;

[0047] The epitaxial structure 102 is located on the substrate 101 . A surface of the substrate 101 away from the epitaxial structure 102 has a plurality of microchannels 111 . The plurality of microchannels 111 are used for the coolant 401 to flow.

[0048] In the disclosed embodiment, multiple microchannels are designed on the side of the substrate away from the epitaxial structure, and the microchannels carry flowing coolant to dissipate heat for the entire transistor, so that the transistor can still maintain a normal temperature under high temperature and harsh working conditions. The above design can improve the stability and yield of the transistor.

[0049] Among them, the microchannel refers to a strip-shaped groove opened on the substrate for the flow of coolant to take away the heat of the transistor. Due to the small size of the groove, it is called a microchannel.

[0050] In the embodiment of the present disclosure, the plurality of microchannels 111 are evenly spaced and distributed.

[0051] In this implementation, by distributing the plurality of microchannels 111 at intervals, it can be ensured that the heat dissipation effect of the plurality of microchannels acts evenly on various regions of the transistor, which is beneficial to the heat dissipation effect.

[0052] Exemplarily, the plurality of microchannels 111 are linear microchannels 111 , the plurality of microchannels 111 are distributed in parallel and at intervals, and the distance between any two adjacent microchannels 111 is a constant value.

[0053] In other examples, the plurality of microchannels 111 may also be curved or zigzag, which is not limited in the embodiments of the present disclosure.

[0054] In the embodiment of the present disclosure, the cross section of the microchannel 111 is an inverted trapezoid. On the one hand, the inverted trapezoidal channel is easy to manufacture, and on the other hand, this shape can help reduce the resistance of the coolant flow, make the coolant flow faster, increase the rate of heat exchange, and facilitate heat dissipation.

[0055] In other embodiments, the cross-section of the microchannel 111 may also be rectangular or arc-shaped, which is not limited in the embodiments of the present disclosure.

[0056] In the disclosed embodiment, the coolant 401 in the microchannel 111 can be water, silicone oil or HCFC (hydrochlorofluorocarbon) and liquid refrigerants with equivalent effects. The above coolant 401 can fully absorb the heat dissipated by the epitaxial structure, reduce the temperature of the epitaxial structure, and facilitate heat dissipation.

[0057] In the disclosed embodiment, the microchannel 111 may be opened to expose the epitaxial structure, that is, the bottom is on the epitaxial structure.

[0058] In another example, the microchannel 111 may also be opened until the epitaxial structure is not exposed, that is, the bottom is still on the substrate 101 .

[0059] Exemplarily, the coolant 401 in the microchannel 111 is HCFC.

[0060] In the embodiment of the present disclosure, the substrate 101 may be any one of substrates such as a sapphire patterned substrate, a Si substrate, and a SiC substrate. The embodiment of the present disclosure does not limit the material of the substrate 101.

[0061] Exemplarily, the substrate 101 is a Si substrate. Si has good electrical conductivity and thermal conductivity, which can ensure that the chip has good heat dissipation. Si is also easy to process and has a low manufacturing cost.

[0062] In the embodiment of the present disclosure, the epitaxial structure 102 includes a channel layer 1021 and a barrier layer 1022 , and the channel layer 1021 and the barrier layer 1022 are stacked on the substrate 101 .

[0063] In the embodiment of the present disclosure, the channel layer 1021 may be a GaN channel layer. GaN has high thermal conductivity, which helps to efficiently dissipate heat and improve the stability and life of the device. It also has high electron mobility, which ensures the electrical conductivity of the epitaxial structure.

[0064] In the embodiment of the present disclosure, the thickness of the channel layer 1021 can be 200-400 nm. A channel layer of this thickness will not increase the risk of leakage due to being too thin, thereby affecting the performance of the device, nor will it be difficult to miniaturize the device due to being too thick.

[0065] Exemplarily, the thickness of the channel layer 1021 is 300 nm.

[0066] In the embodiment of the present disclosure, the barrier layer 1022 may be an AlGaN barrier layer. Application of the AlGaN barrier layer enhances the performance of the device, including improving brightness, efficiency, and reliability.

[0067] In the embodiment of the present disclosure, the proportion of Al in the barrier layer 1022 may be 20-25%. By adjusting the ratio of aluminum to gallium, the energy band structure can be precisely controlled, thereby optimizing the injection efficiency of electrons and holes.

[0068] Exemplarily, Al accounts for 25% of the barrier layer 1022 .

[0069] Alternatively, if Figure 1 As shown, the transistor further includes: a first electrode 104, a second electrode 105, a control electrode 106, a lead oxide layer 107, a connecting column 108, a first substrate 103 and a second substrate 109;

[0070] The first electrode 104, the second electrode 105 and the control electrode 106 are electrically connected to the epitaxial structure 102 respectively; the lead oxide layer 107 covers the epitaxial structure 102, the second substrate 109 covers the lead oxide layer 107, the connecting column 108 connects the first electrode 104, the second electrode 105 and the control electrode 106 to the second substrate 109 respectively, and the first substrate 103 is attached to the side of the substrate 101 away from the epitaxial structure 102, covering multiple microchannels 111.

[0071] In this implementation, the lead oxide layer is provided to protect the device surface from environmental influences, and the second substrate is connected via a connecting column. The connecting column has good ductility, which makes it easier to connect the electrode to the external substrate.

[0072] In the embodiment of the present disclosure, the first substrate 103 functions as a cover.

[0073] Exemplarily, the first substrate 103 may be a packaging material cover.

[0074] In the embodiment of the present disclosure, the first electrode 104 may be a source electrode, the second electrode 105 may be a drain electrode, and the control electrode 106 may be a gate electrode.

[0075] In the embodiment of the present disclosure, the lead oxide layer 107 may be 6 to 20 μm thick. The lead oxide layer of this thickness will not affect the protective effect due to being too thin, nor will it be too thick to make the transistor difficult to miniaturize.

[0076] Exemplarily, the lead oxide layer 107 has a thickness of 15 μm.

[0077] In the embodiment of the present disclosure, the connection pillar 108 may be a copper pillar. Copper has good ductility and can make it easier to connect the electrode to the external substrate.

[0078] In the disclosed embodiment, the connection pillar 108 may be manufactured using a wet copper electroplating process, which may increase the manufacturing efficiency of the connection pillar and reduce the cost.

[0079] In other embodiments, the connection pillar 108 may also be made of other conductive metals, or may be made using other processes, which is not limited in the embodiments of the present disclosure.

[0080] In the embodiment of the present disclosure, the height of the connecting pillar 108 may be 30-80 μm, which can ensure that the connecting pillar extends out of the lead oxide layer but is not too long.

[0081] Exemplarily, the height of the connection pillar 108 is 60 μm. In the embodiment of the present disclosure, the second substrate 109 may be a printed circuit board (PCB).

[0082] In the disclosed embodiment, the second substrate 109 is soldered to the connection pillars 108 via solder balls 112 .

[0083] In the disclosed embodiment, the solder ball 112 may be made of a gold-tin or silver-tin alloy material.

[0084] In the embodiment of the present disclosure, the transistor may further include a back gold layer 303 , and the back gold layer 303 covers a side of the substrate 101 where the microchannel is opened.

[0085] In the embodiment of the present disclosure, the back gold layer 303 may be a Ti, TiW or Au back gold layer.

[0086] In the embodiment of the present disclosure, when the back gold layer 303 is a Ti layer, the thickness of the back gold layer 303 can be 10 to 100 nm; when the back gold layer 303 is a TiW layer, the thickness of the back gold layer 303 can be 10 to 100 nm; when the back gold layer 303 is an Au layer, the thickness of the back gold layer 303 can be 100 to 600 nm.

[0087] Exemplarily, when the back gold layer 303 is a Ti layer, the thickness of the back gold layer 303 is 50 nm, when the back gold layer 303 is a TiW layer, the thickness of the back gold layer 303 is 50 nm, and when the back gold layer 303 is an Au layer, the thickness of the back gold layer 303 is 300 nm.

[0088] like Figure 1 As shown, the transistor may further include an insulating layer 1010 , wherein the insulating layer 1010 covers the barrier layer 1022 , exposing the first electrode 104 , the second electrode 105 and the control electrode 106 .

[0089] Figure 2 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure. Figure 2The method steps include:

[0090] S11. Preparing an epitaxial structure on a substrate.

[0091] S12, forming a plurality of microchannels on a side of the substrate away from the epitaxial structure, wherein the plurality of microchannels are used for coolant to flow.

[0092] In the disclosed embodiment, multiple microchannels are designed on the side of the substrate away from the epitaxial structure, and the microchannels carry flowing coolant to dissipate heat for the entire transistor, so that the transistor can still maintain a normal temperature under high temperature and harsh working conditions. The above design can improve the stability and yield of the transistor.

[0093] Figure 3 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure. Figure 3 The method steps include:

[0094] S21. Forming a channel layer and a barrier layer in sequence on the substrate to form an epitaxial structure.

[0095] The substrate may be any one of a sapphire patterned substrate, a Si substrate, a SiC substrate and the like.

[0096] Exemplarily, the substrate is a Si substrate.

[0097] In one example, step S21 includes:

[0098] The first step is to make a channel layer.

[0099] In the embodiment of the present disclosure, the channel layer may be a GaN channel layer. GaN has high thermal conductivity, which helps to dissipate heat efficiently and improve the stability and life of the device. It also has high electron mobility, which ensures the electrical conductivity of the epitaxial structure.

[0100] In the embodiment of the present disclosure, the channel layer thickness may be 200 to 400 nm. A channel layer of this thickness will not increase the risk of leakage due to being too thin, thereby affecting the performance of the device, nor will it be difficult to miniaturize the device due to being too thick.

[0101] Exemplarily, the channel layer thickness is 300 nm.

[0102] The second step is to make the barrier layer.

[0103] In the embodiment of the present disclosure, the barrier layer may be an AlGaN barrier layer. Application of the AlGaN barrier layer enhances the performance of the device, including improving brightness, efficiency and reliability.

[0104] In the embodiment of the present disclosure, the proportion of Al in the barrier layer can be 20-25%. By adjusting the ratio of aluminum to gallium, the energy band structure can be precisely controlled, thereby optimizing the injection efficiency of electrons and holes.

[0105] Exemplarily, Al accounts for 25% in the barrier layer.

[0106] S22, manufacturing a first electrode, a second electrode and a control electrode, wherein the first electrode, the second electrode and the control electrode are electrically connected to the epitaxial structure respectively.

[0107] The first electrode and the second electrode are connected through the barrier layer and the channel layer, and the control electrode is connected to the barrier layer.

[0108] In one example, step S22 includes:

[0109] In the first step, a first through hole and a second through hole are opened on the barrier layer.

[0110] In the second step, a first electrode and a second electrode are manufactured. The first electrode is connected to the channel layer through the first through hole, and the second electrode is connected to the channel layer through the second through hole.

[0111] In the embodiment of the present disclosure, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0112] In the embodiment of the present disclosure, the first electrode may include a first Ti sublayer, an Al sublayer, a second Ti sublayer, and a TiN sublayer (anti-oxidation sublayer) stacked in sequence.

[0113] In the embodiment of the present disclosure, the second electrode may include a first Ti sublayer, an Al sublayer, a second Ti sublayer, and a TiN sublayer (anti-oxidation sublayer) stacked in sequence.

[0114] The third step is to make the control electrode.

[0115] In the embodiment of the present disclosure, the control electrode may include a first Ti sub-layer, an Al sub-layer, and a second Ti sub-layer stacked in sequence.

[0116] Optionally, the method further comprises manufacturing an insulating layer after manufacturing the first electrode, the second electrode and the control electrode, wherein the insulating layer covers the barrier layer and exposes the first electrode, the second electrode and the control electrode.

[0117] Figure 4 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure, such as Figure 4 As shown, the first electrode 104 and the second electrode 105 are connected through the barrier layer 1022 and the channel layer 1021, and the control electrode 106 is connected to the barrier layer 1022. The insulating layer 1010 covers the barrier layer 1022, exposing the first electrode 104, the second electrode 105 and the control electrode 106.

[0118] S23, making connection columns, wherein the connection columns are respectively connected to the first electrode, the second electrode and the control electrode.

[0119] Figure 4 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure, such as Figure 4 As shown, three connection pillars 108 are respectively connected to the first electrode 104 , the second electrode 105 and the control electrode 106 .

[0120] In one example, step S23 includes:

[0121] In the first step, a sputtering process is used to form an electroplating seed layer on the surface of the epitaxial structure.

[0122] In the disclosed embodiment, the connection pillar may be a copper pillar. Copper has good ductility and can make it easier to connect the electrode to the external substrate.

[0123] In the second step, a second photoresist mask is formed on the surface of the epitaxial structure, wherein the second photoresist mask exposes the electroplating seed layer.

[0124] The third step is to use a wet copper electroplating process to make copper columns on the electroplating seed layer to obtain the connecting columns.

[0125] In the disclosed embodiment, the connecting column is manufactured by using a wet copper electroplating process, which can make the manufacturing efficiency of the connecting column higher and the cost lower.

[0126] In the embodiment of the present disclosure, the height of the connecting pillar can be 30-80 μm, which can ensure that the connecting pillar extends out of the lead oxide layer but is not too long.

[0127] Exemplarily, the height of the connecting pillar is 60 μm.

[0128] After the electroplating is completed, the second photoresist mask is removed by a stripping process, and the surface is processed by an etching device to remove the excess seed layer.

[0129] S24, manufacturing a lead oxide layer, wherein the lead oxide layer covers the epitaxial structure, and the connecting column passes through the lead oxide layer.

[0130] In one example, step S24 includes:

[0131] The first step is to create a lead oxide layer.

[0132] In the disclosed embodiment, the lead oxide layer may be 6 to 20 μm thick. The lead oxide layer of this thickness will not be too thin to affect the protective effect, nor will it be too thick to make the transistor difficult to miniaturize.

[0133] Exemplarily, the lead oxide layer has a thickness of 15 μm.

[0134] In this step, the lead oxide layer is formed by coating.

[0135] The second step is to bake the lead oxide layer.

[0136] See also Figure 4 , the lead oxide layer 107 covers the epitaxial structure 102 and the insulating layer 1010 .

[0137] S25, coating a bonding agent on the surface of the lead oxide layer, and bonding the lead oxide layer to a temporary substrate via the bonding agent.

[0138] Figure 5 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure, such as Figure 5 As shown, the bonding agent 301 covers the lead oxide layer 107 and wraps the upper end portion of the connection column 108, and the temporary substrate 302 is bonded to the lead oxide layer 107 through the bonding agent.

[0139] In one example, step S25 includes:

[0140] The first step is to apply bonding agent.

[0141] The second step is to bond the temporary substrate.

[0142] In the embodiment of the present disclosure, the temporary substrate may be any one of substrates such as a sapphire patterned substrate, a Si substrate, and a SiC substrate.

[0143] Exemplarily, the substrate is a Si substrate.

[0144] S26, forming a plurality of microchannels on a side of the substrate away from the epitaxial structure.

[0145] In one example, step S26 includes:

[0146] The first step is to thin the substrate.

[0147] In an embodiment of the present disclosure, a wafer grinder is used to thin the substrate.

[0148] In the embodiment of the present disclosure, the thickness of the substrate after thinning can be 100-300 μm.

[0149] Exemplarily, the thickness of the substrate after thinning is 200 μm.

[0150] The second step is to form a first photoresist mask on the thinned substrate.

[0151] The third step is to perform dry etching on the substrate under the protection of the first photoresist mask, transfer the pattern of the first photoresist mask to the substrate, and form a plurality of microchannels.

[0152] Exemplarily, Cl gas is used for dry etching.

[0153] After the etching is completed, the first photoresist mask is removed through a stripping process.

[0154] Figure 6 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure, such as Figure 6 As shown, a first photoresist mask 1011 is coated on the substrate 101 , and the cross-sectional shape of the first photoresist mask 1011 is a plurality of regular trapezoids. Figure 7 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure, such as Figure 7 As shown, after etching, the pattern of the first photoresist mask 1011 is transferred to the substrate 101 to form a plurality of microchannels 111 .

[0155] In the embodiment of the present disclosure, the microchannel 111 may be opened to expose the epitaxial structure, that is, the bottom is on the epitaxial structure.

[0156] In another example, the microchannel 111 may also be opened until the epitaxial structure is not exposed, that is, the bottom is still on the substrate 101 .

[0157] S27, making a back gold layer on the substrate.

[0158] Figure 7 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure, such as Figure 7 As shown, the back gold layer 303 covers the substrate 101 .

[0159] In the embodiment of the present disclosure, the back gold layer may be a Ti, TiW or Au back gold layer.

[0160] In the disclosed embodiment, the back gold layer is a Ti layer with a thickness of 10 to 100 nm, the back gold layer is a TiW layer with a thickness of 10 to 100 nm, and the back gold layer is an Au layer with a thickness of 100 to 600 nm.

[0161] Exemplarily, the back gold layer is a Ti layer with a thickness of 50 nm, the back gold layer is a TiW layer with a thickness of 50 nm, and the back gold layer is an Au layer with a thickness of 300 nm.

[0162] S28, separating the lead oxide layer from the temporary substrate.

[0163] The lead oxide layer and the temporary substrate are debonded, and the thinned lead oxide layer is separated from the temporary substrate by a debonder. The transistors are then cut by a grinding wheel cutter and sorted by a chip sorter.

[0164] S29, covering the lead oxide layer with a second substrate, wherein the second substrate is connected to the connecting pillar.

[0165] The transistor body and the second substrate are packaged by filp-chip flip-chip, the pins on the front side of the second substrate are connected with the copper pillars, and the back side of the second substrate is exposed.

[0166] S30, attaching a first substrate to a side of the substrate away from the epitaxial structure to cover the plurality of microchannels.

[0167] In the embodiment of the present disclosure, the first substrate is attached to a side of the substrate away from the epitaxial structure by using a conductive adhesive patch.

[0168] In the embodiment of the present disclosure, the first substrate serves as a cover plate.

[0169] S31, introducing refrigerant into the microchannel.

[0170] The disclosed embodiment of the present invention forms a microchannel through which the refrigerant can pass by opening a groove on the back of the substrate, and then combines the flip-chip advanced packaging form to place the refrigerant inside the microchannel to ensure that the refrigerant can flow in the microchannel, and configures a circulation system outside the transistor to provide power for the refrigerant to flow in the microchannel, thereby ensuring the heat dissipation performance of the transistor. The refrigerant can be purged by a remote fan in the external area of ​​the transistor to transfer heat to the outside of the transistor, ensuring that the chip can maintain a normal temperature under high temperature and harsh working conditions. For example, this solution can reduce the device conduction temperature from 75°C to 25°C; in the summer use scenario of the car, when the outdoor temperature is 55°C, the device operating temperature is reduced from 125°C to 25°C. Heat dissipation through microchannels can improve the service life of the device, improve the reliability of the device, and ensure that the device does not overheat.

[0171] In the embodiments of the present disclosure, the transistor is manufactured by photolithography, thin film, etching, wet process and other equipment, and the transistor can be a D-mode or E-mode device. The transistor can be combined with a capacitor and / or a resistor to form a circuit to realize the basic functions of the circuit.

[0172] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A transistor, characterized in that: The transistor comprises: a substrate (101) and an epitaxial structure (102); The epitaxial structure (102) is located on the substrate (101), and a surface of the substrate (101) away from the epitaxial structure (102) has a plurality of microchannels (111), and the plurality of microchannels (111) are used for allowing a coolant (401) to flow.

2. The transistor according to claim 1, characterized in that The plurality of microchannels (111) are evenly spaced and distributed.

3. The transistor according to claim 1, characterized in that The cross section of the microchannel (111) is an inverted trapezoid.

4. The transistor according to any one of claims 1 to 3, characterized in that: The transistor further comprises: a first electrode (104), a second electrode (105), a control electrode (106), a lead oxide layer (107), a connecting column (108), a first substrate (103) and a second substrate (109); The first electrode (104), the second electrode (105) and the control electrode (106) are respectively electrically connected to the epitaxial structure (102); the lead oxide layer (107) covers the epitaxial structure (102); the second substrate (109) covers the lead oxide layer (107); the connecting column (108) respectively connects the first electrode (104), the second electrode (105) and the control electrode (106) to the second substrate (109); the first substrate (103) is bonded to a surface of the substrate (101) away from the epitaxial structure (102), and covers the plurality of microchannels (111).

5. The transistor according to claim 4, characterized in that The connecting pillar (108) is a copper pillar.

6. A method for preparing a transistor, characterized in that: The transistor preparation method comprises: preparing an epitaxial structure on a substrate; A plurality of microchannels are formed on a side of the substrate away from the epitaxial structure, and the plurality of microchannels are used for coolant to flow.

7. The transistor manufacturing method according to claim 6, characterized in that: The forming of a plurality of microchannels on a side of the substrate away from the epitaxial structure comprises: Performing a thinning process on the substrate; forming a first photoresist mask on the thinned substrate; Under the protection of the first photoresist mask, the substrate is dry-etched to transfer the pattern of the first photoresist mask to the substrate to form a plurality of microchannels.

8. The transistor manufacturing method according to claim 6 or 7, characterized in that: The method further comprises: Manufacturing a first electrode, a second electrode and a control electrode, wherein the first electrode, the second electrode and the control electrode are electrically connected to the epitaxial structure respectively; Making connecting posts, wherein the connecting posts are respectively connected to the first electrode, the second electrode and the control electrode; Manufacturing a lead oxide layer, wherein the lead oxide layer covers the epitaxial structure, and the connecting column passes through the lead oxide layer; Covering the lead oxide layer with a second substrate, wherein the second substrate is connected to the connecting pillar; The first substrate is attached to a side of the substrate away from the epitaxial structure to cover the plurality of microchannels.

9. The transistor manufacturing method according to claim 8, characterized in that: The method of making the connecting column comprises: forming an electroplating seed layer on the surface of the epitaxial structure by a sputtering process; forming a second photoresist mask on the surface of the epitaxial structure, wherein the second photoresist mask exposes the electroplating seed layer; A wet copper electroplating process is adopted to manufacture copper pillars on the electroplating seed layer to obtain the connecting pillars.

10. The transistor manufacturing method according to claim 8, characterized in that: The method further comprises: After the lead oxide layer is made and before the plurality of microchannels are formed, a bonding agent is coated on the surface of the lead oxide layer and the bonding agent is used to bond the lead oxide layer to a temporary substrate; After forming the plurality of microfluidic channels, the lead oxide layer is separated from the temporary substrate.

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