Semiconductor chip, preparation method and computing device

Abstract

The embodiment of the invention provides a semiconductor chip, a preparation method and computing equipment. The semiconductor chip comprises a substrate, the substrate comprises a chip functional area and four L-shaped metal pieces surrounding the functional area, the four L-shaped metal pieces are arranged at intervals and form a ring in a surrounding mode, and any two adjacent L-shaped metal pieces comprise the first L-shaped metal piece and the second L-shaped metal piece; the first L-shaped metal piece comprises a first strip-shaped component and a second strip-shaped component which are vertically arranged, and the second L-shaped metal piece comprises a third strip-shaped component and a fourth strip-shaped component which are vertically arranged; the extension directions of the first strip-shaped part and the third strip-shaped part are opposite, and the extension directions of the second strip-shaped part and the fourth strip-shaped part are the same; the orthographic projection of the first strip-shaped component and the orthographic projection of the third strip-shaped component on a first plane have a first overlapped part, and the first plane is perpendicular to the extending direction of the second strip-shaped component. According to the technical scheme provided by the embodiment of the invention, the arc generation probability can be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor chip, a preparation method and a computing device. Background Art

[0002] The defects caused by arc discharge have a great impact on the product performance of semiconductor chips. Arc discharge is a gas discharge phenomenon that produces a continuous and strong arc between two electrodes under certain conditions. This arc has extremely high temperature and energy, which is enough to cause serious damage to surrounding chips.

[0003] However, arc discharge often occurs in the back-end process of chips. Summary of the invention

[0004] In view of the above problems, the present application is proposed to provide a semiconductor chip, a preparation method and a computing device that solve the above problems or at least partially solve the above problems.

[0005] Therefore, a first aspect of the present application provides a semiconductor chip, comprising:

[0006] A substrate, wherein the substrate includes a chip functional area and a sealing ring structure surrounding the chip functional area;

[0007] The sealing ring structure comprises: four L-shaped metal pieces, which are arranged at intervals from each other and form a ring, wherein any two adjacent L-shaped metal pieces comprise a first L-shaped metal piece and a second L-shaped metal piece;

[0008] The first L-shaped metal member includes a first strip member and a second strip member disposed perpendicularly to each other, and the second L-shaped metal member includes a third strip member and a fourth strip member disposed perpendicularly to each other;

[0009] The first strip component and the third strip component extend in opposite directions;

[0010] There is a first overlapping portion between the orthographic projections of the first strip-shaped component and the third strip-shaped component on a first plane, and the first plane is perpendicular to an extending direction of the first strip-shaped component.

[0011] A second aspect of the present application provides a method for preparing a semiconductor chip, comprising:

[0012] providing a substrate;

[0013] forming a chip functional area and a sealing ring structure surrounding the chip functional area on the substrate;

[0014] Wherein, the sealing ring structure comprises: four L-shaped metal parts, the four L-shaped sealing parts are arranged at intervals from each other and form a ring, wherein any two adjacent L-shaped metal parts comprise a first L-shaped metal part and a second L-shaped metal part;

[0015] The first L-shaped metal part includes a first strip component and a second strip component which are arranged perpendicular to each other, and the second L-shaped metal part includes a third strip component and a fourth strip component which are arranged perpendicular to each other; the extension directions of the first strip component and the third strip component are opposite; the orthographic projections of the first strip component and the third strip component on the first plane along the extension direction of the second strip component have a first overlapping part, and the first plane is perpendicular to the extension direction of the second strip component.

[0016] A third aspect of the present application provides a computing device, comprising: the above-mentioned semiconductor chip.

[0017] Through research, it is found that in the back-end process of semiconductor chips, arc discharge phenomenon is easy to occur on the sealing ring. This is because: the sealing ring is a complete annular metal structure. After the plasma charge used for etching is attracted to the sealing ring, it flows along the sealing ring under the action of the electric field and gathers at a certain position on the sealing ring. After a large amount of charge accumulates at this position, it is easy to cause arc phenomenon. In the technical solution provided in the embodiment of the present application, the sealing ring structure is designed to be four mutually isolated L-shaped metal parts. In this way, the plasma charge adsorbed on the sealing ring structure cannot be gathered in one place, but is dispersed on four mutually isolated L-shaped metal parts, thereby reducing the probability of arc occurrence. In addition, the four L-shaped metal parts are arranged in sequence to form a ring, and the orthographic projections of the two strip-shaped parts with opposite extension directions in any two adjacent L-shaped metal parts on the first plane have overlapping parts, that is, although the sealing metal ring is separated into four mutually isolated L-shaped metal parts, the chip functional area in the semiconductor chip can be completely surrounded by the four L-shaped metal parts through the overlapping design. It can be seen that the sealing ring structure provided in the embodiment of the present application not only has good mechanical structural strength, which can effectively reduce the impact of chip cutting stress on the chip, but also has good sealing performance, which can effectively prevent water vapor and dust from entering the interior of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1a The schematic diagram of the principle of arc discharge is shown in FIG.

[0020] Figure 1b It is a schematic diagram of the structure of an existing semiconductor chip;

[0021] Figure 2 A schematic diagram of the structure of a semiconductor chip provided in one embodiment of the present application;

[0022] Figure 3 A schematic diagram of a preparation method according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below according to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0024] In addition, some of the processes described in the specification, claims and the above-mentioned figures of the present application include multiple operations that appear in a specific order, and these operations may not be executed in the order in which they appear in this article or may be executed in parallel. The serial numbers of the operations, such as 201, 202, etc., are only used to distinguish between different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0025] First, the vocabulary involved in the embodiments of the present application is explained. It can be understood that this explanation is for a clearer understanding of the embodiments of the present application, and does not necessarily constitute a limitation on the embodiments of the present application.

[0026] A silicon-on-insulator (SOI) substrate includes a top silicon layer, a silicon substrate (or bottom silicon layer), and a silicon dioxide buried oxide layer between the top silicon layer and the silicon substrate.

[0027] Photonic Integrated Circuit (PIC) chip refers to a chip that uses photons to process and transmit information.

[0028] At present, arc discharge often occurs in the back-end process of semiconductor chips, and the defects it produces have a great impact on the performance of the product.

[0029] Taking silicon photonic integrated circuit chips as an example, the causes of arc discharge are analyzed:

[0030] Silicon photonic integrated circuit chips usually use silicon-on-insulator (SOI) wafers as substrates, which is equivalent to its main structure being on an insulator substrate. The charges adsorbed by any structure on the insulator substrate are not easy to be extracted, which greatly increases the probability of arc defects. In the back-end process, plasma etching is sometimes required, that is, the semi-finished chip needs to be placed on a plasma machine, fixed by an electrostatic ceramic chuck, and the stability of the plasma is ensured by adjusting the bias power supply and the sheath voltage, so that the plasma flow is concentrated in the groove area to be etched, but more or less plasma is offset during the movement and adsorbed to other areas, such as the closed loop area. The closed loop area adsorbs a large amount of charges. Under the action of the magnetic field, a large amount of charges may gather at a certain position of the closed loop, thereby forming a large voltage difference with other components and generating arc discharge.

[0031] like Figure 1a As shown, a plurality of photonic integrated circuit chips are formed on the SOI wafer substrate (Figure 1 shows a photonic integrated circuit chip S1 and a photonic integrated circuit chip S2). The area between different photonic integrated circuit chips on the wafer is used to separate the chips, and is used to place some marking areas and process monitoring areas for determining the measurement position and monitoring the manufacturing process. Among them, the SOI wafer substrate includes a top silicon c, a silicon substrate (or bottom silicon) a, and a silicon dioxide buried oxide layer b located between the top silicon c and the silicon substrate a. Among them, the top silicon c forms the semiconductor device area of ​​each photonic integrated circuit chip through processes such as etching. After obtaining each semiconductor device area, a metal interconnect structure e and a sealing ring structure d are prepared through a back-end process. Among them, the metal interconnect structure e is used to realize the electrical connection between the devices in the semiconductor device area, and then realize the circuit connection, and the sealing ring structure d (such as Figure 1b As shown in FIG. 1 , the metal interconnection structure e is arranged around the metal interconnection structure e to protect the metal interconnection structure e. It should be noted that the semiconductor device area and the metal interconnection structure above it constitute the chip functional area. Figure 1a As shown, the semiconductor device region (which is obtained by etching the top silicon c), the metal interconnect structure and the sealing ring structure are all located above the silicon dioxide buried oxide layer b. Due to the insulating property of the silicon dioxide buried oxide layer b, the charges adsorbed on the sealing ring structure cannot be conducted to the substrate. The charges adsorbed on the sealing ring structure will be conducted inside the sealing ring under the action of the electric field and gathered at the same position, thereby forming a large voltage difference with other components and generating arc discharge.

[0032] In order to solve or partially solve the above technical problems, an embodiment of the present application provides a solution to reduce the occurrence of arc discharge through structural design.

[0033] Figure 2 This is a schematic diagram of the structure of a semiconductor chip provided in one embodiment of the present application. The semiconductor chip may be an electronic integrated circuit chip or a photonic integrated circuit chip. Figure 2 As shown, the semiconductor chip 100 includes: a substrate (not shown), the substrate including a chip functional area 1 and a sealing ring structure surrounding the chip functional area 1 .

[0034] The chip functional area 1 may include a semiconductor device area and a metal interconnection structure located above the semiconductor device area.

[0035] The metal interconnect structure may be a single-layer structure or a multi-layer structure.

[0036] In one embodiment, when the metal interconnect structure is a multi-layer structure, the metal interconnect structure includes a multi-layer metal interconnect layer and a conductive through hole connecting adjacent metal interconnect layers. The material of the metal interconnect structure can be, for example, a metal material such as copper, silver or gold, which is not specifically limited in the embodiment of the present application. In addition, the device in the semiconductor device area is electrically connected to the metal interconnect structure through a contact hole. Exemplarily, the material of the contact hole can be a metal material such as tungsten.

[0037] Optionally, the substrate is a semiconductor substrate, such as a silicon substrate or a germanium substrate.

[0038] Optionally, the substrate is an SOI substrate, wherein the chip functional area 1 and the sealing ring structure are formed on the top silicon layer of the SOI substrate.

[0039] The sealing ring structure includes four L-shaped metal parts 2, which are arranged at intervals to form a ring. That is, the four L-shaped metal parts are independent of each other and have no electrical connection with each other. The four L-shaped metal parts are arranged in sequence to form a ring surrounding the chip functional area. Figure 2 As shown, the ring resembles a square ring.

[0040] Each L-shaped metal member 2 includes two strip-shaped components which are arranged perpendicular to each other.

[0041] Optionally, each L-shaped metal member 2 may be an integrally formed structure or a spliced ​​structure.

[0042] In some embodiments, the four L-shaped metal pieces 2 are located on the same layer. Exemplarily, the four L-shaped metal pieces 2 are obtained by etching the same metal layer, and each L-shaped metal piece is an integrally formed structure.

[0043] In some embodiments, the four L-shaped metal pieces may be isolated by a dielectric layer. For example, the dielectric layer may be silicon oxide or silicon nitride.

[0044] In the technical solution provided in the embodiment of the present application, the sealing ring structure is designed to be four mutually isolated L-shaped metal parts. In this way, the plasma charge adsorbed on the sealing ring structure cannot gather in one place, but is dispersed on the four mutually isolated L-shaped metal parts, thereby reducing the probability of arc occurrence.

[0045] In addition, the filling of the insulating medium reduces the area of ​​the sealing ring, exposing less metal area, thereby absorbing less plasma charge and reducing the amount of charge, which can further reduce the probability of arc occurrence.

[0046] It should be noted that the sealing ring structure may include multiple metal layers isolated by a dielectric, and each metal layer may include the above four mutually isolated L-shaped metal parts. Optionally, in two adjacent metal layers, the L-shaped metal part located in the upper metal layer and the L-shaped metal part located in the lower metal layer may be electrically connected through a conductive via.

[0047] For the convenience of description, one of any two adjacent L-shaped metal pieces 2 is referred to as a first L-shaped metal piece, and the other is referred to as a second L-shaped metal piece. Figure 2 Taking the L-shaped metal piece 21 (hereinafter referred to as the first L-shaped metal piece) and the L-shaped metal piece 22 (hereinafter referred to as the second L-shaped metal piece) disposed adjacent to each other as an example, the specific structure of the first L-shaped metal piece and the second L-shaped metal piece and the positional relationship therebetween are described in detail. It should be noted that any two adjacent L-shaped metal pieces among the above four L-shaped metal pieces have the structure and positional relationship of the first L-shaped metal piece and the second L-shaped metal piece described below.

[0048] like Figure 2 As shown, the first L-shaped metal part 21 includes a first strip part 211 and a second strip part 212 which are perpendicular to each other, and the second L-shaped metal part 22 includes a third strip part 221 and a fourth strip part 222 which are perpendicular to each other; the extension directions of the first strip part 211 and the third strip part 221 are opposite, and the extension directions of the second strip part 212 and the fourth strip part 222 are the same; there is a first overlapping part in the orthographic projections of the first strip part 211 and the third strip part 221 on the first plane, and the first plane is perpendicular to the extension direction of the first strip part 211.

[0049] The existence of a first overlapping portion between the orthographic projections of the first strip component 211 and the third strip component 221 on the first plane means that a first overlapping portion exists between the orthographic projection of the first strip component 211 and the orthographic projection of the third strip component 221 on the first plane.

[0050] It should be noted that the extension direction of each strip component is from the connecting portion of the strip component to the end of the strip component, and the strip component is connected to the connecting portion of another strip component through its connecting portion to form an L-shaped metal part.

[0051] For example, Figure 2 As shown, the extension direction of the first strip-shaped component 211 is along Figure 2 In the positive direction of the Y axis, the second strip-shaped component 221 extends in the direction Figure 2 The negative Y-axis is shown.

[0052] For example, Figure 2 As shown, the extension direction of the second strip-shaped component 212 is along Figure 2 In the positive direction of the X-axis, the fourth strip-shaped component 222 extends in the direction Figure 2 The positive direction of the X axis is shown.

[0053] In some embodiments, there is a third overlapping area between the orthographic projections of the second strip-shaped component 212 and the fourth strip-shaped component 222 on the second plane, wherein the second plane is perpendicular to the extension direction of the first strip-shaped component.

[0054] The existence of a third overlapping area between the orthographic projections of the second strip component 212 and the fourth strip component 222 on the second plane means that there is a third overlapping portion between the orthographic projection of the second strip component 212 and the orthographic projection of the fourth strip component 222 on the second plane.

[0055] In the embodiment of the present application, there is an overlapping portion between the first strip component 211 and the third strip component 221 (eg Figure 2 The dotted line H in the middle circle) is the existence of this overlapping part, which can effectively prevent Figure 2 The damage to the chip caused by the cutting stress in the positive direction of the X-axis can also effectively prevent the damage caused by the cutting stress along the Figure 2 The water vapor and dust in the positive direction of the X-axis can be removed, thereby reducing the damage of the water vapor and dust to the chip. It should be noted that the orthographic projection of the overlapping portion on the first plane is the first overlapping portion.

[0056] It can be seen that the sealing ring structure provided in the embodiment of the present application not only has good mechanical structural strength, which can effectively reduce the impact of chip cutting stress on the chip, but also has good sealing performance, which can effectively prevent water vapor and dust from entering the interior of the chip.

[0057] In some embodiments, the sum of the first width, the second width and the target spacing is less than or equal to 40um; wherein the first width refers to the width of the first strip component 211 along the extension direction of the second strip component, the second width is the width of the third strip component 221 along the extension direction of the second strip component, and the target spacing refers to the spacing between the first strip component 211 and the third strip component 221 in the extension direction of the second strip component, that is, the width of the gap between the first strip component 211 and the third strip component 221 along the extension direction of the second strip component.

[0058] In some optional embodiments, the distance between the first strip-shaped component and the third strip-shaped component in the extension direction of the second strip-shaped component is less than or equal to 10 um. It should be noted that the smaller the distance, the better the sealing effect.

[0059] In some optional embodiments, the ratio of the width of the first overlapping portion along the extension direction of the first strip-shaped component to the extension length of the first strip-shaped component is greater than or equal to 4%; and / or, the ratio is less than or equal to 25%. It should be noted that the larger the ratio, the better the sealing effect and the anti-cutting stress effect, but the larger the total area of ​​the L-shaped metal part (the larger the area, the more charge is attracted). Therefore, in practical applications, the ratio can be designed by balancing the sealing effect, the anti-cutting stress effect and the total metal area.

[0060] In some embodiments, the four L-shaped metal pieces further include a third L-shaped metal piece. Figure 2 The L-shaped metal piece 23 in FIG. Figure 2 As shown, the third L-shaped metal part 23 includes a fifth strip part 231 and a sixth strip part 232 which are arranged perpendicular to each other; the third L-shaped metal part 23 is adjacent to the first L-shaped metal part 21; the inner side surface 2111 of the first strip part 211 facing the chip functional area 1 is opposite to and spaced from the outer side surface 2211 of the third strip part 221 away from the chip functional area 1; the inner side surface 2311 of the fifth strip part 231 facing the chip functional area 1 is opposite to and spaced from the outer side surface 2121 of the second strip part 212 away from the chip functional area 1; the extension direction of the fifth strip part 231 is opposite to the extension direction of the second strip part 212.

[0061] The sixth strip-shaped component 232 and the first strip-shaped component 211 extend in the same direction.

[0062] The structure provided in the embodiment of the present application can effectively reduce the area occupied by the sealing ring structure and increase the area ratio of the chip functional area.

[0063] In some embodiments, Figure 2 As shown, the inner side 2111 of the first strip component 211 facing the chip functional area 1 and the outer side 2211 of the third strip component 221 away from the chip functional area 1 are opposite and spaced apart. That is to say, although there is an overlapping part between the projections of the first strip component 211 and the third strip component 221 on the first plane, they are still spaced apart, that is, there is a gap between them. Since water vapor and dust will try to enter the chip from all directions, in order to further reduce water vapor and dust from entering the chip through the gap, the following structural design is adopted: Figure 2 As shown, the first L-shaped metal member further includes: a first protrusion 213 located on the inner side surface 2111 of the first strip-shaped member 211 facing the chip functional area 1 , and the first protrusion 213 is spaced apart from the third strip-shaped member 221 .

[0064] like Figure 2 As shown, the first protrusion 213 is located on the forward path of water vapor or dust entering through the gap. The first protrusion 213 can further block the water vapor or dust entering through the gap, thereby reducing the amount of water vapor and dust entering the chip functional area.

[0065] In another embodiment, if Figure 2 As shown, the second L-shaped metal member further includes: a second protrusion 223 located on the outer side surface 2211 of the third strip-shaped member 221 away from the chip functional area 1 , and the second protrusion 223 is spaced apart from the first strip-shaped member 211 .

[0066] like Figure 2 As shown, the second protrusion 223 can effectively block the Figure 2 The water vapor and dust entering the above gap in the negative direction of the Y axis are reduced, thereby reducing the amount of water vapor and dust entering the gap.

[0067] It should be noted that the first protrusion 213 and the second protrusion 223 can be used in combination or alone, and the embodiments of the present application do not specifically limit this. When the first protrusion 213 and the second protrusion 223 are used in combination, the first protrusion 213 and the second protrusion 223 are arranged at intervals. Using the first protrusion 213 alone means that only the first protrusion 213 exists in the semiconductor chip, and the second protrusion 223 does not exist. Using the second protrusion 223 alone means that only the second protrusion 223 exists in the semiconductor chip, and the first protrusion 213 does not exist.

[0068] In one embodiment, if Figure 2As shown, there is no overlap between the orthographic projection of the first protrusion 213 on the first plane and the first overlapped portion. The first overlapped portion refers to the overlapped portion between the orthographic projections of the first strip-shaped component 211 and the third strip-shaped component 221 on the first plane. In other words, the first protrusion 213 is not located in the above-mentioned gap.

[0069] When designing a chip, if the total chip area remains unchanged, it is hoped that the chip functional area is as large as possible, that is, the sealing ring structure is not expected to occupy too much area. Figure 2 As shown, the overlapping portion circled by the dotted line H is the widest part of the sealing ring structure. That is, in order to reduce the width of the sealing ring structure, it is necessary not only to reduce the width of the first strip member 211 along the extension direction of the second strip member and the width of the third strip member 221 along the extension direction of the second strip member, but also to reduce the width (i.e., the spacing) of the gap between the first strip member 211 and the second strip member 221 along the extension direction of the second strip member.

[0070] If the first protrusion 211 is designed in the gap formed between the first strip member 211 and the third strip member 221, the above-mentioned spacing must be increased, which makes the widest part of the sealing ring structure wider. Figure 2 As shown, the first protrusion 213 and / or the second protrusion 223 may be arranged in an area outside the gap. That is, the orthographic projection of the first protrusion 213 on the first plane does not overlap with the first overlapping portion; and / or the orthographic projection of the second protrusion 223 on the first plane does not overlap with the first overlapping portion.

[0071] Optionally, the orthographic projections of the first protrusion 213 and the second protrusion 223 on the second plane have a second overlapping area or a common boundary; the second plane is perpendicular to the extension direction of the first strip-shaped component 211 .

[0072] The existence of a second overlapping area between the orthographic projections of the first protrusion 213 and the second protrusion 223 on the second plane means that a second overlapping area exists between the orthographic projections of the first protrusion 213 and the orthographic projections of the second protrusion 223 on the second plane.

[0073] The orthographic projections of the first protrusion 213 and the second protrusion 223 on the second plane have a common boundary, which means that the orthographic projections of the first protrusion 213 and the orthographic projections of the second protrusion 223 on the second plane have a common boundary.

[0074] In this embodiment, through the cooperation of the first protrusion 213 and the second protrusion 223, water vapor and dust running along the negative direction of the Y-axis can be effectively blocked, and the larger the overlapping area of ​​the projections of the first protrusion 213 and the second protrusion 223, the better the blocking effect.

[0075] In an optional embodiment, the width of the second overlapping area along the extension direction of the second strip-shaped component is equal to the distance between the first strip-shaped component 211 and the third strip-shaped component 221 in the extension direction of the second strip-shaped component. Such a structure has a better blocking effect.

[0076] In an optional embodiment, the orthographic projections of the first protrusion 213 and the second protrusion 223 on the second plane completely overlap, and such a structure not only has a good effect of blocking water vapor and dust, but also can effectively reduce the metal area in the sealing ring structure. The reduction of the metal area in the sealing ring structure helps to reduce the amount of charge adsorbed by the metal in the sealing ring structure, thereby further reducing the probability of arc discharge.

[0077] In some embodiments, Figure 2 As shown, the third L-shaped metal member 23 further includes: a third protrusion 233 located on the inner side surface 2311 of the fifth strip-shaped member 231 facing the chip functional area 1 , and the third protrusion 233 is spaced apart from the second strip-shaped member 212 .

[0078] like Figure 2 As shown, the third protrusion 233 is located on the forward path of water vapor or dust entering through the gap between the second strip part 212 and the fifth strip part 231. The third protrusion 233 can further block the water vapor or dust entering through the gap, thereby reducing the amount of water vapor and dust entering the chip functional area.

[0079] In other embodiments, Figure 2 As shown, the first L-shaped metal member 21 further includes: a fourth protrusion 214 located on an outer side surface 2121 of the second strip-shaped member 212 away from the chip functional area 1 , and the fourth protrusion 214 is spaced apart from the fifth strip-shaped member 231 .

[0080] like Figure 2 As shown, the fourth protrusion 214 can effectively block the Figure 2 The moisture and dust entering the gap between the second strip component 212 and the fifth strip component 231 in the positive direction of the middle X-axis can be reduced, thereby reducing the amount of moisture and dust entering the gap.

[0081] It should be noted that the third protrusion 233 and the fourth protrusion 214 can be used together or alone, and the embodiment of the present application does not specifically limit this. When the third protrusion 233 and the fourth protrusion 214 are used together, the third protrusion 233 and the fourth protrusion 214 are arranged at intervals. Using the third protrusion 233 alone means that the third protrusion 233 exists in the semiconductor chip, and the fourth protrusion 214 does not exist. Using the fourth protrusion 214 alone means that the second protrusion and the fourth protrusion 214 exist in the semiconductor chip, and the third protrusion 233 does not exist.

[0082] In one embodiment, if Figure 2 As shown, the orthographic projection of the third protrusion 233 on the second plane does not overlap with the fourth overlapping portion. The fourth overlapping portion refers to the overlapping portion between the orthographic projections of the second strip component 212 and the fifth strip component 231 on the second plane. In other words, the third protrusion 233 is not located in the gap formed between the second strip component 212 and the fifth strip component 231.

[0083] In one embodiment, if Figure 2 As shown, the orthographic projection of the fourth protrusion 214 on the second plane does not overlap with the fourth overlapping portion. In other words, the fourth protrusion 214 is not located in the gap formed between the second strip component 212 and the fifth strip component 231.

[0084] That is to say, Figure 2 As shown, the third protrusion 233 and / or the fourth protrusion 214 may be disposed in an area outside the above-mentioned gap.

[0085] Optionally, the orthographic projections of the third protrusion 233 and the fourth protrusion 214 on the first plane have a fifth overlapping region or a common boundary.

[0086] The existence of a fifth overlapping region between the orthographic projections of the third protrusion 233 and the fourth protrusion 214 on the first plane means that a fifth overlapping region exists between the orthographic projections of the third protrusion 233 and the fourth protrusion 214 on the first plane.

[0087] The orthographic projections of the third protrusion 233 and the fourth protrusion 214 on the first plane have a common boundary, which means that the orthographic projections of the third protrusion 233 and the fourth protrusion 214 on the first plane have a common boundary.

[0088] In this embodiment, through the cooperation of the third protrusion 233 and the fourth protrusion 214, water vapor and dust running along the positive direction of the X-axis can be effectively blocked, and the larger the overlapping area of ​​the projections of the third protrusion 233 and the fourth protrusion 214, the better the blocking effect.

[0089] In an optional embodiment, the width of the fifth overlapping area along the extension direction of the first strip component 211 is equal to the distance between the second strip component 212 and the fifth strip component 231 in the extension direction of the first strip component 211. Such a structure has a better blocking effect.

[0090] In an optional embodiment, the orthographic projections of the third protrusion 233 and the fourth protrusion 214 on the first plane completely overlap, and such a structure not only has a good effect of blocking water vapor and dust, but also can effectively reduce the metal area in the sealing ring structure. The reduction of the metal area in the sealing ring structure helps to reduce the amount of charge adsorbed by the metal in the sealing ring structure, thereby further reducing the probability of arc discharge.

[0091] In some embodiments, each of the L-shaped metal parts is an integrally formed structure. Figure 2 As shown, taking the first L-shaped metal member 21 as an example, the first strip-shaped member 211 , the second strip-shaped member 212 , the first protrusion 213 and the second protrusion 214 are integrally formed.

[0092] In some embodiments, the four L-shaped metal pieces have the same structure.

[0093] In an exemplary semiconductor chip, the outer frame size of the semiconductor chip is 900um*900um, and the outer frame can be understood as the minimum enclosing frame that can simultaneously surround the four L-shaped metal parts, wherein the length of the two strip parts of each L-shaped metal part is 470um-550um, the length of the protrusion on the side of each strip part along the extension direction of the strip part is 300um-400um, the width of the protrusion on the side of each strip part along the direction perpendicular to the extension direction of the strip part is 5um, and the width of the strip part along the direction perpendicular to its extension direction is 15um.

[0094] It should be noted that Figure 1b and Figure 2 The size ratio between the sealing ring structure and the chip functional area shown is only schematic and not the actual size ratio.

[0095] Figure 3 A method for preparing a semiconductor chip is provided in one embodiment of the present application. Figure 3 As shown, the method includes:

[0096] 301. Provide a substrate.

[0097] 302. Form a chip functional area and a sealing ring structure surrounding the chip functional area on the substrate.

[0098] Wherein, the sealing ring structure comprises: four L-shaped metal parts, the four L-shaped sealing parts are arranged at intervals from each other and form a ring, wherein any two adjacent L-shaped metal parts comprise a first L-shaped metal part and a second L-shaped metal part;

[0099] The first L-shaped metal part includes a first strip component and a second strip component which are arranged perpendicular to each other, and the second L-shaped metal part includes a third strip component and a fourth strip component which are arranged perpendicular to each other; the extension directions of the first strip component and the third strip component are opposite, and the extension directions of the second strip component and the fourth strip component are the same; there is a first overlapping part in the orthographic projections of the first strip component and the third strip component on the first plane, and the first plane is perpendicular to the extension direction of the second strip component.

[0100] In the above 301, the substrate may be a semiconductor substrate or an SOI substrate.

[0101] In the above 302 , a chip functional area and a sealing ring structure surrounding the chip functional area may be formed on the substrate by deposition, patterning and other processes.

[0102] In an optional implementation, a device region may be formed on the substrate, and then a metal interconnection structure and a sealing ring structure surrounding the metal interconnection structure are formed above the device region. The chip functional region includes the device region and the metal interconnection structure located above the device region.

[0103] In some embodiments, the multiple metal layers in the metal interconnect structure correspond one-to-one to the multiple metal layers in the sealing ring structure, and the two corresponding metal layers are located in the same layer. The two metal layers in the same layer can be prepared simultaneously.

[0104] The specific processes of the above-mentioned deposition, patterning and other processes can be set according to actual needs, and the embodiments of the present application do not make specific limitations on this.

[0105] In some embodiments, when the substrate is a semiconductor substrate, a dielectric layer may be first deposited on the semiconductor substrate, and then a semiconductor layer may be deposited on the dielectric layer, and the semiconductor layer may be etched to form a device region.

[0106] In some other embodiments, when the substrate is an SOI substrate, the top silicon layer in the SOI substrate is etched to form a device region.

[0107] In the technical solution provided in the embodiment of the present application, the sealing ring structure is designed to be four mutually isolated L-shaped metal parts, so that the plasma charge adsorbed on the sealing ring structure cannot be gathered in one place, but is dispersed on the four mutually isolated L-shaped metal parts, thereby reducing the probability of arc occurrence. In addition, the four L-shaped metal parts are arranged in sequence to form a ring, and the two strip-shaped parts with opposite extension directions in any two adjacent L-shaped metal parts have overlapping parts in the positive projection of the first plane, that is, although the sealing metal ring is separated into four mutually isolated L-shaped metal parts, the chip functional area in the semiconductor chip can be completely surrounded by the four L-shaped metal parts through the overlapping design. It can be seen that the sealing ring structure provided in the embodiment of the present application not only has good mechanical structural strength, can effectively reduce the impact of chip cutting stress on the chip, but also has good sealing, which can effectively prevent water vapor and dust from entering the chip.

[0108] It should be noted that the specific structure and specific effects of the sealing ring structure involved in the embodiments of the present application can be found in the above Figure 2 The corresponding contents in the structural embodiment shown are not repeated here.

[0109] The present application also provides a computing device, which may include the semiconductor chip involved in the above embodiment.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application is described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents; and these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application. In addition, if two or more features, systems, products, materials and / or methods described herein do not contradict each other, any combination of these features, systems, products, materials and / or methods is included within the scope of the present disclosure.

Claims

1. A semiconductor chip, characterized in that: include: A substrate, wherein the substrate includes a chip functional area and a sealing ring structure surrounding the chip functional area; The sealing ring structure comprises: four L-shaped metal pieces, which are arranged at intervals from each other and form a ring, wherein any two adjacent L-shaped metal pieces comprise a first L-shaped metal piece and a second L-shaped metal piece; The first L-shaped metal member includes a first strip member and a second strip member disposed perpendicularly to each other, and the second L-shaped metal member includes a third strip member and a fourth strip member disposed perpendicularly to each other; The first strip component and the third strip component extend in opposite directions, and the second strip component and the fourth strip component extend in the same direction; There is a first overlapping portion between the orthographic projections of the first strip-shaped component and the third strip-shaped component on a first plane, and the first plane is perpendicular to the extending direction of the second strip-shaped component.

2. The semiconductor chip according to claim 1, characterized in that The inner side surface of the first strip-shaped component facing the chip functional area and the outer side surface of the third strip-shaped component away from the chip functional area are opposite and spaced apart from each other; The first L-shaped metal member further includes: a first protrusion located on the inner side surface of the first strip-shaped component facing the chip functional area, and the first protrusion is spaced apart from the third strip-shaped component.

3. The semiconductor chip according to claim 2, characterized in that The second L-shaped metal member further comprises: a second protrusion located on the outer side of the third strip-shaped member away from the chip functional area; The second protrusion is spaced apart from the first strip-shaped component and the first protrusion.

4. The semiconductor chip according to claim 3, characterized in that The orthographic projection of the first protrusion on the first plane does not overlap with the first overlapping portion; and / or, The orthographic projection of the second protrusion on the first plane has no overlapping portion with the first overlapping portion.

5. The semiconductor chip according to claim 3, characterized in that The orthographic projections of the first protrusion and the second protrusion on the second plane have a second overlapping area or a common boundary; the second plane is perpendicular to the extension direction of the first strip-shaped component.

6. The semiconductor chip according to claim 5, characterized in that The width of the second overlapping area along the extending direction of the second strip-shaped component is equal to the distance between the first strip-shaped component and the third strip-shaped component in the extending direction of the second strip-shaped component.

7. The semiconductor chip according to claim 5, characterized in that The orthographic projections of the first protrusion and the second protrusion on the second plane completely overlap.

8. The semiconductor chip according to any one of claims 1 to 7, characterized in that The sum of the first width, the second width and the target spacing is less than or equal to 40um; Among them, the first width refers to the width of the first strip component along the extension direction of the second strip component, the second width is the width of the third strip component along the extension direction of the second strip component, and the target spacing refers to the spacing between the first strip component and the third strip component in the extension direction of the second strip component.

9. The semiconductor chip according to any one of claims 1 to 7, characterized in that A distance between the first strip-shaped component and the third strip-shaped component in an extending direction of the second strip-shaped component is less than or equal to 10 um.

10. The semiconductor chip according to any one of claims 1 to 7, characterized in that The ratio of the width of the first overlapping portion along the extension direction of the first strip-shaped component to the extension length of the first strip-shaped component is greater than or equal to 4%; and / or, The ratio is less than or equal to 25%.

11. The semiconductor chip according to any one of claims 1 to 7, characterized in that: The four L-shaped metal pieces further include a third L-shaped metal piece, wherein the third L-shaped metal piece includes a fifth strip-shaped piece and a sixth strip-shaped piece which are arranged perpendicular to each other; The third L-shaped metal piece is adjacent to the first L-shaped metal piece; The inner side surface of the first strip-shaped component facing the chip functional area and the outer side surface of the third strip-shaped component away from the chip functional area are opposite and spaced apart from each other; The inner side surface of the fifth strip-shaped component facing the chip functional area is opposite to and spaced from the outer side surface of the second strip-shaped component away from the chip functional area; An extending direction of the fifth strip-shaped component is opposite to an extending direction of the second strip-shaped component.

12. The semiconductor chip according to any one of claims 1 to 7, characterized in that: The semiconductor chip includes a photonic integrated circuit chip.

13. A method for preparing a semiconductor chip, characterized in that: include: providing a substrate; forming a chip functional area and a sealing ring structure surrounding the chip functional area on the substrate; Wherein, the sealing ring structure comprises: four L-shaped metal parts, the four L-shaped sealing parts are arranged at intervals from each other and form a ring, wherein any two adjacent L-shaped metal parts comprise a first L-shaped metal part and a second L-shaped metal part; The first L-shaped metal part includes a first strip component and a second strip component which are arranged perpendicular to each other, and the second L-shaped metal part includes a third strip component and a fourth strip component which are arranged perpendicular to each other; the extension directions of the first strip component and the third strip component are opposite; the orthographic projections of the first strip component and the third strip component on the first plane have a first overlapping part, and the first plane is perpendicular to the extension direction of the second strip component.

14. A computing device, characterized in that include: The semiconductor chip according to any one of claims 1 to 12.

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