Low-temperature ALD (atomic layer deposition) lamination passivation method and equipment for improving performance of crystal silicon slice battery

Abstract

The invention relates to a low-temperature ALD lamination passivation method and equipment for improving the performance of a crystal silicon slice battery, and the method comprises the following steps: providing a silicon-based battery sample with a complete new side section, stacking a plurality of battery pieces in a piece box, and only exposing the side sections in a cavity; at the temperature of 50-140 DEG C, sequentially growing a SiO2 film and an Al2O3 film on the side section of the battery by adopting an ALD technology, and respectively taking the SiO2 film and the Al2O3 film as a first passivation layer and a second passivation layer; and completing side wall passivation and vacuum breaking, and taking out the wafer box carrying the sample for cooling. According to the method, ALD deposition is carried out in a low-temperature environment, so that thermal damage of high temperature to a battery piece is effectively avoided, and the uniformity and the structural stability of a passivation layer are kept; the laminated structure of the SiO2 and Al2O3 films can significantly reduce the recombination effect of minority carriers and improve the passivation effect, thereby improving the open-circuit voltage and conversion efficiency of the cell.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular to a low-temperature ALD stacking passivation method and equipment for improving the performance of crystalline silicon slice cells. Background Art

[0002] Photovoltaic technology is the most promising clean renewable energy. Currently, crystalline silicon cells dominate the photovoltaic field. With the development of technology, half-cell module technology has gradually been widely used in the field of crystalline silicon cells due to its advantages such as reducing losses in the process of cell interconnection and improving power output. When making a half-cell module, the entire cell needs to be divided into one or more pieces by a laser scribing machine. The low current effect brought by cell cutting reduces the risk of hot spots in the module, but the high-power laser scribing process will inevitably cause cutting damage, which will degrade the mechanical and electrical properties of the cell to varying degrees. For example, the microcracks formed by cutting can easily expand during the subsequent processing of the cell, reducing the mechanical strength of the half-cell and increasing the fragmentation rate; the exposed silicon substrate surface will produce a large number of defects and dangling bonds as recombination centers, reducing the carrier life and the conversion efficiency of the cell. According to research, the power loss of a 72-format module corresponding to a 182mm*182mm cell is as high as 5-10W when cut in half.

[0003] Chinese patent literature discloses "a method and device for repairing damage passivation caused by cutting half a solar cell", with the announcement number CN117926227A. The invention uses a plate-type PEALD deposition device to load the sliced ​​cells into multiple carriers. The carriers pass through the preheating chamber, reaction chamber, and annealing chamber in sequence to deposit a first layer of aluminum oxide of 4-20nm and a second layer of aluminum nitride of 5-15nm, ultimately achieving a 0.1%-0.3% increase in the efficiency of the half-cell. This method reduces the loss of the cell caused by laser cutting to a certain extent and improves the efficiency. However, in terms of equipment, this equipment is a time-type ALD, which deposits two materials. The process time is very long, the amount of TMA special gas used is large, and the cost is high. At the same time, the equipment is divided into a preheating chamber, a reaction chamber and an annealing chamber. The battery samples need to be transferred in the three chambers, which can easily cause scratches on the battery cell grid lines, and the entire chamber occupies a large area. The photovoltaic manufacturing industry is currently in a critical period of cost reduction and efficiency improvement. This equipment is difficult to meet the current photovoltaic manufacturing industry's needs for economy and scale. Most importantly, in terms of process, the temperature of crystalline silicon batteries currently on the market combined with laser-assisted sintering is extremely sensitive. Long-term high temperatures above 230°C will lead to an increase in the grid line contact resistance, thereby causing a sharp drop in electrical performance. The invention causes the battery cell to be in a high temperature state for a long time, which inevitably causes performance loss and makes it difficult to increase the side passivation to the optimal level. Summary of the invention

[0004] In view of the above technical problems, the purpose of the present invention is to provide a low-temperature ALD stacking passivation method and equipment for improving the performance of crystalline silicon sliced ​​cells. Through low-temperature deposition and stacking structure, crystalline silicon sliced ​​cells can achieve efficient passivation in a low-temperature environment, maximally compensate for the damage caused by cutting, and improve the conversion efficiency of battery components. ALD deposition in a low-temperature environment effectively avoids thermal damage to the cell sheet at high temperature and maintains the uniformity and structural stability of the passivation layer; SiO 2 and Al 2 O 3 The stacked structure of the thin film can significantly reduce the recombination effect of minority carriers and enhance the passivation effect, thereby increasing the open circuit voltage and conversion efficiency of the battery cell.

[0005] According to one aspect of the present invention, a low-temperature ALD stack passivation method for improving the performance of crystalline silicon slice cells is provided, comprising the following steps:

[0006] Providing silicon-based battery samples with complete new side cut surfaces, stacking multiple battery cells in a cell box, with only the side cut surfaces exposed in the chamber;

[0007] At 50-140℃, ALD technology is used to grow SiO on the side surface of the battery. 2 Thin film and Al 2 O 3 thin films, serving as first and second passivation layers, respectively;

[0008] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0009] In the scheme, a novel stacked passivation is adopted, using positively charged SiO 2 With negatively charged Al 2 O 3 Together they play a passivation role. First, a thin layer of SiO 2 It has excellent compatibility with crystalline silicon, reducing the formation of surface defects. 2 O 3 The negative charge of the film is just at the Al 2 O 3 SiO generated at the interface with crystalline silicon 2 The junction has a high negative charge density, which maximizes the passivation effect, saturates a large number of newly formed dangling bonds caused by laser cutting, and reduces leakage on the side section of the battery.

[0010] Some technical solutions also include the SiO 2 The film surface was subjected to TMA or H 2 O pretreatment to enhance Al 2 O 3 Adhesion of the passivation layer.

[0011] Some technical solutions also include SiO 2 / Al 2 O 3 The stacked structure is subjected to plasma oxidation treatment to eliminate oxygen vacancy defects and enhance the passivation effect.

[0012] Some technical solutions also include heating the side section of the battery to 200-230° C. and keeping it warm for 0-5 minutes to stimulate the field passivation effect of the passivation stack.

[0013] In some technical solutions, the battery is one of TOPCon, HJT, and BC.

[0014] In some technical solutions, SiO 2 During the growth of the film, O 2 and H 2 O is the special gas source, and the flow rate is controlled at 0.1-8slm. In order to reduce the formation of excessive pinholes and maintain SiO 2 The passivation quality of the SiO 2 The thickness is controlled at 1.5-2nm.

[0015] In the scheme, O 2 and H 2 Precise control of the O gas source reduces SiO 2 The pinholes on the surface of the layer are formed to ensure the quality and uniformity of the first passivation layer and improve the passivation effect. 2 The thickness further reduces the recombination of minority carriers, thereby increasing the open circuit voltage.

[0016] In some technical solutions, Al 2 O 3 During the growth of the film, TMA and H 2 O is the special gas source, TMA and H 2 The liquid temperature of O is controlled at 20-40℃, and the second passivation layer Al 2 O 3 The thickness is 30-90nm.

[0017] In some technical solutions, TMA or H 2 The pretreatment cycle of O is 3-10 cycles.

[0018] In the scheme, by optimizing TMA and H 2 O source temperature and Al 2 O 3 The thickness of the layer ensures the consistency of the negative charge density and the stability of the passivation effect. This step improves the Al 2 O 3The potential shielding effect of the layer further improves the open circuit voltage and fill factor of the battery.

[0019] In some technical solutions, the heating rate of all steps is controlled at 5-15°C / min.

[0020] In the scheme, the appropriate heating rate avoids damage to the film structure caused by sudden temperature changes, improves the uniformity and stability of the passivation layer, and thus ensures the mechanical and electrical properties of the battery cell.

[0021] In some technical solutions, the film forming pressure of the first and second passivation layers is 1-6 mbar.

[0022] In some technical solutions, the entire process of heating and heat preservation is carried out in a nitrogen environment, the nitrogen flow rate is 10-50slm, the nitrogen is divided into source nitrogen and dilution nitrogen, the source nitrogen flow rate is 50-300sccm, the dilution nitrogen flow rate is 3-8slm, and the carrier gas pipeline temperature is 40-90°C.

[0023] In some technical solutions, TMA and H 2 The source nitrogen gas for O remained at the same flow rate during the deposition.

[0024] In some technical solutions, the TMA and H 2 The source nitrogen gas of O was varied in flow rate during deposition.

[0025] In some technical solutions, the TMA and H 2 The source nitrogen flow rate of O was divided into multiple stages during deposition.

[0026] The present invention adopts a low-temperature ALD stacking passivation process. The low-temperature deposition plus a short high-temperature process keeps the battery cell in a relatively low temperature environment, avoiding the degradation of battery performance caused by long-term high temperature, and perfectly matches the crystalline silicon cells currently on the market that have undergone laser-assisted sintering.

[0027] The present invention adopts thin layer SiO 2 As the first passivation layer, it has extremely good compatibility with crystalline silicon, reducing the formation of surface defects. 2 With negatively charged Al 2 O 3 Together, they play a dielectric passivation role, forming an effective potential gradient at the interface between the dielectric layer and silicon to repel minority carriers, thereby reducing surface recombination; finally, combined with pre-pass TMA / H 2 O and plasma oxidation treatment methods eliminate oxygen vacancy defects and maximize the dielectric passivation effect; the passivation process of the present invention can increase the power gain of the half-cell module by 5-10W, completely compensating for the damage caused by cutting. The present invention provides a very perfect passivation efficiency improvement solution for the photovoltaic manufacturing industry.

[0028] According to another aspect of the present invention, there is further provided a device applicable to the above-mentioned low-temperature ALD stack passivation method, the device comprising:

[0029] A low-temperature ALD device with a chamber for sequentially growing SiO on the side cut surface of a cell. 2 and Al 2 O 3 film;

[0030] Gas source control device, capable of providing O 2 , H 2 O, TMA gas source and adjust its flow;

[0031] A heating device is used to heat the side section of the battery.

[0032] As a preferred solution, the device also includes a plasma treatment device for treating SiO 2 / Al 2 O 3 The stack is subjected to plasma oxidation treatment to eliminate oxygen vacancy defects; and / or,

[0033] The device is also equipped with a deposition thickness monitoring module to monitor the SiO 2 and Al 2 O 3 Precise control of film thickness; and / or,

[0034] The equipment adopts a spatial ALD device.

[0035] The present invention adopts the above technical solution to have at least the following beneficial effects:

[0036] 1. The present invention performs ALD deposition in a low temperature environment to effectively avoid thermal damage to the cell by high temperature and maintain the uniformity and structural stability of the passivation layer; SiO 2 and Al 2 O 3 The laminated structure of the thin film can significantly reduce the recombination effect of minority carriers and improve the passivation effect, thereby increasing the open circuit voltage and conversion efficiency of the cell;

[0037] 2. The present invention uses low-temperature deposition, laminated structure and short-time high-temperature activation to enable the crystalline silicon sliced ​​battery to achieve efficient passivation in a low-temperature environment, to compensate for the damage caused by cutting to the greatest extent, and to improve the conversion efficiency of the battery assembly; the present invention uses ALD technology to deposit SiO 2 and Al 2 O 3 Thin films, using their interaction to form effective field passivation and potential gradient, reduce minority carrier recombination, and improve open circuit voltage and fill factor;

[0038] 3. The present invention uses TMA or H 2 O pretreatment increases the Al 2 O 3 Thin film on SiO 2 The surface adhesion is improved, interface defects are reduced, and the structural integrity of the passivation layer is ensured; this treatment further enhances the passivation effect, allowing the cell to exhibit higher stability and efficiency under operating conditions;

[0039] 4. The present invention uses plasma oxidation to effectively eliminate SiO 2 / Al 2 O 3 The oxygen vacancy defects at the interface reduce the recombination centers and further improve the passivation effect. This step enables the passivation layer to exhibit excellent electrical properties in long-term use, prolongs the minority carrier lifetime, and increases the open circuit voltage of the battery.

[0040] 5. The short-time high-temperature treatment of the present invention activates the field effect of the passivation layer, increases the potential gradient, and significantly improves the field passivation effect; this step ensures that the battery cell can obtain a better fill factor and open circuit voltage, thereby improving its overall efficiency;

[0041] 6. The present invention uses a low-temperature ALD stacked passivation process to sequentially deposit SiO on the side cut surface of the crystalline silicon sliced ​​cell. 2 and Al 2 O 3 Thin film, combined with TMA / H 2 Optimization steps such as O pretreatment, plasma oxidation treatment and short-time high-temperature activation have effectively improved the electrical performance of the battery; specific performance data show that this process can increase the open-circuit voltage of the half-cell battery module to 1.3-1.8mV, the fill factor is increased by about 0.2%-0.4%, and the final module power gain reaches 5-10W, which significantly compensates for the damage loss caused by laser cutting and provides an efficient and stable passivation improvement solution for photovoltaic cell manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 The present invention is a schematic flow chart of a low-temperature ALD stacking passivation method for improving the performance of crystalline silicon slice cells according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The specific implementation methods of the present invention are described below in conjunction with the accompanying drawings. Obviously, the following embodiments are only some specific implementation methods of the present invention, but not all embodiments. The following exemplary embodiment description is only illustrative and is not a limitation on the present invention and its application or use. Based on the description of the present invention, all other technical solutions obtained by ordinary technicians in the field without creative labor belong to the scope of protection of the present invention.

[0044] This embodiment provides a low-temperature ALD stack passivation method for improving the performance of crystalline silicon slice cells, including: Figure 1 The steps shown are to prove Figure 1 The importance of each process step is demonstrated by designing the experiments shown in Table 1 below, which include 6 embodiments and 7 comparative examples, to prove the reliability of the present method.

[0045] Table 1. Experimental parameters of various embodiments and comparative examples

[0046]

[0047] This experiment uniformly uses a whole piece of 26.4% 182mm*182mm TopCon battery as a sample. After non-destructive laser cutting, each group of experiments has 1500 half pieces. IV test is carried out before the experiment and then after the experiment. After the test is completed, 10 72-format components are prepared in each group.

[0048] Example 1

[0049] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0050] The battery side section was heated to 140°C at a heating rate of 10°C / min;

[0051] Using low temperature ALD technology to grow 2nm SiO on the side cut surface 2 film;

[0052] In SiO 2 The film was pretreated with TMA for 5 cycles;

[0053] Using low temperature ALD technology to grow 60nm Al on the side cut surface 2 O 3 The film acts as a second passivation layer;

[0054] The side cut surface is plasma oxidized to remove SiO 2 / Al 2 O 3 Oxygen vacancy defects in the stack improve its passivation performance;

[0055] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0056] Example 2

[0057] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0058] The battery side section was heated to 140°C at a heating rate of 10°C / min;

[0059] Using low temperature ALD technology to grow 2nm SiO on the side cut surface 2 film;

[0060] Using low temperature ALD technology to grow 60nm Al on the side cut surface 2 O 3 The film acts as a second passivation layer;

[0061] The side cut surface is plasma oxidized to remove SiO 2 / Al 2 O 3 Oxygen vacancy defects in the stack improve its passivation performance;

[0062] The battery side section was heated to 230°C at a heating rate of 10°C / min and kept at this temperature for 1 min.

[0063] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0064] Example 3

[0065] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0066] The battery side section was heated to 140°C at a heating rate of 10°C / min;

[0067] Using low temperature ALD technology to grow 2nm SiO on the side cut surface 2 film;

[0068] In SiO 2 The film was pretreated with TMA for 5 cycles;

[0069] Using low temperature ALD technology to grow 60nm Al on the side cut surface 2 O 3 The film acts as a second passivation layer;

[0070] The battery side section was heated to 230°C at a heating rate of 10°C / min and kept at this temperature for 1 min.

[0071] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0072] Example 4

[0073] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0074] The battery side section was heated to 50°C at a heating rate of 10°C / min;

[0075] Using low temperature ALD technology to grow 2nm SiO on the side cut surface 2 film;

[0076] In SiO 2 The film was pretreated with TMA for 5 cycles;

[0077] Using low temperature ALD technology to grow 60nm Al on the side cut surface 2 O 3 The film acts as a second passivation layer;

[0078] The side cut surface is plasma oxidized to remove SiO 2 / Al 2 O 3 Oxygen vacancy defects in the stack improve its passivation performance;

[0079] The battery side section was heated to 230°C at a heating rate of 10°C / min and kept at this temperature for 1 min.

[0080] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0081] Example 5

[0082] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0083] The battery side section was heated to 90°C at a heating rate of 10°C / min;

[0084] Using low temperature ALD technology to grow 2nm SiO on the side cut surface 2 film;

[0085] In SiO 2 The film was pretreated with TMA for 5 cycles;

[0086] Using low temperature ALD technology to grow 60nm Al on the side cut surface 2 O 3 The film acts as a second passivation layer;

[0087] The side cut surface is plasma oxidized to remove SiO 2 / Al 2 O 3 Oxygen vacancy defects in the stack improve its passivation performance;

[0088] The battery side section was heated to 230°C at a heating rate of 10°C / min and kept at this temperature for 1 min.

[0089] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0090] Example 6

[0091] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0092] The battery side section was heated to 140°C at a heating rate of 10°C / min;

[0093] Using low temperature ALD technology to grow 2nm SiO on the side cut surface 2 film;

[0094] In SiO 2 The film was pretreated with TMA for 5 cycles;

[0095] Using low temperature ALD technology to grow 60nm Al on the side cut surface 2 O 3 The film acts as a second passivation layer;

[0096] The side cut surface is plasma oxidized to remove SiO 2 / Al 2 O 3 Oxygen vacancy defects in the stack improve its passivation performance;

[0097] The battery side section was heated to 230°C at a heating rate of 10°C / min and kept at this temperature for 1 min.

[0098] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0099] Comparative Example 1

[0100] This example serves as a basic control group, without any process, to exclude the influence of the IV tester and component-side equipment.

[0101] Comparative Example 2

[0102] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0103] The battery side section was heated to 140°C at a heating rate of 10°C / min;

[0104] The battery side section was heated to 230°C at a heating rate of 10°C / min;

[0105] Keep the same process time as other experiments;

[0106] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0107] Comparative Example 3

[0108] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0109] The battery side section was heated to 230°C at a heating rate of 10°C / min;

[0110] Keep the same process holding time as other experiments;

[0111] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0112] Comparative Example 4

[0113] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0114] The battery side section was heated to 140°C at a heating rate of 15°C / min;

[0115] Keep the same process holding time as other experiments;

[0116] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0117] Comparative Example 5

[0118] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0119] The battery side section was heated to 140°C at a heating rate of 20°C / min;

[0120] Keep the same process holding time as other experiments;

[0121] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0122] Comparative Example 6

[0123] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0124] The battery side section was heated to 140°C at a heating rate of 25°C / min;

[0125] Keep the same process holding time as other experiments;

[0126] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0127] Comparative Example 7

[0128] Provide silicon-based battery samples with complete new side cuts, multiple battery cells are stacked and placed in a cell box, with only the side cuts exposed in the chamber;

[0129] The battery side section was heated to 140°C at a heating rate of 10°C / min;

[0130] Using low temperature ALD technology to grow 2nm SiO on the side cut surface 2 film;

[0131] The battery side section was heated to 230°C at a heating rate of 10°C / min and kept at this temperature for 1 min.

[0132] After the sidewall passivation is completed, the vacuum is broken and the wafer box carrying the sample is taken out and cooled down.

[0133] The test results are shown in Table 1:

[0134] Table 1. Electrical performance improvement results of Examples 1 to 6 and Comparative Examples 1 to 7

[0135] ΔEta(%) ΔVoc(mV) ΔFF(%) ΔRs(Ω) ΔRsh(Ω) ΔPmax(W) Comparative Example 1 0.003 0.3 0.005 0.00005 -15 Comparative Example 2 0.005 0.2 0.002 0.00003 -14 0.2 Comparative Example 3 -0.002 0.1 -0.014 0.00028 -25 -0.5 Comparative Example 4 -0.013 0.3 -0.025 0.00025 -38 -1.2 Comparative Example 5 -0.043 0.2 -0.182 0.00084 -32 -2.7 Comparative Example 6 -0.104 0.2 -0.241 0.00154 -28 -2.8 Comparative Example 7 0.013 0.6 0.056 0.00003 21 0.8 Example 1 0.156 1.3 0.219 0.00005 254 3.5 Example 2 0.168 1.6 0.206 0.00002 198 3.2 Example 3 0.162 1.5 0.256 0.00005 375 4.3 Example 4 0.052 0.5 0.093 0.00004 89 1.3 Example 5 0.085 0.6 0.138 0.00006 108 2.6 Example 6 0.195 1.8 0.379 0.00004 467 6.9

[0136] Note: Eta is conversion efficiency, in %, Voc is open circuit voltage, in mV, FF is fill factor, in %, Rs is series resistance, in Ω, Rsh is parallel resistance, in Ω, Pmax is component power, in W. All IV data above are the differences before and after the experiment. The comparison group of all component powers is Comparative Example 1.

[0137] As can be seen from Table 1, the IV electrical properties and component power of Example 6 are the most improved, and the efficiency improvement value is basically equivalent to the cutting damage value. Specific analysis: Except for the steps related to coating, Example 2 is exactly the same as Example 6, indicating that the electrical performance gain of Example 4 is all due to the laminated passivation process of the present invention; Example 3 performed the same process time as other groups at 230°C, but the electrical performance showed a downward trend, indicating that the printed TOPCon battery cannot be in a high temperature environment for a long time, because of the particularity of LECO slurry, its temperature sensitivity increases, resulting in reduced heat resistance of the battery; For Examples 4-6, as the heating rate increases, the performance of the battery cell decays more and more seriously, which is mainly reflected in the increase of Rs and the damage to the grid line contact. The heating rate is controlled below 15°C / min to ensure that the performance of the battery cell itself will not decay. The reason may be that the thermal conductivity of silver, aluminum, and silicon is different, and the excessive heating causes pinhole-like gaps inside, thereby increasing the contact resistance; For Example 7, only SiO 2The passivation of the battery is shown in Figure 6, Rsh is improved, leakage current is reduced, and there is a certain passivation effect but it is not outstanding. Compared with Example 6, Examples 1-3 respectively reflect the importance of short-term high-temperature excitation, TMA pretreatment and plasma oxidation, which are crucial to make up for the passivation defects and enhance the passivation effect. Examples 4-5 respectively reflect the difference between 50°C deposition and 90°C deposition. From the results, when passivated at a lower temperature, the battery performance has only a small gain, and a good passivation effect cannot be stimulated if the temperature is too low.

[0138] In summary, the present invention uses low-temperature coating and short-term high-temperature annealing process to avoid the performance loss of the battery caused by long-term high temperature. On this basis, combined with SiO 2 / Al 2 O 3 Multilayer passivation, TMA / H 2 O pretreatment and plasma oxidation eliminate a large number of oxygen vacancy defects, maximize the dielectric passivation effect, improve the open circuit voltage and parallel resistance, make the component power gain 5-10W, and completely compensate for the damage caused by cutting. The present invention provides a very perfect passivation efficiency improvement solution for the photovoltaic manufacturing industry.

[0139] Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

Claims

1. A low-temperature ALD stack passivation method for improving the performance of crystalline silicon slice cells, characterized in that: The following steps are involved: Providing silicon-based battery samples with complete new side cut surfaces, stacking multiple battery cells in a cell box, with only the side cut surfaces exposed in the chamber; At 50-140°C, ALD technology is used to sequentially grow SiO2 film and Al2O3 film on the side surface of the battery as the first and second passivation layers, respectively; After the sidewall passivation is completed, the vacuum is broken and the cassette carrying the sample is taken out and cooled down.

2. The low temperature ALD stack passivation method according to claim 1, characterized in that: The method also includes pre-treating the surface of the SiO2 film with TMA or H2O to enhance the adhesion of the Al2O3 passivation layer.

3. The low temperature ALD stack passivation method according to claim 1, characterized in that: The method also includes plasma oxidation treatment of the SiO2 / Al2O3 stacked structure to eliminate oxygen vacancy defects and enhance the passivation effect.

4. The low temperature ALD stack passivation method according to claim 1, characterized in that: The method also includes heating the side section of the battery to 200-230° C. and keeping the temperature for 0-5 minutes to stimulate the field passivation effect of the passivation stack.

5. The low temperature ALD stack passivation method according to any one of claims 1 to 4, characterized in that: The battery is one of TOPCon, HJT and BC.

6. The low temperature ALD stack passivation method according to claim 1, characterized in that: During the growth of SiO2 film, O2 and H2O are used as special gas sources, the flow rate is controlled at 0.1-8slm, and the SiO2 thickness is controlled at 1.5-2nm to reduce the formation of pinholes and ensure the passivation quality.

7. The low temperature ALD stack passivation method according to claim 1, characterized in that: During the growth of the Al2O3 film, TMA and H2O are used as special gas sources, the liquid temperature of TMA and H2O is controlled at 20-40°C, and the thickness of the second passivation layer Al2O3 is 30-90nm.

8. The low temperature ALD stack passivation method according to claim 1 or 4, characterized in that: The heating rate of all steps was controlled at 5-15°C / min.

9. An apparatus suitable for the low-temperature ALD stack passivation method according to any one of claims 1 to 8, characterized in that: The device comprises: A low-temperature ALD device with a chamber for sequentially growing SiO2 and Al2O3 films on the side cut surface of the cell; Gas source control device, capable of providing O2, H2O, TMA gas sources and adjusting their flow rates; A heating device is used to heat the side section of the battery.

10. The device according to claim 9, characterized in that The device also includes a plasma treatment device for performing plasma oxidation treatment on the SiO2 / Al2O3 stack to eliminate oxygen vacancy defects; and / or, The device is also equipped with a deposition thickness monitoring module to achieve precise control of the thickness of SiO2 and Al2O3 films; and / or, The equipment adopts a spatial ALD device.

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