Display device

Abstract

A display device is provided. The display device includes: a substrate including a display area and an intermediate area; a light emitting element on the display area and including a pixel electrode, an emission layer, and a common electrode; an edge structure on the intermediate region and including a lower metal stack and an upper metal stack; and a first inorganic encapsulation film on the light emitting element and the edge structure. The lower metal stack includes a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer. The upper metal stack includes a fourth sub-metal layer and a fifth sub-metal layer. The width of the first sub-metal layer is larger than that of the third sub-metal layer, the width of the third sub-metal layer is larger than that of the second sub-metal layer, and the width of the fifth sub-metal layer is larger than that of the fourth sub-metal layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0106075 filed in the Korean Intellectual Property Office on August 14, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device. Background Art

[0004] With the development of information-oriented society, various demands on display devices are increasing. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among such flat panel display devices, a light emitting display device includes a light emitting element that can emit light by itself so that each of the pixels of the display panel can emit light by itself. Accordingly, the light emitting display device can display an image without a backlight unit that supplies light to the display panel.

[0005] For example, a display device includes a display area that displays an image and a non-display area around the display area. Recently, the width of the non-display area has been continuously reduced in order to allow viewers to be more immersed in the content displayed on the display area and to increase the aesthetics of the display device.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] The display device may include a through hole in which one or more optical devices (such as a camera) are disposed. A non-display area around (eg, adjacent to) the through hole may block moisture from penetrating into the display area.

[0008] One or more embodiments of the present disclosure are directed to a display device having high brightness while blocking moisture.

[0009] However, the aspects and features of the present disclosure are not limited thereto, and other aspects and features of the present disclosure will be apparent to those of ordinary skill in the art through the following description.

[0010] According to one or more embodiments of the present disclosure, a display device includes a substrate, a light-emitting element, an edge structure, and a first inorganic encapsulation film, the substrate including a display area surrounding a through hole, and an intermediate area between the through hole and the display area, the light-emitting element is on the display area of ​​the substrate and includes a pixel electrode, an emission layer on the pixel electrode, and a common electrode on the emission layer, the edge structure is on the intermediate area of ​​the substrate and includes a lower metal stack and an upper metal stack, and the first inorganic encapsulation film is on the light-emitting element and the edge structure. The lower metal stack includes a first sub-metal layer, a second sub-metal layer on the first sub-metal layer, and a third sub-metal layer on the second sub-metal layer. The upper metal stack is on the lower metal stack and includes a fourth sub-metal layer on the third sub-metal layer, and a fifth sub-metal layer on the fourth sub-metal layer. The width of the first sub-metal layer is greater than the width of the third sub-metal layer, the width of the third sub-metal layer is greater than the width of the second sub-metal layer, and the width of the fifth sub-metal layer is greater than the width of the fourth sub-metal layer.

[0011] In embodiments, the edge structure may include an inorganic layer between the lower metal stack and the upper metal stack, and a width of the inorganic layer may be greater than or equal to a width of the third sub-metal layer.

[0012] In embodiments, the width of the fourth sub-metal layer may be greater than the width of the second sub-metal layer.

[0013] In an embodiment, the thickness of the fourth sub-metal layer may be greater than the thickness of the fifth sub-metal layer.

[0014] In an embodiment, the display device may further include a pixel defining layer on the display area of ​​the substrate and exposing at least a portion of the pixel electrode, a first bank layer on the pixel defining layer, and a second bank layer on the first bank layer and including a side surface protruding from a side surface of the first bank layer. The first bank layer may include the same material as that of the fourth sub-metal layer, and the second bank layer may include the same material as that of the fifth sub-metal layer.

[0015] In an embodiment, the display device may further include a pixel defining layer on the display area of ​​the substrate and exposing at least a portion of the pixel electrode, and the inorganic layer may include the same material as that of the pixel defining layer.

[0016] In an embodiment, the display device may further include a thin film transistor, which is between the substrate and the light emitting element in the display area and includes a semiconductor layer, a source electrode, a drain electrode and a gate electrode. The source electrode and the drain electrode may include: a layer including the same material as the material of the first sub-metal layer, a layer including the same material as the material of the second sub-metal layer, and a layer including the same material as the material of the third sub-metal layer.

[0017] In an embodiment, the display device may further include an organic encapsulation film on the first inorganic encapsulation film, a second inorganic encapsulation film on the organic encapsulation film, and a first dam between the substrate and the first inorganic encapsulation film in the intermediate region. The first dam may include a first side surface facing the through hole, and a second side surface opposite to the first side surface. The first inorganic encapsulation film and the second inorganic encapsulation film may contact each other on the first side surface of the first dam.

[0018] In embodiments, the organic encapsulation film may be on the second side surface of the first dam.

[0019] In an embodiment, the edge structure may be between the first dam and the through hole.

[0020] In embodiments, the edge structure may overlap the organic encapsulation film in a thickness direction of the substrate.

[0021] In an embodiment, the first sub-metal layer, the third sub-metal layer, and the fifth sub-metal layer may include titanium (Ti), and the second sub-metal layer and the fourth sub-metal layer may include aluminum (Al).

[0022] In an embodiment, the common electrode may contact a side surface of the first bank layer.

[0023] In an embodiment, a maximum vertical distance from the substrate to the common electrode may be smaller than a maximum vertical distance from the substrate to the second bank layer.

[0024] In an embodiment, the display device may further include an organic pattern on the second bank layer and including the same material as the emission layer, and an electrode pattern on the organic pattern and including the same material as the common electrode. The emission layer and the organic pattern may be spaced apart from each other, and the common electrode and the electrode pattern may be spaced apart from each other.

[0025] In an embodiment, the substrate may include an inclined surface toward the through hole.

[0026] In an embodiment, the display device may further include an optical device positioned in the through hole.

[0027] According to one or more embodiments of the present disclosure, a display device includes a substrate, a light-emitting element, an edge structure, and a first inorganic encapsulation film, wherein the substrate includes a display area surrounding a through hole, and an intermediate area between the through hole and the display area, the light-emitting element is on the display area of ​​the substrate and includes a pixel electrode, an emission layer on the pixel electrode, and a common electrode on the emission layer, the edge structure is on the intermediate area of ​​the substrate and includes a lower metal stack and an upper metal stack, and the first inorganic encapsulation film is on the light-emitting element and the edge structure. The lower metal stack includes a first sub-metal layer, a second sub-metal layer on the first sub-metal layer, and a third sub-metal layer on the second sub-metal layer. The upper metal stack is on the lower metal stack and includes a fourth sub-metal layer on the third sub-metal layer, and a fifth sub-metal layer on the fourth sub-metal layer. The thickness of the fourth sub-metal layer is greater than the thickness of the fifth sub-metal layer. The first inorganic encapsulation film contacts the lower surface of the third sub-metal layer, and the lower surface and upper surface of the fifth sub-metal layer.

[0028] In embodiments, the edge structure may include an inorganic layer between the lower metal stack and the upper metal stack, and a width of the inorganic layer may be greater than or equal to a width of the third sub-metal layer.

[0029] In embodiments, a width of the first sub-metal layer may be greater than a width of the third sub-metal layer, and a width of the fourth sub-metal layer may be greater than a width of the second sub-metal layer.

[0030] According to one or more embodiments of the present disclosure, a display device may include a structure in which two tip structures are stacked on each other around (eg, adjacent to) a through hole, so that penetration of moisture may be effectively blocked and brightness may be increased.

[0031] However, the present disclosure is not limited to the above-mentioned aspects and features. Additional aspects and features will be partially set forth in the following description with reference to the drawings, and in part may be apparent from the description and drawings, or may be learned by practicing one or more of the presented embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure;

[0034] Figure 2 is a plan view showing a display panel according to an embodiment of the present disclosure;

[0035] Figure 3 is shown along Figure 1A cross-sectional view of an example of a display device taken along line II';

[0036] Figure 4 It shows that when the circuit board is bent Figure 3 A cross-sectional view of an example of a display device;

[0037] Figure 5 is a cross-sectional view showing a display area of ​​a display device according to an embodiment of the present disclosure;

[0038] Figure 6 is a cross-sectional view showing a display area of ​​a display device according to an embodiment of the present disclosure;

[0039] Figure 7 It is shown Figure 6 An enlarged cross-sectional view of area A1;

[0040] Figure 8 yes Figure 2 An enlarged plan view of region II;

[0041] Fig. 9 is shown along Figure 8 A cross-sectional view of an example of a display panel taken along line III-III';

[0042] Fig.10 It is shown Fig. 9 An enlarged cross-sectional view of an example of area A2;

[0043] Fig.11 It is shown Fig. 9 An enlarged cross-sectional view of another example of area A2;

[0044] Figure 12 to Figure 14 It is shown Fig.10 and Fig.11 An enlarged cross-sectional view of an example of area A3; and

[0045] Figures 15 to 19 2 is a cross-sectional view showing sequential processes of a method for manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always refer to the same elements. However, the present disclosure can be implemented in various forms and should not be construed as being limited only to the embodiments shown in this article. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the present disclosure will be fully conveyed to those skilled in the art. Accordingly, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, the same reference numerals represent the same elements throughout the drawings and written descriptions, and therefore their redundant descriptions may not be repeated.

[0047] When a specific embodiment can be implemented in different ways, the specific process order may be different from the described order. For example, two processes described in succession may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0048] In the accompanying drawings, for the sake of clarity, the relative size, thickness and ratio of elements, layers and regions can be exaggerated and / or simplified. Such as "beneath", "below", "lower", "under", "above", "upper" and similar spatial relative terms can be used in this article for the convenience of explanation, to describe the relationship between an element or feature and another (some) element or feature as shown in each figure. It should be understood that, in addition to the orientations depicted in each figure, spatial relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in each figure is turned over, the element described as "below" or "below" or "below" of other elements or features will be subsequently oriented to "above" of other elements or features. Therefore, the example terms "below" and "below" can include both the orientations of the top and bottom. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0049] In each figure, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0050] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part.

[0051] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to another element or layer, or there may be intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, and / or can be indirectly electrically connected with one or more intervening layers, regions, or elements therebetween. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0052] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless otherwise clearly indicated in the context, the singular forms "a" and "an" as used herein are also intended to include plural forms. It should also be understood that when the terms "comprise", "comprising", "include", "including", "has", "have" and "having" are used in this specification, the existence of the stated features, wholes, steps, operations, elements and / or parts is specified, but the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their clusters is not excluded. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the statement "A and / or B" means A, B, or A and B. When a statement such as "at least one of..." is after a column of elements, the entire column of elements is modified without modifying the individual elements in the column. For example, the expressions "at least one of a, b, and c" and "at least one selected from the cluster consisting of a, b, and c" indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0053] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0055] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure. Figure 2 is a plan view showing a display panel according to an embodiment of the present disclosure.

[0056] Reference Figure 1 According to an embodiment of the present disclosure, the display device 10 is a device for displaying moving images and / or still images. The display device 10 can be used as a display screen of various suitable portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs)) and a display screen of various suitable products (such as televisions, notebooks, monitors, billboards, and Internet of Things (IoT) devices).

[0057] According to an embodiment of the present disclosure, the display device 10 may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro-LED display device using a micro-light-emitting diode or a nano-light-emitting diode (micro-LED or nano-LED). Hereinafter, for the convenience of explanation, the display device 10 will be described in more detail in the context of an organic light-emitting display device as a representative example. However, it should be understood that the present disclosure is not limited thereto.

[0058] The display device 10 according to the embodiment may include a display panel 100 , a display driver 200 , and a circuit board 300 .

[0059] The display panel 100 may be formed as a rectangular plane having a long side extending in a first direction (e.g., an X-axis direction) and a short side extending in a second direction (e.g., a Y-axis direction) crossing or intersecting the first direction (e.g., the X-axis direction). Each of the corners where the long side extending in the first direction (e.g., the X-axis direction) and the short side extending in the second direction (e.g., the Y-axis direction) intersect may be formed as a right angle or may be rounded with a curvature. The shape of the display panel 100 when viewed from the top (e.g., in a plan view) is not limited to a quadrilateral shape, and may be formed in a polygonal shape different from a quadrilateral, a circular shape, or an elliptical shape.

[0060] The display panel 100 may be formed to be flat or substantially flat, but the present disclosure is not limited thereto. For example, the display panel 100 may be formed at the left and right ends and may include a bent portion having a constant curvature or a variable curvature. In addition, the display panel 100 may be flexible so that it can be bent, curved, folded, or rolled.

[0061] The display panel 100 may include a display area DA in which an image is displayed and a non-display area NDA in which an image is not displayed. Accordingly, a layer or component (e.g., a substrate) of the display panel 100 may also include an area corresponding to an area of ​​the display panel 100, such as the display area DA and an intermediate area MA described below.

[0062] The display area DA may occupy most of the area of ​​the display panel 100. The display area DA may be disposed at the center of the display panel 100. A plurality of pixels may be disposed in the display area DA to display an image, each pixel including a plurality of emission areas.

[0063] The non-display area NDA may include an intermediate area MA and a first non-display area NDA1. The display area DA may surround the intermediate area MA and the through hole TH (e.g., around the periphery of the intermediate area MA and the through hole TH). The intermediate area MA may surround the through hole TH (e.g., around the periphery of the through hole TH) and may be positioned between the display area DA and the through hole TH. The through hole TH may be a hole that allows light to be transmitted therethrough, and may be a hole in which the optical device OPD (e.g., see Figure 3 ) area.

[0064] The first non-display area NDA1 may be disposed adjacent to the display area DA. The first non-display area NDA1 may be on the outside of the display area DA. The first non-display area NDA1 may be disposed to surround the display area DA (e.g., around the periphery of the display area DA). The first non-display area NDA1 may be an edge area of ​​the display panel 100.

[0065] Reference Figure 1 and Figure 2 , the first non-display area NDA1 may include a display pad PD, a display driver 200 , and a circuit board 300 .

[0066] The display pad PD may be disposed at one edge of the display panel 100. For example, the display pad PD may be disposed at a lower edge of the display panel 100. The display pad PD may be connected to the display driver 200 and the circuit board 300.

[0067] The display driver 200 may generate and output signals and voltages for driving the display panel 100. In more detail, the display driver 200 may generate and output data voltages, power supply voltages, scan timing signals, gate control signals, and the like. The display driver 200 may apply a power supply voltage to a voltage line, and may supply a gate control signal to a gate driver.

[0068] The display driver 200 may be disposed between the display pad PD and the display area DA in the first non-display area NDA1. The display driver 200 may be attached to the first non-display area NDA1 of the display panel 100 by a chip on glass (COG) technology. As another example, the display driver 200 may be attached to the circuit board 300 by a chip on plastic (COP) technology.

[0069] The circuit board 300 may be disposed on a display pad PD disposed at one edge of the display panel 100. The circuit board 300 may be attached to the display pad PD using a conductive adhesive member such as an anisotropic conductive film and / or an anisotropic conductive adhesive. Accordingly, the circuit board 300 may be electrically connected to a signal line of the display panel 100. The circuit board 300 may be a flexible printed circuit board or a flexible film such as a chip on film.

[0070] The bending area may be positioned between the display driver 200 and the display area DA in the first non-display area NDA1. The bending area may be bent so that the display driver 200 and the circuit board 300 are disposed below the display panel 100. The display driver 200 and the circuit board 300 bent at the bending area may overlap the display area DA in a third direction (e.g., Z-axis direction).

[0071] Figure 3 is shown along Figure 1 A cross-sectional view of an example of a display device taken along line II'. Figure 4 It shows that when the circuit board is bent Figure 3 A cross-sectional view of an example of a display device.

[0072] Reference Figure 3The display device 10 according to the embodiment may include a display panel 100, a polarizing film PF, a cover window CW and a panel bottom cover PB. The display panel 100 may include: a substrate SUB, a thin film transistor layer TFTL and an emission material layer EML (for example, see Figure 5 )'s display layer DISL, thin film encapsulation layer ENC, touch sensor layer SENL and organic planarization layer ORL.

[0073] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded or rolled. For example, the substrate SUB may include, but is not limited to, a polymer resin such as polyimide (PI). According to another embodiment, the substrate SUB may include a glass material or a metal material.

[0074] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors. Each of the plurality of thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode.

[0075] The emission material layer EML may be disposed on the thin film transistor layer TFTL. The emission material layer EML may include a plurality of light emitting elements and a pixel defining layer for defining pixels, each light emitting element including a pixel electrode, a common electrode and an emission layer to emit light. A plurality of light emitting elements may be disposed in the display area DA.

[0076] The thin film encapsulation layer ENC may be disposed on the emission material layer EML. The thin film encapsulation layer ENC may cover the upper surface and the side surface of the emission material layer EML so as to prevent or substantially prevent oxygen and / or moisture from penetrating into the emission material layer EML. The thin film encapsulation layer ENC may include at least one inorganic film and at least one organic film.

[0077] The touch sensor layer SENL may be disposed on the thin film encapsulation layer ENC. The touch sensor layer SENL may include sensor electrodes. The touch sensor layer SENL may sense a user's touch using the sensor electrodes.

[0078] The polarizing film PF may be disposed on the touch sensor layer SENL. The polarizing film PF may be disposed on the display panel 100 so as to reduce reflection of external light. The polarizing film PF may include a first base member, a linear polarizer, a retardation film (such as a quarter wavelength (λ / 4) plate), and a second base member. The first base member, the retardation film, the linear polarizer, and the second base member of the polarizing film PF may be sequentially stacked on the display panel 100.

[0079] The cover window CW may be disposed on the polarizing film PF. The cover window CW may be attached to the polarizing film PF by a transparent adhesive member such as an optically clear adhesive (OCA) film.

[0080] The panel bottom cover PB may be disposed on the lower surface of the substrate SUB. The lower surface of the substrate SUB may be opposite to the upper surface. In other words, the lower surface of the substrate SUB may be opposite to the surface at which the thin film transistor layer TFTL, the emission material layer EML, the thin film encapsulation layer ENC, and the touch sensor layer SENL are positioned. The panel bottom cover PB may be attached to the lower surface of the substrate SUB by an adhesive member. The adhesive member may be a pressure sensitive adhesive (PSA).

[0081] The panel cover bottom PB may include at least one of a light blocking member for absorbing light incident from the outside, a buffer member for absorbing external impact, and a heat dissipation member for effectively dissipating heat.

[0082] The display device 10 may further include an optical device OPD. The optical device OPD may output or receive light in the infrared, ultraviolet, and / or visible ranges. For example, the optical device OPD may be an optical sensor that senses light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, and / or an image sensor.

[0083] The optical device OPD may be disposed in the through hole TH. The through hole TH may allow light to pass therethrough, and may be a physical hole that penetrates through the panel bottom cover PB, the display panel 100, and the polarizing film PF. However, the present disclosure is not limited thereto. For example, the through hole TH may penetrate through the panel bottom cover PB, but may not penetrate through the display panel 100 or the polarizing film PF. The cover window CW may be disposed to cover the through hole TH.

[0084] Reference Figure 4 , the display driver 200 and the circuit board 300 may be bent so that they may be positioned below the display panel 100. The circuit board 300 may be attached to the lower surface of the panel cover bottom PB by an adhesive member 310. The adhesive member 310 may be a pressure sensitive adhesive.

[0085] Figure 5 is a cross-sectional view showing a display area of ​​a display device according to an embodiment of the present disclosure. Figure 6 is a cross-sectional view showing a display area of ​​a display device according to an embodiment of the present disclosure.

[0086] Reference Figure 5 , the display panel 100 according to the embodiment may be a light emitting display panel including light emitting elements ED1 and ED2 each including an emission layer EL. Figure 5 The emission layer EL and / or the common electrode CE may be formed not only where they overlap with the pixel electrodes AE1 and AE2 but also where they do not overlap with the pixel electrodes AE1 and AE2.

[0087] Reference Figure 6, the display panel 100 according to the embodiment may be a light-emitting display panel including light-emitting elements ED1, ED2, and ED3 including emission layers EL1, EL2, and EL3 spaced apart from each other. Figure 5 The common electrode CE is shown to extend continuously in the display area DA, but Figure 6 The emission layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 may be separated from each other and may be formed in the opening defined by the bank structure BNS.

[0088] The display device 10 may include a plurality of emission areas EA1, EA2, and EA3 arranged in the display area DA. The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors from each other (hereinafter, for the convenience of explanation, the emission area EAn and the nth emission area EAn indicate the same features and are not particularly distinguished in the description). The first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit red light, green light, and blue light, respectively. The color of the light emitted from the emission areas EA1, EA2, and EA3 may be determined according to the light emitting elements ED1, ED2, and ED3 (for example, see Figure 6 ), which will be described in more detail below. For example, the first emission area EA1 may output a red first light, the second emission area EA2 may output a green second light, and the third emission area EA3 may output a blue third light. However, the present disclosure is not limited thereto.

[0089] Each of the first, second, and third emission areas EA1, EA2, and EA3 may be defined by a corresponding opening defined by the pixel defining layer PDL or a corresponding opening defined by the bank structure BNS, which will be described in more detail below.

[0090] In the display device 10, one first emission area EA1, two second emission areas EA2, and one third emission area EA3 disposed adjacent to each other may form a single pixel group. A single pixel group may represent black and white or color grayscale by including emission areas EA1, EA2, and EA3 for emitting light of different colors from each other. However, the present disclosure is not limited thereto. The combination of emission areas EA1, EA2, and EA3 forming a single pixel group may be variously modified according to the arrangement of the emission areas EA1, EA2, and EA3 and the color of the light emitted from the emission areas EA1, EA2, and EA3.

[0091] Reference Figure 5 and Figure 6 , the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, an emission material layer EML, a thin film encapsulation layer ENC, and a touch sensor layer SENL.

[0092] The substrate SUB may be the same as or substantially the same as the substrate described above, and thus, a redundant description may not be repeated.

[0093] The thin film transistor layer TFTL may include a first buffer layer BF1, a bottom metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulator GI, a first interlayer dielectric layer ILD1, a capacitor electrode CPE, a second interlayer dielectric layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0094] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing or substantially preventing penetration of air and / or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked on each other.

[0095] Optionally, the bottom metal layer BML may be disposed on the first buffer layer BF1 (see Figure 6 ). For example, the bottom metal layer BML may include a single layer or multiple layers (e.g., may be made of a single layer or multiple layers) of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a suitable alloy thereof.

[0096] Optionally, the second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML (see Figure 6 ). The second buffer layer BF2 may include an inorganic film capable of preventing or substantially preventing the penetration of air and / or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked on each other.

[0097] The thin film transistor TFT may be disposed on the first buffer layer BF1 and / or the second buffer layer BF2, and may be a part of a pixel circuit of a pixel among the plurality of pixels (e.g., may be formed or included in the pixel circuit). For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0098] The semiconductor layer ACT may be disposed on the first buffer layer BF1 and / or the second buffer layer BF2. The semiconductor layer ACT may overlap the bottom metal layer BML and the gate electrode GE in the thickness direction and may be insulated from the gate electrode GE by the gate insulator GI. The material of a portion of the semiconductor layer ACT may be made conductive to form the source electrode SE and the drain electrode DE.

[0099] The gate electrode GE may be disposed on the gate insulator GI. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulator GI interposed therebetween.

[0100] The gate insulator GI may be disposed on the semiconductor layer ACT. For example, the gate insulator GI may cover the first buffer layer BF1 or the second buffer layer BF2, may cover the semiconductor layer ACT, and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulator GI may include a contact hole through which the first connection electrode CNE1 passes.

[0101] The first interlayer dielectric layer ILD1 may cover the gate electrode GE and the gate insulator GI. The first interlayer dielectric layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer dielectric layer ILD1 may be connected to the contact hole of the gate insulator GI and the contact hole of the second interlayer dielectric layer ILD2.

[0102] The capacitor electrode CPE may be disposed on the first interlayer dielectric layer ILD1. Figure 5 As shown in , there may be a plurality of capacitor electrodes CPE. The first capacitor electrode CPE1 may be disposed on the gate insulator GI. The second capacitor electrode CPE2 may be disposed on the first interlayer dielectric layer ILD1 and may overlap with the first capacitor electrode CPE1 in the thickness direction. According to another embodiment, as Figure 6 As shown in , the capacitor electrode CPE may overlap the gate electrode GE in the thickness direction so that the capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0103] The second interlayer dielectric layer ILD2 may cover the capacitor electrode CPE and the first interlayer dielectric layer ILD1. The second interlayer dielectric layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer dielectric layer ILD2 may be connected to the contact hole of the first interlayer dielectric layer ILD1 and the contact hole of the gate insulator GI.

[0104] The first connection electrode CNE1 may be disposed on the second interlayer dielectric layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be placed in a contact hole formed in the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the gate insulator GI to contact the drain electrode DE of the thin film transistor TFT. The first connection electrode CNE1 may include a single layer or multiple layers (e.g., may be made of a single layer or multiple layers) of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a suitable alloy thereof. The first connection electrode CNE1 may include: a layer including the same material as that of the first sub-metal layer 411, a layer including the same material as that of the second sub-metal layer 412, and a layer including the same material as that of the third sub-metal layer 413, which will be described in more detail below.

[0105] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer dielectric layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0106] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3. The second connection electrode CNE2 may be disposed in a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0107] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 pass.

[0108] The emission material layer EML may be disposed on the thin film transistor layer TFTL. Figure 5 , the emission material layer EML may include light emitting elements ED1 and ED2 and a pixel defining layer PDL. Figure 6 , the emission material layer EML may include light emitting elements ED1 , ED2 , and ED3 , a pixel defining layer PDL, and a bank structure BNS.

[0109] Figure 7 It is shown Figure 6 For example, Figure 7 Can show Figure 6 The first emission area EA1.

[0110] The light emitting elements ED1, ED2, and ED3 may be disposed on the second passivation layer PAS2. The light emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, emission layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3. Holes from the pixel electrodes AE1, AE2, and AE3 and electrons from the common electrodes CE1, CE2, and CE3 may be combined with each other in the emission layers EL1, EL2, and EL3 to emit light.

[0111] The pixel electrodes AE1, AE2 and AE3 may be disposed in emission areas EA1, EA2 and EA3, respectively. The pixel electrodes AE1, AE2 and AE3 may include a first pixel electrode AE1 disposed in a first emission area EA1, a second pixel electrode AE2 disposed in a second emission area EA2, and a third pixel electrode AE3 disposed in a third emission area EA3 (hereinafter, for the convenience of explanation, the pixel electrode AEn and the nth pixel electrode AEn indicate the same features and are not particularly distinguished in the description). Each of the pixel electrodes AE1, AE2 and AE3 may be spaced apart from the other pixel electrodes on the second passivation layer PAS2. The pixel electrodes AE1, AE2 and AE3 may be disposed in different emission areas EA1, EA2 and EA3, respectively.

[0112] The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the corresponding thin film transistor TFT through the corresponding first connection electrode CNE1 and the second connection electrode CNE2. According to an embodiment of the present disclosure, the pixel electrodes AE1, AE2, and AE3 may have a material layer having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium oxide (In 2 O 3 )) and a stacked structure of a reflective material layer (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a suitable mixture thereof). A layer with a higher work function may be disposed on a layer higher than the reflective material layer so that it may be closer to the emission layers EL1, EL2 and EL3. For example, the pixel electrodes AE1, AE2 and AE3 may have, but are not limited to, a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag and / or ITO / Ag / ITO.

[0113] The pixel defining layer PDL may be positioned on the second passivation layer PAS2 and the pixel electrodes AE1, AE2, and AE3, and may at least partially expose the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may define emission areas EA1, EA2, and EA3. The pixel defining layer PDL may cover edges of the pixel electrodes AE1, AE2, and AE3.

[0114] The pixel definition layer PDL may include an organic or inorganic insulating material. Figure 5 In the embodiment where the display area DA shown in FIG. 1 includes a continuous common electrode CE, the pixel defining layer PDL may be an organic film including (e.g., made of) acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and / or the like. As another example, in the embodiment where Figure 6 and Figure 7 In the display device shown in FIG. 1 including emission layers EL1, EL2 and EL3 and common electrodes CE1, CE2 and CE3 spaced apart from each other, the pixel defining layer PDL may include one or more inorganic insulating materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and silicon oxynitride. Zinc oxide may be ZnO and / or ZnO 2 .

[0115] According to the embodiment, Figure 5 As shown in , the spacer 191 may be disposed on the pixel defining layer PDL. The spacer 191 may support a mask during a process of manufacturing the emission layer EL. The spacer 191 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0116] The emission layer EL is formed on the pixel electrodes AE1 and AE2. The emission layer EL may include an organic material to emit light of a desired color (e.g., a determined or predetermined color). For example, the emission layer EL may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits light of a desired color (e.g., a predetermined color), and may be formed using a phosphor or a fluorescent material.

[0117] The common electrode CE is formed on the emission layer EL. The common electrode CE may be formed to cover the emission layer EL. Figure 5 As shown in FIG. 1 , the common electrode CE may be a common layer commonly formed in the emission areas EA1 and EA2 . A capping layer may be formed on the common electrode CE.

[0118] According to the embodiment, Figure 6 and Figure 7As shown in , the embankment structure BNS may be disposed on the pixel defining layer PDL. The embankment structure BNS may have a structure in which embankment layers BN1 and BN2 containing materials different from each other are sequentially stacked on each other (hereinafter, for the convenience of explanation, the embankment layer BNn and the nth embankment layer BNn indicate the same features and are not particularly distinguished in the description). A plurality of openings formed in the embankment structure BNS of the emission material layer EML may be defined along the boundary of the embankment structure BNS. The openings may include a first emission area EA1, a second emission area EA2, and a third emission area EA3. The first embankment layer BN1 and the second embankment layer BN2 of the embankment structure BNS may surround the emission areas EA1, EA2, and EA3 (e.g., around the periphery of the emission areas EA1, EA2, and EA3) and may be disposed to overlap with the light blocking layer BM, which will be described in more detail below. The light emitting elements ED1, ED2, and ED3 of the display device 10 may conform to the openings of the embankment structure BNS. For example, in an embodiment, the light emitting elements ED1, ED2, and ED3 correspond to the first opening, the second opening, and the third opening, respectively.

[0119] The first bank layer BN1 may be disposed on the pixel defining layer PDL. The first bank layer BN1 may include a metal having high electrical conductivity. For example, the first bank layer BN1 may include aluminum (Al) having high electrical conductivity.

[0120] Reference Figure 7 , the first bank layer BN1 may be disposed on the pixel defining layer PDL. A side surface of the first bank layer BN1 may be more recessed away from the emission areas EA1, EA2, and EA3 than a side surface of the pixel defining layer PDL. A side surface of the first bank layer BN1 may be more recessed away from the emission areas EA1, EA2, and EA3 than a side surface of the second bank layer BN2, which will be described in more detail below.

[0121] According to an embodiment, the first bank layer BN1 may include a metal material. According to an embodiment, the first bank layer BN1 may include aluminum (Al) or an alloy of aluminum (Al).

[0122] The second bank layer BN2 may be disposed on the first bank layer BN1. The second bank layer BN2 may include a tip TIP protruding from the first bank layer BN1. The side surface of the second bank layer BN2 may protrude more toward the emission regions EA1, EA2, and EA3 than the side surface of the first bank layer BN1. Since the side surface of the second bank layer BN2 protrudes more toward the emission regions EA1, EA2, and EA3 than the side surface of the first bank layer BN1, an undercut structure of the first bank layer BN1 may be formed under the tip TIP of the second bank layer BN2.

[0123] In the display device 10 according to the embodiment, the embankment structure BNS includes a tip TIP protruding toward the emission areas EA1, EA2, and EA3, and therefore, the emission layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 can be formed via a deposition process and an etching process instead of a mask process. In addition, different layers can be formed separately in different emission areas EA1, EA2, and EA3 via a deposition process. For example, even if the emission layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 are formed via a deposition process without using a mask, the deposited materials may not be connected to each other between the emission areas EA1, EA2, and EA3, and the tip TIP of the second embankment layer BN2 may be disconnected from each other via the embankment structure BNS therebetween. By forming a material for forming a determined layer on the front surface of the display device 10, and then etching and removing the layer formed at an unnecessary position, different layers can be formed separately in different emission areas EA1, EA2, and EA3. In the display device 10, different light emitting elements ED1, ED2 and ED3 can be formed for different emission areas EA1, EA2 and EA3 through deposition and etching processes without using a mask process, and unnecessary configurations can be eliminated from the display device 10, and therefore, the non-display area NDA can be reduced.

[0124] Since the first bank layer BN1 and the second bank layer BN2 include materials different from each other, the shape of the side surface of the bank structure BNS may be formed due to the difference in etching rate during the etching process. According to an embodiment, the second bank layer BN2 may include a material having an etching rate slower than that of the first bank layer BN1, and accordingly, the first bank layer BN1 may be further etched during the etching process, so that the lower surface of the tip TIP of the second bank layer BN2 may be exposed, thereby forming an undercut portion.

[0125] The second bank layer BN2 may include a metal material different from the metal material of the first bank layer BN1. It may be desirable that the metal material of the second bank layer BN2 is removed together with the metal material of the first bank layer BN1 by dry etching and is not etched by wet etching, or is etched slower than the first bank layer BN1. According to an embodiment, the first bank layer BN1 may include aluminum (Al), and the second bank layer BN2 may include titanium (Ti).

[0126] The tip TIP of the second bank layer BN2 may overlap the common electrodes CE1, CE2, and CE3 in the thickness direction (e.g., Z-axis direction) of the substrate SUB. In addition, the tip TIP of the second bank layer BN2 may overlap the pixel defining layer PDL in the thickness direction of the substrate SUB. The common electrodes CE1, CE2, and CE3 may be formed below the lower surface of the tip TIP of the second bank layer BN2. The maximum vertical distance from the substrate SUB to the common electrodes CE1, CE2, and CE3 may be less than the maximum vertical distance from the substrate SUB to the second bank layer BN2.

[0127] According to the embodiment, Figure 6 and Figure 7 As shown in , the emission layer EL may include a first emission layer EL1, a second emission layer EL2, and a third emission layer EL3 arranged in different emission areas EA1, EA2, and EA3 (hereinafter, for the convenience of explanation, the emission layer ELn and the nth emission layer ELn indicate the same features and are not particularly distinguished in the description). The first emission layer EL1 may be arranged on the first pixel electrode AE1 in the first emission area EA1, the second emission layer EL2 may be arranged on the second pixel electrode AE2 in the second emission area EA2, and the third emission layer EL3 may be arranged on the third pixel electrode AE3 in the third emission area EA3. For example, the first emission layer EL1 may emit a red first light, the second emission layer EL2 may emit a green second light, and the third emission layer EL3 may emit a blue third light.

[0128] The emission layers EL1, EL2, and EL3 may be in direct contact with the side surface of the first bank layer BN1. The contact area between the common electrodes CE1, CE2, and CE3 and the side surface of the first bank layer BN1 may be greater than the contact area between the emission layers EL1, EL2, and EL3 and the side surface of the first bank layer BN1. The common electrodes CE1, CE2, and CE3 on the side surface of the first bank layer BN1 may have a larger area, or may be disposed at a higher position than the emission layers EL1, EL2, and EL3 on the side surface of the first bank layer BN1. Since the common electrodes CE1, CE2, and CE3 of different light-emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first bank layer BN1, they may be in contact with the first bank layer BN1 with a larger area.

[0129] Since the light emitting elements ED1 , ED2 , and ED3 are formed in the openings of the bank structure BNS, the thickness of the first bank layer BN1 may be greater than (eg, much greater than) the thickness of the second bank layer BN2 .

[0130] According to an embodiment, the pixel defining layer PDL may be disposed on the pixel electrodes AE1, AE2, and AE3, and may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. A temporary protective layer may be disposed between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3, and then removed during the process of manufacturing the display device 10. Accordingly, the lower surface of the pixel defining layer PDL may be spaced apart from the pixel electrodes AE1, AE2, and AE3 at a position where the temporary protective layer is partially removed. The emission layers EL1, EL2, and EL3 may be disposed at a position where the pixel defining layer PDL is spaced apart from the pixel electrodes AE1, AE2, and AE3. The deposition process of the emission layers EL1, EL2, and EL3 may be performed so that the material for the emission layers EL1, EL2, and EL3 is deposited in an inclined direction, rather than in a direction perpendicular or substantially perpendicular to the upper surface of the substrate 110. Accordingly, the emission layers EL1, EL2, and EL3 may be disposed to fill the space between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL. The unremoved portion of the temporary protective layer may remain as a residual pattern RP where the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL are spaced apart from each other. Figure 6 and Figure 7 In the example shown in , the side surface of the residual pattern RP facing the emission areas EA1, EA2, and EA3 is more recessed than the side surface of the pixel defining layer PDL, but the present disclosure is not limited thereto. The side surface of the residual pattern RP may protrude from the side surface of the pixel defining layer PDL toward the emission areas EA1, EA2, and EA3, or may be aligned or substantially aligned with the side surface of the pixel defining layer PDL.

[0131] Common electrodes CE1, CE2, and CE3 may be disposed on the emission layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 include a transparent conductive material to allow light generated in the emission layers EL1, EL2, and EL3 to exit. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low-level voltage. When the pixel electrodes AE1, AE2, and AE3 receive a voltage equal to the data voltage and the common electrodes CE1, CE2, and CE3 receive a low-level voltage, a potential difference may be formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3 so that the emission layers EL1, EL2, and EL3 may emit light.

[0132] For example, the common electrodes CE1, CE2 and CE3 may include, but are not limited to, silver (Ag). The common electrodes CE1, CE2 and CE3 may include a material layer having a small work function, such as Li, Ca, Al, Mg, Pt, Pd, Ni, Au, Nd, Ir, Cr, Ba or a suitable compound thereof (e.g., BaF) or a suitable mixture (e.g., a mixture of Ag and Mg). The common electrodes CE1, CE2 and CE3 may also include a multilayer structure including the above materials, such as LiF / Ca or LiF / Al. The common electrodes CE1, CE2 and CE3 may also include a transparent metal oxide layer disposed on the material layer having a small work function.

[0133] The common electrodes CE1, CE2 and CE3 may include a first common electrode CE1, a second common electrode CE2 and a third common electrode CE3 which are arranged in emission areas EA1, EA2 and EA3 which are different from each other (hereinafter, for the convenience of explanation, the common electrode CEn and the nth common electrode CEn indicate the same features and are not particularly distinguished in the description). The first common electrode CE1 may be arranged on the first emission layer EL1 in the first emission area EA1, the second common electrode CE2 may be arranged on the second emission layer EL2 in the second emission area EA2, and the third common electrode CE3 may be arranged on the third emission layer EL3 in the third emission area EA3.

[0134] In the display device 10 according to an embodiment of the present disclosure, the common electrodes CE1, CE2, and CE3 disposed in the emission areas EA1, EA2, and EA3 different from each other are not directly connected to each other, but may be electrically connected to each other through the first bank layer BN1 of the bank structure BNS. Accordingly, portions of the common electrodes CE1, CE2, and CE3 may contact the side surface of the first bank layer BN1 of the bank structure BNS.

[0135] The cover layer CPL may be disposed on the common electrodes CE1, CE2, and CE3. The cover layer CPL may include an inorganic insulating material to cover the light emitting elements ED1, ED2, and ED3. The cover layer CPL may prevent or substantially prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. In an embodiment, the cover layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. Zinc oxide may be ZnO and / or ZnO 2 .

[0136] Reference Figure 6 and Figure 7, a plurality of trace patterns TRP1, TRP2, and TRP3 may be disposed on the second bank layer BN2. The trace patterns TRP1, TRP2, and TRP3 may include organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and a cover pattern CLP. The plurality of trace patterns TRP1, TRP2, and TRP3 may be arranged to surround the periphery of the emission areas EA1, EA2, and EA3. The trace patterns TRP1, TRP2, and TRP3 may be partially etched during a process of manufacturing the display device 10 so that the pattern shape may be changed.

[0137] Since the bank structure BNS includes the tip TIP, the trace patterns TRP1, TRP2, and TRP3 may be formed by disconnecting the emission layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the cover layer CPL in the emission areas EA1, EA2, and EA3.

[0138] The plurality of organic patterns ELP1, ELP2, and ELP3 may be disposed on the second bank layer BN2 to partially overlap the second bank layer BN2. The organic patterns ELP1, ELP2, and ELP3 may include the same materials as those of the emission layers EL1, EL2, and EL3, respectively.

[0139] The electrode patterns CEP1, CEP2, and CEP3 may be disposed on the organic patterns ELP1, ELP2, and ELP3, respectively. The electrode patterns CEP1, CEP2, and CEP3 may include a first electrode pattern CEP1, a second electrode pattern CEP2, and a third electrode pattern CEP3, respectively including the same material as the common electrodes CE1, CE2, and CE3 (hereinafter, for convenience of explanation, the electrode pattern CEPn indicates the same features as the nth electrode pattern CEPn and is not particularly distinguished in the description).

[0140] A plurality of cover patterns CLP may be positioned on the plurality of electrode patterns CEP1, CEP2, and CEP3. The cover pattern CLP may include the same material as that of the cover layer CPL. The arrangement relationship between the cover pattern CLP and the electrode patterns CEP1, CEP2, and CEP3 may be the same or substantially the same as the arrangement relationship between the cover layer CPL and the common electrodes CE1, CE2, and CE3.

[0141] The thin film encapsulation layer ENC may cover the emission material layer EML. Figure 5 As shown in , the thin film encapsulation layer ENC can completely cover the common electrode CE. As another example, Figure 6 and Figure 7 As shown in , the thin film encapsulation layer ENC may cover the light emitting elements ED1 , ED2 , and ED3 , the bank structure BNS, and the trace patterns TRP1 , TRP2 , and TRP3 .

[0142] The thin film encapsulation layer ENC may include at least one inorganic layer to prevent or substantially prevent oxygen and / or moisture from penetrating into the emission material layer EML. The thin film encapsulation layer ENC may include at least one organic layer to protect the emission material layer EML from particles such as dust. According to an embodiment of the present disclosure, the thin film encapsulation layer ENC may include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3 stacked on each other in sequence. The first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 may be inorganic encapsulation layers, and the organic encapsulation film TFE2 disposed between the first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 may be an organic encapsulation layer.

[0143] Each of the first inorganic encapsulating film TFE1 and the second inorganic encapsulating film TFE3 may include one or more inorganic insulating materials. The inorganic insulating materials may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride. Zinc oxide may be ZnO and / or ZnO 2 .

[0144] The organic encapsulation film TFE2 may include a polymer-based material. The polymer-based material may include acrylic resin, epoxy resin, polyimide, polyethylene and / or the like. For example, the organic encapsulation film TFE2 may include acrylic resin, such as polymethyl methacrylate and polyacrylic acid. The organic encapsulation film TFE2 may be formed by curing a monomer or applying a polymer.

[0145] According to the embodiment, Figure 6 As shown in , the first inorganic encapsulation film TFE1 may include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3 arranged to correspond to different emission areas EA1, EA2, and EA3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may contain an inorganic insulating material to cover the light emitting elements ED1, ED2, and ED3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may prevent or substantially prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may cover the organic patterns ELP1, ELP2, and ELP3, the electrode patterns CEP1, CEP2, and CEP3, and the covering pattern CLP, thereby preventing or substantially preventing the pattern arranged on the embankment structure BNS from being delaminated during the process of manufacturing the display device 10.

[0146] Since the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be formed by chemical vapor deposition (CVD), they can be formed along the steps of the layers on which they are deposited. For example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can form a thin film even under the undercut portion of the tip TIP of the bank structure BNS.

[0147] The first inorganic layer TL1 may be disposed on the first light emitting element ED1 and the first electrode pattern CEP1. The first inorganic layer TL1 may be disposed to cover the side surfaces of the first light emitting element ED1, the cover layer CPL, and the second bank layer BN2 adjacent to the first common electrode CE1, and may cover the first organic pattern ELP1, the first electrode pattern CEP1, and the cover pattern CLP. However, the first inorganic layer TL1 may not overlap the second opening or the third opening, and may be disposed only on the first opening and the bank structure BNS around the first opening (e.g., adjacent to the first opening). Although in Figures 4 to 6 In the example shown in , the thickness of the first inorganic layer TL1 encapsulated along the outer surface of the first trace pattern TRP1 and the light-emitting element ED1 is not uniform, but the first organic layer TL1 can be set with a uniform or substantially uniform thickness along the upper surface and side surfaces of the first trace pattern TRP1, the side surface and lower surface of the second bank layer BN2, the side surface of the first bank layer BN1, and the upper surface of the first common electrode CE1 (hereinafter, for the convenience of explanation, the organic pattern ELPn and the nth organic pattern ELPn indicate the same features and are not particularly distinguished in the description; the trace pattern TRPn and the nth trace pattern TRPn indicate the same features and are not particularly distinguished in the description; the light-emitting element EDn and the nth light-emitting element EDn indicate the same features and are not particularly distinguished in the description;).

[0148] The second inorganic layer TL2 may be disposed on the second light emitting element ED2 and the second electrode pattern CEP2. However, the second inorganic layer TL2 may not overlap the first opening or the third opening, and may be disposed only on the second opening and the bank structure BNS around (eg, adjacent to) the second opening.

[0149] The third inorganic layer TL3 may be disposed on the third light emitting element ED3 and the third electrode pattern CEP3. However, the third inorganic layer TL3 may not overlap the first opening or the second opening, and may be disposed only on the third opening and the bank structure BNS around (eg, adjacent to) the third opening.

[0150] The first inorganic layer TL1 may be formed after forming the first common electrode CE1. The second inorganic layer TL2 may be formed after forming the second common electrode CE2. The third inorganic layer TL3 may be formed after forming the third common electrode CE3. Accordingly, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be respectively disposed to cover different electrode patterns CEP1, CEP2, and CEP3 and the organic patterns ELP1, ELP2, and ELP3. When viewed from the top (e.g., in a plan view), each of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may have a boundary that is the same as or similar to a boundary of the corresponding first trace pattern TRP1, the second trace pattern TRP2, and the third trace pattern TRP3, and may have an area larger than the area of ​​the corresponding opening of the embankment structure BNS or the corresponding emission areas EA1, EA2, and EA3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be spaced apart from each other on the embankment structure BNS. Accordingly, a portion of the second bank layer BN2 may not overlap with the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3, and a portion of the upper surface of the second bank layer BN2 may be exposed in the space between the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 without being covered by the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3. The exposed upper surface of the second bank layer BN2 may be in direct contact with the organic encapsulation film TFE2 of the thin film encapsulation layer ENC.

[0151] The touch sensor layer SENL may be disposed on the thin film encapsulation layer ENC. The touch sensor layer SENL may include a touch buffer layer TBF, a touch insulating layer TIL, a touch electrode TE, and a touch protection layer TPR.

[0152] The touch buffer layer TBF may be disposed on the thin film encapsulation layer ENC. The touch buffer layer TBF may have insulating properties and optical characteristics. The touch buffer layer TBF may include at least one inorganic film. However, the present disclosure is not limited thereto, and the touch buffer layer TBF may be eliminated as needed or desired. In some embodiments, a connection electrode electrically connected between the touch electrodes TE may be disposed on the touch buffer layer TBF. The connection electrode may include a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO) (e.g., may be made thereof), or may include a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and / or a stacked structure of an APC alloy and ITO (e.g., ITO / APC / ITO) (e.g., may be made thereof).

[0153] like Figure 5As shown in , the touch connection electrode BE1 may be disposed on the touch buffer layer TBF. The touch insulation layer TIL may cover the touch buffer layer TBF and a portion of the touch connection electrode BE1. Some of the touch electrodes TE may be disposed on the touch insulation layer TIL and may contact the touch connection electrode BE1 through a through hole disposed in the touch insulation layer TIL. The drive electrode RE may be disposed on the touch insulation layer TIL. Figure 6 As shown in , the touch insulating layer TIL may cover the touch buffer layer TBF. The touch insulating layer TIL may have insulating properties. For example, the touch insulating layer TIL may be an inorganic layer including at least one selected from a group consisting of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0154] Some of the touch electrodes TE may be disposed on the touch insulating layer TIL. The touch electrode TE may not overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3. The touch electrode TE may include a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO) (e.g., may be made of it), or may include a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and / or a stacked structure of an APC alloy and ITO (e.g., ITO / APC / ITO) (e.g., may be made of it).

[0155] The touch protection layer TPR may cover the touch electrode TE and the touch insulation layer TIL. The touch protection layer TPR may have insulation properties and optical characteristics. The touch protection layer TPR may be formed of any material among the materials listed above for the touch insulation layer TIL.

[0156] The light-blocking layer BM may be disposed on the touch sensor layer SENL. The light-blocking layer BM may overlap with the pixel-defining layer PDL and / or the embankment structure BNS. The light-blocking layer CM may include a first optical opening OPT1 corresponding to the first emission area EA1, a second optical opening OPT2 corresponding to the second emission area EA2, and a third optical opening OPT3 corresponding to the third emission area EA3. The light-blocking layer BM may include a light-absorbing material. For example, the light-blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be, but is not limited to, carbon black, and the organic black pigment may include, but is not limited to, at least one of lactam black, perylene black, and aniline black. The light-blocking layer BM may prevent or substantially prevent visible light from penetrating and mixing colors between the first emission area EA1, the second emission area EA2, and the third emission area EA3 to improve the color gamut of the display device 10.

[0157] According to an embodiment, the color filter layer CF may overlap the emission areas EA1 , EA2 , and EA3 , and may be disposed on the touch protection layer TPR and the light blocking layer BM.

[0158] The color filter layer CF may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, which are respectively arranged in different emission areas EA1, EA2, and EA3. The color filters CF1, CF2, and CF3 may include colorants (such as dyes and pigments) that absorb light within a wavelength range other than light within a specific wavelength range, and may be arranged in association with the light emitted from the emission areas EA1, EA2, and EA3 (hereinafter, for the convenience of explanation, the color filter CFn and the nth color filter CFn indicate the same features and are not particularly distinguished in the description). For example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first emission area EA1 and transmits only a red first light. The second color filter CF2 may be a green color filter that is arranged to overlap with the second emission area EA2 and transmits only a green second light. The third color filter CF3 may be a blue color filter that is arranged to overlap with the third emission area EA3 and transmits only a blue third light.

[0159] Although in Figure 6 In the example shown in , the color filters CF1, CF2 and CF3 are spaced apart from each other on the light blocking layer BM, but the present disclosure is not limited thereto. In other words, the color filters CF1, CF2 and CF3 may partially overlap each other. In other words, different color filters CF1, CF2 and CF3 may not overlap with the emission areas EA1, EA2 and EA3, but may overlap with each other on the light blocking layer BM.

[0160] The organic planarization layer ORL may be disposed on the touch sensor layer SENL. The organic planarization layer ORL may provide a flat or substantially flat surface throughout the elements having different heights so that the polarization film PF may be easily attached thereto, and may prevent or substantially prevent reflection of external light caused by the polarization film PF from being recognized by the user.

[0161] The organic planarization layer ORL may include an overcoat layer OC. The overcoat layer OC may include (eg, may be made of) an organic material, and may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and / or the like.

[0162] Figure 8 yes Figure 2 An enlarged plan view of region II.

[0163] Reference Figure 8, the middle area MA may surround the through hole TH (e.g., around the periphery of the through hole TH), and may be positioned between the through hole TH and the display area DA. The first dam DAM1 and the second dam DAM2 may be positioned in the middle area MA. The second dam DAM2 surrounds the through hole TH (e.g., around the periphery of the through hole TH), and the first dam DAM1 surrounds the second dam DAM2 (e.g., around the periphery of the second dam DAM2).

[0164] Fig. 9 is shown along Figure 8 A cross-sectional view of an example of a display panel taken along line III-III'.

[0165] Reference Fig. 9 The through hole TH may penetrate the substrate SUB, the thin film transistor layer TFTL, the emission material layer EML, the thin film encapsulation layer ENC, the touch sensor layer SENL, the organic planarization layer ORL, and the polarization film PF included in the display panel 100. The through hole TH may be formed via a laser processing process. The through hole TH may be covered by the window CW (e.g., see Figure 3 ) covers, and the optical device OPD (see, for example, Figure 3 ) can be arranged inside the through hole TH.

[0166] A plurality of light emitting elements are disposed in the display area DA, but not in the middle area MA. The middle area MA may include a first dam DAM1, a second dam DAM2, and a plurality of edge structures SP (eg, see Fig.10 and Fig.11 The first inorganic encapsulation film TFE1 disposed on the light emitting element adjacent to the boundary between the display area DA and the middle area MA may cover the middle area MA, and may cover the first dam DAM1, the second dam DAM2, and the plurality of edge structures SP in the middle area MA.

[0167] The substrate SUB may include a first surface SUB_S1, a second surface SUB_S2, and a third surface SUB_S3 in the middle area MA. The second surface SUB_S2 of the substrate SUB may connect the third surface SUB_S3 of the substrate SUB with the first surface SUB_S1. The second surface SUB_S2 of the substrate SUB may be formed by laser processing for forming the through hole TH, and may be an inclined surface toward the through hole TH. In more detail, the second surface SUB_S2 of the substrate SUB may be formed by spraying an etching solution after irradiating laser. An angle θ1 formed by the third surface SUB_S3 of the substrate SUB and the second surface SUB_S2 may be an obtuse angle, and an angle θ2 formed by the first surface SUB_S1 of the substrate SUB and the second surface SUB_S2 may be an obtuse angle.

[0168] Fig.10 It is shown Fig. 9 An enlarged cross-sectional view of an example of area A2. Fig.11 It is shown Fig. 9 FIG. 4 is an enlarged cross-sectional view of another example A2_1 of the area A2.

[0169] Reference Fig.10 and Fig.11 , the first dam DAM1 may be disposed on the second interlayer dielectric layer ILD2. The display device 10 may have a structure in which several layers are sequentially stacked on one substrate SUB. Some layers of the display device 10 may include organic materials (e.g., may be made of organic materials) and may be formed via a process of directly applying organic materials on the substrate SUB. For example, the organic encapsulation film TFE2 of the thin film encapsulation layer ENC may include organic materials and may have fluidity and flow. The organic material applied on the display area DA may overflow into the non-display area NDA. Accordingly, the first dam DAM1 may be positioned in the middle area MA and may prevent or substantially prevent the organic material disposed in the display area DA from overflowing into the through hole TH. The first dam DAM1 may prevent or substantially prevent the organic material applied to the display area DA from overflowing into the non-display area NDA. Therefore, the first dam DAM1 may have a minimum or reduced thickness or height.

[0170] In some embodiments, the first dam DAM1 may have a multi-layer structure. The first dam DAM1 may include a layer including the same material as that of the pixel defining layer PDL of the display area DA, and a layer including the same material as that of the spacer 191. There may be a plurality of first dams DAM1, and the plurality of material layers may be alternately stacked on each other several times. In other words, the first dam DAM1 may have a multi-layer structure in which a first dam layer and a second dam layer are alternately stacked on each other.

[0171] The first inorganic encapsulation film TFE1, the organic encapsulation film TFE2, and the second inorganic encapsulation film TFE3 may be disposed on the first dam DAM1. The first dam DAM1 may include a first side surface DAM_S1 facing the through hole TH, and a second side surface DAM_S2 opposite to the first side surface DAM_S1. The first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 may contact each other on the first side surface DAM_S1 of the first dam DAM1 without the organic encapsulation film TFE2 between the first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3. The organic encapsulation film TFE2 may be disposed on the second side surface DAM_S2, but not on the first side surface DAM_S1.

[0172] According to an embodiment, the second dam DAM2 may be positioned between the through hole TH and the first dam DAM 1. The second dam DAM2 may block particles and / or the like from penetrating through the through hole TH.

[0173] The edge structure SP may be disposed on the second interlayer dielectric layer ILD2 in the middle area MA. The edge structure SP may increase the contact area of ​​the packaging film, thereby preventing or substantially preventing delamination and / or cracking of the film around (eg, adjacent to) the through hole TH. Figure 5 In the display device shown in FIG. 1 , in which the emission layer EL and the common electrode CE are formed across the entire surface, since the emission layer EL and the common electrode CE are formed of a material having a low step coverage, they may be disconnected by the tip structure of the edge structure SP, which will be described in more detail below.

[0174] There may be multiple edge structures SP. Fig.10 As shown in FIG. 1 , the edge structure SP may be disposed between the first dam DAM1 and the through hole TH. However, the present disclosure is not limited thereto, and as Fig.11 As shown in FIG. 1 , the edge structures SP may be disposed closer to the display area DA than the first dam DAM1 so that they overlap with the organic encapsulation film TFE2 in the thickness direction of the substrate (e.g., the Z-axis direction). In some embodiments, some of the edge structures SP may be disposed between the second dam DAM2 and the through hole TH (e.g., as shown in FIG. 1 ). Fig.10 ), while other ones of the edge structures SP may be disposed at positions where they overlap with the organic encapsulating film TFE2 in the thickness direction of the substrate (eg, as shown in FIG. 1 ). Fig.11 ).

[0175] Figure 12 to Figure 14 It is shown Fig.10 and Fig.11 Examples of areas A3, A3_1 and A3_2 are enlarged cross-sectional views of areas A3. For example, Figure 12 to Figure 14 is an enlarged cross-sectional view showing one edge structure SP among a plurality of edge structures SP according to various embodiments.

[0176] Reference Figure 12 to Figure 14 , each of the edge structures SP (or SP_1, SP_2) may include a lower metal stack 410 (or 410_1, 410_2) and an upper metal stack 420 (or 420_1, 420_2). In the lower metal stack 410, a first sub-metal layer 411 (or 411_1, 411_2), a second sub-metal layer 412 (or 412_1, 412_2), and a third sub-metal layer 413 (or 413_1, 413_2) may be stacked on each other in sequence. In the upper metal stack 420 disposed on the lower metal stack 410, a fourth sub-metal layer 421 (or 421_1, 421_2) and a fifth sub-metal layer 422 (or 422_1, 422_2) may be stacked on each other in sequence.

[0177] Each of the lower metal stack 410 and the upper metal stack 420 may have a tip structure. The lower metal stack 410 may have a tip structure in which the width w12 of the third sub-metal layer 413 is greater than the width w21 of the second sub-metal layer 412. The upper metal stack 420 may have a tip structure in which the width w13 of the fifth sub-metal layer 422 is greater than the width w22 of the fourth sub-metal layer 421. In other words, in the edge structure SP, two tip structures are stacked on each other. By stacking the two tip structures, when compared with a single tip structure, the penetration of external air can be effectively prevented while reducing the number of edge structures SP. Since the effect of preventing moisture penetration can be improved, the content of nitride contained in the first inorganic encapsulation film TFE1 can be reduced, thereby increasing the brightness.

[0178] The width of the first to fifth sub-metal layers refers to the width at the interface where the tip structure is formed. In more detail, the second sub-metal layer 412 and the third sub-metal layer 413 form a tip structure, and the width at the interface between the second sub-metal layer 412 and the third sub-metal layer 413 is defined as the width w21 of the second sub-metal layer 412 and the width w12 of the third sub-metal layer 413. The fourth sub-metal layer 421 and the fifth sub-metal layer 422 form a tip structure, and the width at the interface between the fourth sub-metal layer 421 and the fifth sub-metal layer 422 is defined as the width w22 of the fourth sub-metal layer 421 and the width w13 of the fifth sub-metal layer 422. The inorganic layer 430 (or 430_1) described in more detail below forms a tip structure on the third sub-metal layer 413, and the width w31 of the inorganic layer 430 is defined as the width at the boundary between the inorganic layer 430 and the third sub-metal layer 413. The width w11 of the first sub-metal layer 411 refers to the width at the interface with the second interlayer dielectric layer ILD2. The widths of the first sub-metal layer 411, the third sub-metal layer 413, the fifth sub-metal layer 422, and the inorganic layer 430 may be measured relative to their lower surfaces. The widths of the second sub-metal layer 412 and the fourth sub-metal layer 421 may be measured relative to their upper surfaces.

[0179] The lower metal stack 410 is formed simultaneously or substantially simultaneously when the source electrode SE and the drain electrode DE (or in more detail, the first connection electrode CNE1) of the thin film transistor TFT are formed in the display area DA. Accordingly, the source electrode SE and the drain electrode DE (or in more detail, the first connection electrode CNE1) may include a layer including the same material as that of the first sub-metal layer 411, a layer including the same material as that of the second sub-metal layer 412, and a layer including the same material as that of the third sub-metal layer 413.

[0180] The upper metal stack 420 may be formed after forming the pixel electrodes AE1, AE2, and AE3 and before forming the emission layers EL1, EL2, and EL3. Figure 6 As shown in FIG. 1 , if the bank structure BNS is formed in the display area DA, the upper metal stack 420 may be formed together when the bank structure BNS is formed. In this case, the first bank layer BN1 may include the same material as the fourth sub-metal layer 421, and the second bank layer BN2 may include the same material as the fifth sub-metal layer 422. Figure 5 As shown in FIG, when the emission layer EL and the common electrode CE are formed across the entire surface, an additional process of forming the upper metal stack 420 may be performed only in the middle area MA after forming the pixel defining layer PDL.

[0181] The width w11 of the first submetal layer 411 may be greater than the width w12 of the third submetal layer 413. In a process of etching the pixel electrode after forming the source and drain electrodes, the width w12 of the third submetal layer 413 exposed at a higher level may be smaller than the width w11 of the first submetal layer 411.

[0182] according to Fig.12 In the embodiment shown in , the edge structure SP may include an inorganic layer 430 disposed between the lower metal stack 410 and the upper metal stack 420. The width w31 of the inorganic layer 430 may be greater than or equal to the width w12 of the third sub-metal layer 413. If the width w31 of the inorganic layer 430 is greater than the width w12 of the third sub-metal layer 413, the emission layer EL and the common electrode CE may be effectively cut. The inorganic layer 430 may include one or more inorganic insulating materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. Zinc oxide may be ZnO and / or ZnO 2 According to the present embodiment, the inorganic layer 430 may include the same material as that of the pixel defining layer PDL in the display area DA.

[0183] according to Fig.13 , the width w22_1 of the fourth sub-metal layer 421_1 may be greater than the width w21_1 of the second sub-metal layer 412_1. During wet etching to form the tip structure of the upper metal stack 420_1, the side surface of the second sub-metal layer 412_1 of the lower metal stack 410_1 is also etched, and thus, the width w21_1 of the second sub-metal layer 412_1 may be reduced.

[0184] The length of the tip of the upper metal stack 420_1 (eg, w13_1-w22_1) may be smaller than the length of the tip of the lower metal stack 410_1 (eg, w12_1-w21_1). The tip of the lower metal stack 410_1 may be strengthened by wet etching twice, thereby increasing the length of the tip.

[0185] The thickness of the fourth sub-metal layer 421_1 may be greater than the thickness of the second sub-metal layer 412_1. The thickness of the fourth sub-metal layer 421_1 may be greater than the thickness of the fifth sub-metal layer 422_1.

[0186] The width w13_1 of the fifth submetal layer 422_1 may be equal to or smaller than the width w11_1 of the first submetal layer 411_1. During the process of etching the side surface of the first bank layer BN1, the width w13_1 of the fifth submetal layer 422_1 exposed at a higher level may be reduced.

[0187] exist Fig.14 In the embodiment shown in , the edge structure SP_2 includes an inorganic layer 430_1, and the width w22_2 of the fourth sub-metal layer 421_2 is greater than the width w21_2 of the second sub-metal layer 412_2. Fig.14 As shown in FIG. 4 , the width of the inorganic layer 430_1 is represented as w31_1, and the widths of the first sub-metal layer 411_2, the third sub-metal layer 413_2, and the fifth sub-metal layer 422_2 are represented as w11_2, w12_2, and w13_2, respectively.

[0188] The first sub-metal layer 411_2, the third sub-metal layer 413_2, and the fifth sub-metal layer 422_2 may include the same material as each other (e.g., may be made of the same material), the second sub-metal layer 412_2 and the fourth sub-metal layer 421_2 may include the same material as each other (e.g., may be made of the same material), and the first sub-metal layer 411_2 and the second sub-metal layer 412_2 may include different materials from each other (e.g., may be made of different materials). The first sub-metal layer 411_2, the third sub-metal layer 413_2, and the fifth sub-metal layer 422_2 may include titanium (Ti), and the second sub-metal layer 412_2 and the fourth sub-metal layer 421_2 may include aluminum (Al).

[0189] The first inorganic encapsulation film TFE1 may contact a lower surface of a tip of the edge structure SP_2. The first inorganic encapsulation film TFE1 may contact a lower surface of the third sub-metal layer 413_2 and lower and upper surfaces of the fifth sub-metal layer 422_2.

[0190] Although like Figure 6 The example shown in Figure 12 to Figure 14In the example shown in FIG. 1 , the emission layers EL1 , EL2 , and EL3 and the common electrodes CE1 , CE2 , and CE3 are spaced apart from each other and are not formed in the middle area MA so that the edge structure SP contacts the first inorganic encapsulation film TFE1 , but the present disclosure is not limited thereto. Figure 5 When the emission layer EL and the common electrode CE are formed across the entire surface as shown in , residues of the emission layer EL and the common electrode CE may be formed on a portion of the side surface and the upper surface of the edge structure SP. In this case, a portion of the side surface of the edge structure SP may be in contact with the emission layer EL, and another portion of the side surface of the edge structure SP may be in contact with the first inorganic encapsulation film TFE1.

[0191] Various processes of the method of manufacturing the edge structure SP of the display device 10 according to the embodiment of the present disclosure will hereinafter be described in more detail.

[0192] Figures 15 to 19 is a cross-sectional view showing a sequential process of a method for manufacturing a display device according to an embodiment of the present disclosure. For example, Figures 15 to 19 The manufacturing process can be schematically shown Fig.14 Hereinafter, for the sake of convenience, the formation process of each layer may not be described in detail, and the formation order of each layer may be described in more detail.

[0193] Reference Fig.15 , a lower metal stack material layer 410a is formed on the second interlayer dielectric layer ILD2. The lower metal stack material layer 410a may include a first sub-metal material layer 411a, a second sub-metal material layer 412a, and a third sub-metal material layer 413a stacked one on another in sequence. The lower metal stack material layer 410a may be formed on the second interlayer dielectric layer ILD2 in the middle area MA, and a source electrode SE and a drain electrode DE may be formed on the second interlayer dielectric layer ILD2 in the display area DA. Although the first passivation layer PAS1, the second passivation layer PAS2, and the pixel electrode layer are formed during subsequent processes, the first passivation layer PAS1, the second passivation layer PAS2, and the pixel electrode layer may not be formed on the lower metal stack material layer 410a.

[0194] Then, refer to Fig.16 , the side surface of the second sub-metal material layer 412a is etched. During the wet etching process of patterning the pixel electrode layer in the display area DA to form the pixel electrodes AE1, AE2 and AE3 spaced apart from each other, the side surface of the second sub-metal material layer 412a in the middle area MA may be etched. Thus, the tip structure of the lower metal stack material layer 410a may be obtained.

[0195] Then, refer to Fig.17, an inorganic layer 430a is formed on the lower metal stack material layer 410a. In the process of forming the pixel defining layer PDL in the display area DA, an inorganic layer 430a may be formed on the third sub-metal material layer 413a in the middle area MA. Fig.13 As shown in FIG. 4A and FIG. 5B , there is no edge structure SP of the inorganic layer 430 , and this process may be omitted.

[0196] Then, refer to Fig.18 , an upper metal stack material layer 420a is formed on the inorganic layer 430a. The upper metal stack material layer 420a may include a fourth sub-metal material layer 421a and a fifth sub-metal material layer 422a sequentially stacked on each other. Figure 5 When formed across the entire surface as shown in , the upper metal stack material layer 420a may be formed in the middle area MA between the formation of the pixel defining layer PDL and the formation of the emission layer EL. Figure 6 When the bank structure BNS is included as shown in FIG, during the process of forming the bank structure BNS in the display area DA, the upper metal stack material layer 420a may be formed in the middle area MA. The first bank layer BN1 and the fourth sub-metal material layer 421a may be formed together, and the second bank layer BN2 and the fifth sub-metal material layer 422a may be formed together. Fig.13 As shown in FIG. 4A and FIG. 5B , there is no edge structure SP of the inorganic layer 430 , and this process may be omitted.

[0197] Then, refer to Fig.19 , etching the side surface of the fourth sub-metal material layer 421a and the side surface of the second sub-metal material layer 412a. Thus, the upper metal stack material layer 420a may have a tip structure, and the tip structure of the lower metal stack material layer 410a may be secondary enhanced. Figure 6 When including the dam structure BNS as shown in FIG, during the process of forming the undercut structure of the first dam layer BN1 in the display area DA, the side surface of the fourth sub-metal material layer 421a and the side surface of the second sub-metal material layer 412a may be etched together in the middle area MA.

[0198] The foregoing is an explanation of some embodiments of the present disclosure and should not be interpreted as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications can be made in the embodiments without departing from the spirit and scope of the present disclosure. It should be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise explicitly indicated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it should be understood that the foregoing is an explanation of various exemplary embodiments and should not be interpreted as being limited to the specific embodiments disclosed herein, and it should be understood that modifications to the disclosed embodiments and other exemplary embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the accompanying claims and their equivalents.

Claims

1. A display device, comprising: a substrate, the substrate comprising a display area surrounding the through hole and an intermediate area between the through hole and the display area; A light emitting element, the light emitting element being on the display area of ​​the substrate and comprising: Pixel electrode; an emission layer, the emission layer being on the pixel electrode; and A common electrode, the common electrode being on the emission layer; an edge structure on the middle region of the substrate and comprising a lower metal stack and an upper metal stack; and a first inorganic encapsulation film, the first inorganic encapsulation film being on the light emitting element and the edge structure, in: The lower metal stack includes a first sub-metal layer, a second sub-metal layer on the first sub-metal layer, and a third sub-metal layer on the second sub-metal layer; The upper metal stack is on the lower metal stack and includes a fourth sub-metal layer on the third sub-metal layer and a fifth sub-metal layer on the fourth sub-metal layer; The width of the first sub-metal layer is greater than the width of the third sub-metal layer; The width of the third sub-metal layer is greater than the width of the second sub-metal layer; and The width of the fifth sub-metal layer is greater than the width of the fourth sub-metal layer.

2. The display device according to claim 1, wherein: The edge structure includes an inorganic layer between the lower metal stack and the upper metal stack, and Wherein, the width of the inorganic layer is greater than or equal to the width of the third sub-metal layer.

3. The display device according to claim 1, wherein: The width of the fourth sub-metal layer is greater than the width of the second sub-metal layer.

4. The display device according to claim 1, wherein: The thickness of the fourth sub-metal layer is greater than the thickness of the fifth sub-metal layer.

5. The display device according to claim 1, further comprising: a pixel defining layer, the pixel defining layer being on the display area of ​​the substrate and exposing at least a portion of the pixel electrode; a first bank layer, the first bank layer being on the pixel defining layer; as well as a second bank layer on the first bank layer and including a side surface protruding from a side surface of the first bank layer, wherein the first bank layer comprises the same material as that of the fourth sub-metal layer, and The second bank layer includes a material that is the same as that of the fifth sub-metal layer.

6. The display device according to claim 2, further comprising: a pixel defining layer on the display area of ​​the substrate and exposing at least a portion of the pixel electrode, The inorganic layer includes the same material as that of the pixel defining layer.

7. The display device according to claim 1, further comprising: a thin film transistor, the thin film transistor being between the substrate and the light emitting element in the display region and comprising a semiconductor layer, a source electrode, a drain electrode and a gate electrode, Wherein, the source electrode and the drain electrode include: a layer comprising the same material as that of the first sub-metal layer; a layer including the same material as that of the second sub-metal layer; and A layer including the same material as that of the third sub-metal layer.

8. The display device according to claim 1, further comprising: an organic encapsulation film, the organic encapsulation film being on the first inorganic encapsulation film; a second inorganic encapsulation film, the second inorganic encapsulation film being on the organic encapsulation film; as well as a first dam, the first dam being between the substrate and the first inorganic encapsulating film in the middle region, wherein the first dam includes a first side surface facing the through hole and a second side surface opposite to the first side surface, The first inorganic encapsulating film and the second inorganic encapsulating film are in contact with each other on the first side surface of the first dam.

9. The display device according to claim 8, wherein: The organic encapsulating film is on the second side surface of the first dam.

10. The display device according to claim 8, wherein: The edge structure is between the first dam and the through hole.

11. The display device according to claim 8, wherein: The edge structure overlaps the organic encapsulation film in a thickness direction of the substrate.

12. The display device according to claim 1, wherein: The first sub-metal layer, the third sub-metal layer, and the fifth sub-metal layer include titanium, and Wherein, the second sub-metal layer and the fourth sub-metal layer contain aluminum.

13. The display device according to claim 5, wherein: The common electrode contacts the side surface of the first bank layer.

14. The display device according to claim 5, wherein: A maximum vertical distance from the substrate to the common electrode is smaller than a maximum vertical distance from the substrate to the second bank layer.

15. The display device according to claim 5, further comprising: an organic pattern on the second bank layer and including the same material as that of the emission layer; as well as an electrode pattern on the organic pattern and comprising the same material as that of the common electrode, wherein the emission layer and the organic pattern are spaced apart from each other, and Wherein, the common electrode and the electrode pattern are spaced apart from each other.

16. The display device according to claim 1, wherein: The substrate includes an inclined surface facing the through hole.

17. The display device according to claim 16, further comprising: An optical device is positioned in the through hole.

18. A display device comprising: a substrate, the substrate comprising a display area surrounding the through hole and an intermediate area between the through hole and the display area; A light emitting element, the light emitting element being on the display area of ​​the substrate and comprising: Pixel electrode; an emission layer, the emission layer being on the pixel electrode; and A common electrode, the common electrode being on the emission layer; an edge structure on the middle region of the substrate and comprising a lower metal stack and an upper metal stack; and a first inorganic encapsulation film, the first inorganic encapsulation film being on the light emitting element and the edge structure, in: The lower metal stack includes a first sub-metal layer, a second sub-metal layer on the first sub-metal layer, and a third sub-metal layer on the second sub-metal layer; The upper metal stack is on the lower metal stack and includes a fourth sub-metal layer on the third sub-metal layer and a fifth sub-metal layer on the fourth sub-metal layer; The thickness of the fourth sub-metal layer is greater than the thickness of the fifth sub-metal layer; and The first inorganic encapsulating film contacts a lower surface of the third sub-metal layer, and a lower surface and an upper surface of the fifth sub-metal layer.

19. The display device according to claim 18, wherein: The edge structure includes an inorganic layer between the lower metal stack and the upper metal stack, and Wherein, the width of the inorganic layer is greater than or equal to the width of the third sub-metal layer.

20. The display device according to claim 18, wherein: The width of the first sub-metal layer is greater than the width of the third sub-metal layer, and Wherein, the width of the fourth sub-metal layer is greater than the width of the second sub-metal layer.

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