Semiconductor surface coating method

Abstract

The invention discloses a semiconductor surface coating method. The method comprises the following steps: pre-cleaning a semiconductor substrate; in a vacuum chamber, performing staged coating treatment on the pre-cleaned semiconductor substrate so as to form a plurality of layers of silicon films on the surface of the semiconductor substrate by staged deposition; and coating the surface of the semiconductor substrate again so as to deposit the diamond-like coating on the surface of the silicon film. By adopting the technical scheme provided by the invention, the tensile stress of the semiconductor coating surface can be enhanced, so that the phenomena of hardness, brittleness and falling of the semiconductor surface coating are effectively prevented.

Description

Technical Field

[0001] The invention relates to the technical field of microelectronics manufacturing, and in particular to a semiconductor surface coating method. Background Art

[0002] Under high temperature and high pressure environment, the coating on the surface of semiconductor components often becomes hard and brittle and falls off, thus affecting the normal use of semiconductor components. Therefore, how to prevent the coating on the surface from becoming hard and brittle and falling off is an urgent problem to be solved in the industry. Summary of the invention

[0003] The purpose of the embodiment of the present invention is to provide a semiconductor surface coating method, which can enhance the tensile stress of the semiconductor coating surface, thereby effectively preventing the semiconductor surface coating from becoming hard, brittle, and falling off.

[0004] In order to achieve the above object, an embodiment of the present invention provides a method for coating a semiconductor surface, comprising:

[0005] Pre-cleaning the semiconductor substrate;

[0006] In the vacuum chamber, the pre-cleaned semiconductor substrate is subjected to a staged coating process to deposit a plurality of silicon films on the surface of the semiconductor substrate in stages;

[0007] The surface of the semiconductor substrate is subjected to a coating treatment again to deposit a diamond-like coating on the surface of the silicon film.

[0008] Furthermore, the pre-cleaning treatment of the semiconductor substrate specifically includes:

[0009] The semiconductor substrate is ultrasonically cleaned using NMP solvent and IPA solvent;

[0010] Drying the semiconductor substrate after ultrasonic cleaning;

[0011] The dried semiconductor substrate is placed in a vacuum chamber and bombarded and cleaned.

[0012] Furthermore, the use of NMP solvent and IPA solvent to perform ultrasonic cleaning on the semiconductor substrate specifically includes:

[0013] The semiconductor substrate is immersed in NMP solvent for 40 to 45 minutes; wherein the temperature of the NMP solvent is 30 to 45°C;

[0014] Using deionized water to rinse the immersed semiconductor substrate;

[0015] The rinsed semiconductor substrate was ultrasonically cleaned for 30 minutes using IPA solvent as a cleaning solution.

[0016] Furthermore, placing the dried semiconductor substrate in a vacuum chamber and performing bombardment cleaning on the semiconductor substrate specifically includes:

[0017] The dried semiconductor substrate is placed in a vacuum chamber, evacuated and heated to a temperature of 100-150°C;

[0018] Argon gas is introduced into the vacuum chamber at a flow rate of 25 to 35 ml / min. When the gas pressure in the vacuum chamber reaches 10 to 15 Pa, the bias voltage is turned on to -1000 V, and the semiconductor substrate is bombarded and cleaned for 30 minutes using argon plasma, argon-oxygen mixed gas, argon-ethane mixed gas, nitrogen or helium.

[0019] Furthermore, the step of performing a film coating process on the pre-cleaned semiconductor substrate in stages to deposit a plurality of silicon films on the surface of the semiconductor substrate in stages specifically includes:

[0020] Argon gas was introduced into the vacuum chamber, and the vacuum degree was 1.0×10 -1 Under the operating conditions of Pa, ion source power of 2.0~2.5kW, negative bias voltage of 100~150V, and sputtering target power of 1.5~1.8kW, the pre-cleaned semiconductor substrate is coated in three stages by sputtering silicon target to deposit three layers of silicon film on the surface of the semiconductor substrate; wherein, the argon gas flow rate and deposition rate are adjusted respectively in different coating stages.

[0021] Furthermore, the thickness of the silicon film deposited in the first coating stage is 2.0-3.5 nm, the thickness of the silicon film deposited in the second coating stage is 2.0-2.5 nm, and the thickness of the silicon film deposited in the third coating stage is 1.0-2.0 nm.

[0022] Furthermore, in the first coating stage, the argon gas flow rate is 180 sccm, the deposition rate is 1.5 angstroms / second, and the thickness of the corresponding deposited silicon film is 3.5 nm.

[0023] Furthermore, in the second coating stage, the argon gas flow rate is 200 sccm, the deposition rate is 2.0 angstroms / second, and the thickness of the corresponding deposited silicon film is 2.5 nm.

[0024] Furthermore, in the third coating stage, the argon gas flow rate is 200 sccm, the deposition rate is 2.5 angstroms / second, and the thickness of the corresponding deposited silicon film is 2.0 nm.

[0025] Compared with the prior art, the embodiment of the present invention provides a method for coating a semiconductor surface. First, the semiconductor substrate is pre-cleaned; then, the pre-cleaned semiconductor substrate is subjected to a staged coating process in a vacuum chamber to deposit several layers of silicon film on the surface of the semiconductor substrate in stages; finally, the surface of the semiconductor substrate is coated again to deposit a diamond-like coating on the surface of the silicon film. The embodiment of the present invention can enhance the tensile stress of the semiconductor coating surface, thereby effectively preventing the semiconductor surface coating from becoming hard, brittle, or falling off. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flow chart of a preferred embodiment of a semiconductor surface coating method provided by the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this technical field without creative work are within the scope of protection of the present invention.

[0028] The present invention provides a method for coating a semiconductor surface. Figure 1 FIG. 1 is a flow chart of a preferred embodiment of a semiconductor surface coating method provided by the present invention, wherein the method comprises steps S11 to S13:

[0029] Step S11, pre-cleaning the semiconductor substrate;

[0030] Step S12, in a vacuum chamber, performing a phased coating process on the pre-cleaned semiconductor substrate to deposit a plurality of silicon films on the surface of the semiconductor substrate in phases;

[0031] Step S13, performing coating treatment on the surface of the semiconductor substrate again to deposit a diamond-like coating on the surface of the silicon film.

[0032] In the specific implementation, first, the surface of the semiconductor substrate to be coated is pre-cleaned; then, in a vacuum chamber, the semiconductor substrate after the pre-cleaning treatment is subjected to a staged coating treatment, and the silicon film is coated several times instead of being coated once, so as to form several layers of silicon film by corresponding deposition in stages on the surface of the semiconductor substrate; finally, the surface of the semiconductor substrate after the silicon film is coated is coated again to deposit a DLC (Diamond-like Carbon) coating on the surface of the silicon film, so that the DLC coating covers the surface of the silicon film.

[0033] It should be noted that, when depositing the DLC coating, the existing DLC ​​coating solution may be adopted, and the embodiment of the present invention does not make any specific limitation.

[0034] It should be noted that, in the embodiment of the present invention, the silicon film is plated several times instead of once, which can enhance the tensile stress on the surface of the plated film.

[0035] In another preferred embodiment, the pre-cleaning treatment of the semiconductor substrate specifically includes:

[0036] The semiconductor substrate is ultrasonically cleaned using NMP solvent and IPA solvent;

[0037] Drying the semiconductor substrate after ultrasonic cleaning;

[0038] The dried semiconductor substrate is placed in a vacuum chamber and bombarded and cleaned.

[0039] Specifically, in combination with the above-mentioned embodiments, when pre-cleaning the surface of the semiconductor substrate, NMP (N-methylpyrrolidone) solvent and IPA (isopropyl alcohol) solvent can be used to first perform ultrasonic cleaning on the surface of the semiconductor substrate, and then the semiconductor substrate after the ultrasonic cleaning is dried, and the dried semiconductor substrate is placed in a vacuum chamber, and the surface of the dried semiconductor substrate is bombarded and cleaned.

[0040] It should be noted that when the semiconductor substrate is dried, an existing drying treatment scheme may be adopted, and the embodiment of the present invention does not make any specific limitation.

[0041] As a preferred embodiment, the use of NMP solvent and IPA solvent to perform ultrasonic cleaning on the semiconductor substrate specifically includes:

[0042] The semiconductor substrate is immersed in NMP solvent for 40 to 45 minutes; wherein the temperature of the NMP solvent is 30 to 45°C;

[0043] Using deionized water to rinse the immersed semiconductor substrate;

[0044] The rinsed semiconductor substrate was ultrasonically cleaned for 30 minutes using IPA solvent as a cleaning solution.

[0045] Specifically, in combination with the above embodiments, when using NMP solvent and IPA solvent to perform ultrasonic cleaning on the surface of the semiconductor substrate, the semiconductor substrate can be first placed in an NMP solvent at a temperature of 30°C to 45°C and soaked for 40min to 45min. Thereafter, the surface of the soaked semiconductor substrate is rinsed with deionized water to rinse the surface of the semiconductor substrate clean. Then, the semiconductor substrate is placed in an IPA solvent and the IPA solvent is used as a cleaning solution. The surface of the semiconductor substrate after the rinse is ultrasonically cleaned for 30min.

[0046] Exemplarily, the temperature of the NMP solvent can be 30°C, 31°C, 32°C, 33°C, 34°C, 35°C, 36°C, 37°C, 38°C, 39°C, 40°C, 41°C, 42°C, 43°C, 44°C or 45°C, and can also be set according to actual needs, which is not specifically limited in the embodiments of the present invention.

[0047] Exemplarily, the immersion time of the semiconductor substrate in the NMP solvent can be 40 minutes, 41 minutes, 42 minutes, 43 minutes, 44 minutes or 45 minutes, and can also be set according to actual needs, which is not specifically limited in the embodiment of the present invention.

[0048] As a preferred solution, placing the dried semiconductor substrate in a vacuum chamber and performing bombardment cleaning on the semiconductor substrate specifically includes:

[0049] The dried semiconductor substrate is placed in a vacuum chamber, evacuated and heated to a temperature of 100-150°C;

[0050] Argon gas is introduced into the vacuum chamber at a flow rate of 25 to 35 ml / min. When the gas pressure in the vacuum chamber reaches 10 to 15 Pa, the bias voltage is turned on to -1000 V, and the semiconductor substrate is bombarded and cleaned for 30 minutes using argon plasma, argon-oxygen mixed gas, argon-ethane mixed gas, nitrogen or helium.

[0051] Specifically, in combination with the above embodiments, when the surface of the semiconductor substrate is bombarded and cleaned, the semiconductor substrate after the drying process can be first placed in a vacuum chamber, the vacuum chamber is evacuated, and heated to a temperature that is stable at 100°C to 150°C, and then argon (Ar) is introduced into the vacuum chamber at a flow rate of 25ml / min to 35ml / min. When the gas pressure in the vacuum chamber reaches 10Pa to 15Pa, a bias of -1000V is applied to the semiconductor substrate, and argon plasma, argon-oxygen mixed gas, argon-ethane mixed gas, nitrogen or helium are used to bombard and clean the surface of the semiconductor substrate for 30 minutes.

[0052] Exemplarily, the heating temperature in the vacuum chamber can be 100°C, 105°C, 110°C, 115°C, 120°C, 125°C, 130°C, 135°C, 140°C, 145°C or 150°C, and can also be set according to actual needs, which is not specifically limited in the embodiments of the present invention.

[0053] Exemplarily, the flow rate of argon gas introduced into the vacuum chamber can be 25ml / min, 26ml / min, 27ml / min, 28ml / min, 29ml / min, 30ml / min, 31ml / min, 32ml / min, 33ml / min, 34ml / min or 35ml / min, and can also be set according to actual needs, which is not specifically limited in the embodiments of the present invention.

[0054] Exemplarily, the air pressure in the vacuum chamber may be 10Pa, 11Pa, 12Pa, 13Pa, 14Pa or 15Pa, and may also be set according to actual needs, which is not specifically limited in the embodiment of the present invention.

[0055] In another preferred embodiment, the step of performing a film coating process on the pre-cleaned semiconductor substrate in stages to deposit a plurality of silicon films on the surface of the semiconductor substrate in stages specifically includes:

[0056] Argon gas was introduced into the vacuum chamber, and the vacuum degree was 1.0×10 -1 Under the operating conditions of Pa, ion source power of 2.0~2.5kW, negative bias voltage of 100~150V, and sputtering target power of 1.5~1.8kW, the pre-cleaned semiconductor substrate is coated in three stages by sputtering silicon target to deposit three layers of silicon film on the surface of the semiconductor substrate; wherein, the argon gas flow rate and deposition rate are adjusted respectively in different coating stages.

[0057] Specifically, in combination with the above embodiment, when the surface of the semiconductor substrate after the pre-cleaning treatment is subjected to the staged coating treatment, argon gas can be introduced into the vacuum chamber, and the vacuum degree in the vacuum chamber is 1.0×10 -1 Under the operating conditions of Pa, ion source power of 2.0kW~2.5kW, workpiece negative bias of 100V~150V, and sputtering target power of 1.5kW~1.8kW, the surface of the pre-cleaned semiconductor substrate is coated in three stages by sputtering silicon target, and in different coating stages, the argon gas flow rate and deposition rate are changed respectively to deposit three silicon films with different thicknesses on the surface of the semiconductor substrate.

[0058] Exemplarily, the value of the ion source power may be 2.0 kW, 2.1 kW, 2.2 kW, 2.3 kW, 2.4 kW or 2.5 kW, and may also be set according to actual needs, which is not specifically limited in the embodiment of the present invention.

[0059] Exemplarily, the value of the negative bias voltage of the workpiece can be 100V, 105V, 110V, 115V, 120V, 125V, 130V, 135V, 140V, 145V or 150V, and can also be set according to actual needs, which is not specifically limited in the embodiments of the present invention.

[0060] Exemplarily, the sputtering target power may be 1.5 kW, 1.6 kW, 1.7 kW or 1.8 kW, and may also be set according to actual needs, which is not specifically limited in the embodiment of the present invention.

[0061] As a preferred embodiment, the thickness of the silicon film deposited in the first coating stage is 2.0-3.5 nm, the thickness of the silicon film deposited in the second coating stage is 2.0-2.5 nm, and the thickness of the silicon film deposited in the third coating stage is 1.0-2.0 nm.

[0062] Specifically, in combination with the above embodiments, after the coating treatment in the first coating stage, the thickness of the first silicon film formed by the deposition is 2.0nm~3.5nm, after the coating treatment in the second coating stage, the thickness of the second silicon film formed by the deposition is 2.0nm~2.5nm, and after the coating treatment in the third coating stage, the thickness of the third silicon film formed by the deposition is 1.0nm~2.0nm.

[0063] Exemplarily, the thickness of the first layer of silicon film can be 2.0nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, 2.6nm, 2.7nm, 2.8nm, 2.9nm, 3.0nm, 3.1nm, 3.2nm, 3.3nm, 3.4nm or 3.5nm, and can also be set according to actual needs, which is not specifically limited in the embodiments of the present invention.

[0064] Exemplarily, the thickness of the second silicon film layer may be 2.0 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm or 2.5 nm, and may also be set according to actual needs, which is not specifically limited in the embodiment of the present invention.

[0065] Exemplarily, the thickness of the third silicon film can be 1.0nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm or 2.0nm, and can also be set according to actual needs, which is not specifically limited in the embodiment of the present invention.

[0066] As a preferred solution, in the first coating stage, the argon gas flow rate is 180 sccm, the deposition rate is 1.5 angstroms / second, and the thickness of the corresponding deposited silicon film is 3.5 nm.

[0067] Specifically, in combination with the above embodiment, in the first coating stage of silicon coating, the preferred parameters are: argon gas flow rate is 180 sccm, deposition rate is 1.5 angstroms / second, corresponding to a first silicon film thickness of 3.5 nm deposited on the surface of the semiconductor substrate.

[0068] As a preferred solution, in the second coating stage, the argon gas flow rate is 200 sccm, the deposition rate is 2.0 angstroms / second, and the thickness of the corresponding deposited silicon film is 2.5 nm.

[0069] Specifically, in combination with the above embodiment, in the second coating stage of the silicon coating, the preferred parameters are: argon gas flow rate is 200 sccm, deposition rate is 2.0 angstroms / second, and the thickness of the second silicon film deposited on the surface of the semiconductor substrate is 2.5 nm.

[0070] As a preferred solution, in the third coating stage, the argon gas flow rate is 200 sccm, the deposition rate is 2.5 angstroms / second, and the thickness of the corresponding deposited silicon film is 2.0 nm.

[0071] Specifically, in combination with the above embodiment, in the third coating stage of the silicon coating, the preferred parameters are: argon gas flow rate is 200 sccm, deposition rate is 2.5 angstroms / second, corresponding to a third silicon film thickness of 2.0 nm deposited on the surface of the semiconductor substrate.

[0072] It can be understood that after the coating process is completed, the first silicon film, the second silicon film, the third silicon film and the DLC coating are deposited in sequence on the surface of the semiconductor substrate, that is, the first silicon film is deposited on the surface of the semiconductor substrate, the second silicon film is deposited on the surface of the first silicon film, the third silicon film is deposited on the surface of the second silicon film, and the DLC coating is deposited on the surface of the third silicon film.

[0073] Through experimental tests, it is known that after the silicon film is plated on the surface of the semiconductor substrate in three steps a, b, and c, the tensile stress on the plated surface is enhanced from the original 1.5GPA~1.6GPA to 1.1GPA~4.0GPA. The specific test data are shown in Table 1.

[0074] Table 1 Working conditions and tensile stress data

[0075]

[0076] In combination with all the above embodiments, the implementation process of the present scheme is described below through the first specific embodiment, including: (1) placing the semiconductor substrate in an NMP solvent at a temperature of 30°C and soaking it for 40 minutes, then using deionized water to rinse the surface of the soaked semiconductor substrate, and then using IPA solvent as a cleaning solution to ultrasonically clean the surface of the rinsed semiconductor substrate for 30 minutes; (2) drying the semiconductor substrate after ultrasonic cleaning, placing the dried semiconductor substrate in a vacuum chamber, evacuating the vacuum chamber, and heating it to a temperature that is stable at 100°C, and then introducing argon gas into the vacuum chamber at a flow rate of 25 ml / min. When the air pressure in the vacuum chamber reaches 10 Pa, applying a bias of -1000 V to the semiconductor substrate, and bombarding and cleaning the surface of the semiconductor substrate for 30 minutes using argon plasma, argon-oxygen mixed gas, argon-ethane mixed gas, nitrogen or helium; (3) introducing argon gas into the vacuum chamber, and at a vacuum degree of 1.0×10 -1 Pa, ion source power of 2.0kW, negative bias voltage of 100V, and sputtering target power of 1.5kW, the semiconductor substrate after pre-cleaning treatment is coated in three stages by sputtering silicon target to deposit three layers of silicon film on the surface of the semiconductor substrate; wherein, in the first coating stage of silicon coating, the argon gas flow rate is 180sccm, the deposition rate is 1.5 angstroms / second, and the thickness of the first silicon film deposited on the surface of the semiconductor substrate is 3.5nm; in the second coating stage of silicon coating, the argon gas flow rate is 180sccm, the deposition rate is 1.5 angstroms / second, and the thickness of the first silicon film deposited on the surface of the semiconductor substrate is 3.5nm; During the coating stage, the argon gas flow rate is 200 sccm and the deposition rate is 2.0 angstroms per second, corresponding to a second silicon film having a thickness of 2.5 nm deposited on the surface of the semiconductor substrate. During the third coating stage of silicon coating, the argon gas flow rate is 200 sccm and the deposition rate is 2.5 angstroms per second, corresponding to a third silicon film having a thickness of 2.0 nm deposited on the surface of the semiconductor substrate. (4) The surface of the semiconductor substrate after silicon coating is subjected to coating treatment again to deposit a DLC coating on the surface of the silicon film.

[0077] In combination with all the above embodiments, the implementation process of the present scheme is described below through a second specific embodiment, including: (1) placing the semiconductor substrate in an NMP solvent at a temperature of 37°C and soaking it for 42 minutes, then using deionized water to rinse the surface of the soaked semiconductor substrate, and then using IPA solvent as a cleaning solution to ultrasonically clean the surface of the rinsed semiconductor substrate for 30 minutes; (2) drying the semiconductor substrate after ultrasonic cleaning, placing the dried semiconductor substrate in a vacuum chamber, evacuating the vacuum chamber, and heating it to a temperature that is stable at 125°C, and then introducing argon gas into the vacuum chamber at a flow rate of 28 ml / min. When the air pressure in the vacuum chamber reaches 12 Pa, applying a bias of -1000 V to the semiconductor substrate, and bombarding and cleaning the surface of the semiconductor substrate for 30 minutes using argon plasma, argon-oxygen mixed gas, argon-ethane mixed gas, nitrogen or helium; (3) introducing argon gas into the vacuum chamber, and at a vacuum degree of 1.0×10 -1 Under the operating conditions of 1.7 kW of ion source power, 2.2 kW of ion source power, 125 V of negative bias voltage, and 1.7 kW of sputtering target power, the semiconductor substrate after pre-cleaning treatment is subjected to coating treatment in three stages by sputtering silicon target, so as to deposit three layers of silicon film on the surface of the semiconductor substrate; wherein, in the first coating stage of silicon coating, the argon gas flow rate is 180 sccm, the deposition rate is 1.5 angstroms / second, and the thickness of the first silicon film deposited on the surface of the semiconductor substrate is 3.5 nm; in the second coating stage of silicon coating, the argon gas flow rate is 180 sccm, the deposition rate is 1.5 angstroms / second, and the thickness of the first silicon film deposited on the surface of the semiconductor substrate is 3.5 nm; During the coating stage, the argon gas flow rate is 200 sccm and the deposition rate is 2.0 angstroms per second, corresponding to a second silicon film having a thickness of 2.5 nm deposited on the surface of the semiconductor substrate. During the third coating stage of silicon coating, the argon gas flow rate is 200 sccm and the deposition rate is 2.5 angstroms per second, corresponding to a third silicon film having a thickness of 2.0 nm deposited on the surface of the semiconductor substrate. (4) The surface of the semiconductor substrate after silicon coating is subjected to coating treatment again to deposit a DLC coating on the surface of the silicon film.

[0078] In combination with all the above embodiments, the implementation process of the present scheme is described below through the third specific embodiment, including: (1) placing the semiconductor substrate in an NMP solvent at a temperature of 45°C and soaking it for 45 minutes, then using deionized water to rinse the surface of the soaked semiconductor substrate, and then using IPA solvent as a cleaning solution to ultrasonically clean the surface of the rinsed semiconductor substrate for 30 minutes; (2) drying the semiconductor substrate after ultrasonic cleaning, placing the dried semiconductor substrate in a vacuum chamber, evacuating the vacuum chamber, and heating it to a temperature stable at 150°C, and then introducing argon gas into the vacuum chamber at a flow rate of 35 ml / min. When the air pressure in the vacuum chamber reaches 15 Pa, applying a bias of -1000 V to the semiconductor substrate, and bombarding and cleaning the surface of the semiconductor substrate for 30 minutes using argon plasma, argon-oxygen mixed gas, argon-ethane mixed gas, nitrogen or helium; (3) introducing argon gas into the vacuum chamber, and at a vacuum degree of 1.0×10 -1 Under the operating conditions of 100 kW Pa, ion source power of 2.5 kW, negative bias voltage of 150 V, and sputtering target power of 1.8 kW, the semiconductor substrate after pre-cleaning treatment is subjected to coating treatment in three stages by sputtering a silicon target to deposit three layers of silicon film on the surface of the semiconductor substrate; wherein, in the first coating stage of silicon coating, the argon gas flow rate is 180 sccm, the deposition rate is 1.5 angstroms / second, and the thickness of the first silicon film deposited on the surface of the semiconductor substrate is 3.5 nm; in the second coating stage of silicon coating, the argon gas flow rate is 180 sccm, the deposition rate is 1.5 angstroms / second, and the thickness of the first silicon film deposited on the surface of the semiconductor substrate is 3.5 nm; During the coating stage, the argon gas flow rate is 200 sccm and the deposition rate is 2.0 angstroms per second, corresponding to a second silicon film having a thickness of 2.5 nm deposited on the surface of the semiconductor substrate. During the third coating stage of silicon coating, the argon gas flow rate is 200 sccm and the deposition rate is 2.5 angstroms per second, corresponding to a third silicon film having a thickness of 2.0 nm deposited on the surface of the semiconductor substrate. (4) The surface of the semiconductor substrate after silicon coating is subjected to coating treatment again to deposit a DLC coating on the surface of the silicon film.

[0079] In summary, the semiconductor surface coating method provided by the embodiment of the present invention firstly performs a pre-cleaning treatment on the semiconductor substrate; then, in a vacuum chamber, the pre-cleaned semiconductor substrate is subjected to a staged coating treatment to deposit and form a plurality of silicon films on the surface of the semiconductor substrate in stages; finally, the surface of the semiconductor substrate is subjected to a coating treatment again to deposit and form a diamond-like coating on the surface of the silicon film. The embodiment of the present invention can enhance the tensile stress on the surface of the semiconductor coating, thereby effectively preventing the semiconductor surface coating from becoming hard, brittle, or falling off.

[0080] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for coating a semiconductor surface, characterized in that: include: Pre-cleaning the semiconductor substrate; In the vacuum chamber, the pre-cleaned semiconductor substrate is subjected to a staged coating process to deposit a plurality of silicon films on the surface of the semiconductor substrate in stages; The surface of the semiconductor substrate is subjected to a coating treatment again to deposit a diamond-like coating on the surface of the silicon film.

2. The method for coating a semiconductor surface as claimed in claim 1, characterized in that: The pre-cleaning treatment of the semiconductor substrate specifically includes: The semiconductor substrate is ultrasonically cleaned using NMP solvent and IPA solvent; Drying the semiconductor substrate after ultrasonic cleaning; The dried semiconductor substrate is placed in a vacuum chamber and bombarded and cleaned.

3. The method for coating a semiconductor surface as claimed in claim 2, characterized in that: The use of NMP solvent and IPA solvent to perform ultrasonic cleaning on the semiconductor substrate specifically includes: The semiconductor substrate is immersed in NMP solvent for 40 to 45 minutes; wherein the temperature of the NMP solvent is 30 to 45°C; Using deionized water to rinse the immersed semiconductor substrate; The rinsed semiconductor substrate was ultrasonically cleaned for 30 minutes using IPA solvent as a cleaning solution.

4. The method for coating a semiconductor surface as claimed in claim 2, characterized in that: Placing the dried semiconductor substrate in a vacuum chamber and performing bombardment cleaning on the semiconductor substrate specifically includes: The dried semiconductor substrate is placed in a vacuum chamber, evacuated and heated to a temperature of 100-150°C; Argon gas is introduced into the vacuum chamber at a flow rate of 25 to 35 ml / min. When the gas pressure in the vacuum chamber reaches 10 to 15 Pa, the bias voltage is turned on to -1000 V, and the semiconductor substrate is bombarded and cleaned for 30 minutes using argon plasma, argon-oxygen mixed gas, argon-ethane mixed gas, nitrogen or helium.

5. The method for coating a semiconductor surface as claimed in claim 1, characterized in that: The step of performing a film coating process on the pre-cleaned semiconductor substrate in stages to deposit a plurality of silicon films on the surface of the semiconductor substrate in stages specifically includes: Argon gas was introduced into the vacuum chamber, and the vacuum degree was 1.0×10 -1 Under the operating conditions of Pa, ion source power of 2.0~2.5kW, negative bias voltage of 100~150V, and sputtering target power of 1.5~1.8kW, the pre-cleaned semiconductor substrate is coated in three stages by sputtering silicon target to deposit three layers of silicon film on the surface of the semiconductor substrate; wherein, the argon gas flow rate and deposition rate are adjusted respectively in different coating stages.

6. The method for coating a semiconductor surface as claimed in claim 5, characterized in that: The thickness of the silicon film deposited in the first coating stage is 2.0 to 3.5 nm, the thickness of the silicon film deposited in the second coating stage is 2.0 to 2.5 nm, and the thickness of the silicon film deposited in the third coating stage is 1.0 to 2.0 nm.

7. The method for coating a semiconductor surface as claimed in claim 5, characterized in that: In the first coating stage, the argon gas flow rate is 180 sccm, the deposition rate is 1.5 angstroms / second, and the thickness of the corresponding deposited silicon film is 3.5 nm.

8. The method for coating a semiconductor surface as claimed in claim 5, characterized in that: In the second coating stage, the argon gas flow rate is 200 sccm and the deposition rate is 2.0 angstroms / second, corresponding to a silicon film with a thickness of 2.5 nm.

9. The method for coating a semiconductor surface as claimed in claim 5, characterized in that: In the third coating stage, the argon gas flow rate is 200 sccm, the deposition rate is 2.5 angstroms / second, and the thickness of the corresponding deposited silicon film is 2.0 nm.

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