Silicon wafer bearing frame with supporting points

By designing a plate frame with brackets and mask steps in the silicon wafer bearing frame, the problem of the inability to coat the silicon wafer around the silicon wafer and the target material is wrapped around the silicon wafer in the prior art, and the coating efficiency and the conversion efficiency of solar cells are improved.

CN119506816APending Publication Date: 2025-02-25NAN TONG JIU FANG XIN CAI LIAO GU FEN YOU XIAN GONG SI
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Patent Information

Application Number
CN202411654105.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-19
Publication Date
2025-02-25

AI Technical Summary

Technical Problem

In the existing silicon wafer bearing frame design, the mask steps around the silicon wafer cause the ITO film to be unable to be coated in the 1mm wide area, which reduces the coating efficiency. At the same time, reducing the mask area will cause the target to wind over the silicon wafer, which will reduce the coating efficiency.

Method used

A silicon wafer bearing frame with support points is designed. There are support points distributed around the inner wall of the mounting frame. The support points are equipped with mask steps. The mask size of the mounting frame is larger than the size of the silicon wafer. The support points are located below the mounting frame to support the silicon wafer.

Benefits of technology

By increasing the effective coating area of ​​the mask area, the offset rate during the silicon wafer coating process is reduced, from 2.3‰ to less than 1‰, and the conversion efficiency of solar cells is improved by about 0.2%.

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Abstract

The invention discloses a silicon wafer bearing frame with supporting points, which comprises a bearing frame body, the bearing frame body is provided with a plurality of wafer placing frames (2), the supporting points (3) are distributed on the periphery of the inner wall of each wafer placing frame (2), each supporting point (3) is provided with a mask step, the size of the hollow part of each wafer placing frame is defined as the mask size, and the mask size of each wafer placing frame is larger than the size of a silicon wafer (1). According to the bearing frame body, a silicon wafer (1) is erected in the wafer placing frame (2) in the film coating process, the silicon wafer (1) is supported by the supporting points (3), a target material on the lower surface of the silicon wafer can be prevented from being wound to the position above the silicon wafer from a gap and plated on the upper surface of the silicon wafer, the deviation rate in the film coating process of the silicon wafer is reduced, and the film coating efficiency of the silicon wafer can be effectively improved.
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Description

Technical Field

[0001] The invention belongs to the technical field of vacuum coating equipment, and in particular relates to a silicon wafer carrying frame with supporting points. Background Art

[0002] Physical vapor deposition technology can not only deposit metal films and alloy films, but also compounds, ceramics, semiconductors, polymer films, etc. PVD technology can produce thin films with excellent properties, such as high hardness, wear resistance, corrosion resistance, etc. Physical vapor deposition (PVD) is a technology that converts solid materials into gaseous state through physical processes and then deposits them on the surface of the substrate to form a thin film. PVD mainly achieves material transfer and deposition through physical processes such as evaporation, sputtering, and arc evaporation. The vacuum evaporation silicon wafer carrier loads solar silicon wafers and circulates them in the process chambers of the evaporation equipment to complete the coating process. Therefore, the requirements for the carrier in the entire coating process are very high, and the quality of the carrier directly affects the quality of the silicon wafers in the subsequent process.

[0003] The existing silicon wafer carrier frame is designed with a mask step, that is, the size of the mask is smaller than the size of the silicon wafer. This results in the area within the mask step being unable to be coated with ITO film during the coating process of the silicon wafer. Currently, there is a 1mm wide area around the silicon wafer that cannot be coated with ITO film. This 1mm wide mask area greatly reduces the coating efficiency of the silicon wafer. In order to improve the coating efficiency of the silicon wafer, the mask area needs to be further reduced. However, when the mask area is reduced, the target material on the lower surface of the silicon wafer will be coated from the gap to the top of the silicon wafer and coated on the upper surface of the silicon wafer, which in turn reduces the coating efficiency of the silicon wafer. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to solve the deficiencies in the prior art and provide a silicon wafer carrying frame with supporting points.

[0005] Technical solution: A silicon wafer carrier frame with supporting points, including a carrier frame body, the carrier frame body is provided with multiple wafer placing frames, the inner walls of the wafer placing frames are distributed with supporting points, the supporting points are provided with mask steps, the size of the hollowed-out parts of the wafer placing frames is defined as the mask size, the mask size of the wafer placing frames is larger than the size of the silicon wafer, the carrier frame body places the silicon wafer on the wafer placing frames during the coating process, and the supporting points hold the silicon wafer.

[0006] A further improvement of the present invention is that the supporting frame body is made of metal material.

[0007] A further improvement of the present invention is that the material of the supporting frame body is stainless steel or titanium alloy.

[0008] A further improvement of the present invention is that the supporting frame body is made of non-metallic material.

[0009] A further improvement of the present invention is that the material of the supporting frame body is carbon fiber or PEEK‌‌.

[0010] A further improvement of the present invention is that the center distance between adjacent supporting points is between 30 mm and 70 mm.

[0011] A further improvement of the present invention is that the number of supporting points distributed around the inner wall of the film placing frame ranges from 4 to 16.

[0012] A further improvement of the present invention is that the chamfer size of the front side of the film placing frame is 1.5x20° to 2.5x40°, and the chamfer size of the back side of the film placing frame is 0.5x60° to 1x80°.

[0013] A further improvement of the present invention is that chamfered portions are provided at the four top corners of the wafer placing frame, the chamfered portions imitate the shape of the four corners of the silicon wafer, and the gap between the chamfered edges of the wafer placing frame and the edges of the silicon wafer is in the range of 0.1 to 0.3 mm.

[0014] A further improvement of the present invention is that the gap between the wafer placing frame and the silicon wafer is in the range of 0.1 to 0.3 mm, that is, the size of the mask of the wafer placing frame is larger than the size of the silicon wafer by 0.1 to 0.6 mm.

[0015] Compared with the prior art, the silicon wafer carrying frame with supporting points provided by the present invention achieves at least the following beneficial effects: The present invention is provided with a wafer placing frame, and supporting points are distributed around the inner wall of the wafer placing frame. The supporting points are provided with mask steps to achieve that the mask size is larger than the size of the silicon wafer. The bearing frame body holds the silicon wafer in the wafer placing frame during the coating process. The supporting points are located below the wafer placing frame and are used to hold the silicon wafer. The present invention can prevent the target material on the lower surface of the silicon wafer from going around the gap to the top of the silicon wafer and coating on the upper surface of the silicon wafer, and can also increase the proportion of effective coating on the back of the silicon wafer. Thereby reducing the offset rate during the silicon wafer coating process. The offset rate is an indicator used to measure the degree of discreteness relative to its mean. The offset rate during the silicon wafer coating process is reduced from 2.3‰ to less than 1‰. By increasing the effective coating ratio on the back of the silicon wafer, the conversion efficiency of the silicon wafers and the solar cells produced by using the present invention can be increased by 0.2%. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the assembly of the present invention; Figure 2 A schematic diagram of a whole bearing frame formed by multiple film placing frames; Figure 3 This is the enlarged view of point A; Figure 4 is a schematic diagram of the chamfered portion; Figure 5 It is a distribution position diagram of the support points of a single film placing frame; Figure 6 A cross-sectional view of the carrier frame.

[0017] In the figure: 1-silicon wafer; 2-wafer frame; 3-support point; 4-chamfered part. DETAILED DESCRIPTION

[0018] Various exemplary embodiments of the present invention are now described in detail. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, numerical expressions and numerical values ​​described in these embodiments do not limit the scope of the present invention. The following description of at least one exemplary embodiment is actually only illustrative and is not intended to be any limitation on the present invention and its application or use.

[0019] The techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0020] See also Figure 1-6 A silicon wafer carrier frame with supporting points includes a carrier frame body, the carrier frame body is provided with multiple wafer placing frames 2, the inner wall of the wafer placing frames 2 is distributed with supporting points 3, the supporting points 3 are provided with mask steps, the size of the hollow part of the wafer placing frame is defined as the mask size, the mask size of the wafer placing frame is larger than the size of the silicon wafer 1, the carrier frame body places the silicon wafer 1 in the wafer placing frame 2 during the coating process, and the supporting points 3 hold the silicon wafer 1.

[0021] A further improvement of the present invention is that the load-bearing frame body is made of metal material, can bear heavy loads, and has high structural strength and durability.

[0022] A further improvement of the present invention is that the material of the supporting frame body is stainless steel or titanium alloy. The stainless steel supporting frame has strong corrosion resistance, can remain stable in various environments, and is not easy to rust or corrode; the titanium alloy supporting frame has the characteristics of high strength, high toughness and corrosion resistance, and can remain stable in harsh environments.

[0023] A further improvement of the present invention is that the supporting frame body is made of non-metallic material.

[0024] A further improvement of the present invention is that the material of the supporting frame body is carbon fiber or PEEK. Carbon fiber has significant light weight and high strength characteristics, and PEEK has high strength, high modulus and good dimensional stability, and can maintain its performance under extreme conditions.

[0025] A further improvement of the present invention is that the center distance between adjacent supporting points 3 is between 30 mm and 70 mm.

[0026] A further improvement of the present invention is that the number of supporting points distributed around the inner wall of the film placing frame 2 ranges from 4 to 16.

[0027] A further improvement of the present invention is that the chamfer size of the front side of the film placing frame 2 is 1.5x20° to 2.5x40°, and the chamfer size of the back side of the film placing frame 2 is 0.5x60° to 1x80°.

[0028] A further improvement of the present invention is that chamfered portions 4 are provided at the four top corners of the wafer placing frame 2, and the chamfered portions 4 imitate the shape of the four corners of the silicon wafer, and the gap between the chamfered edges of the wafer placing frame 2 and the edges of the silicon wafer is in the range of 0.1 to 0.3 mm.

[0029] A further improvement of the present invention is that the gap between the wafer placing frame 2 and the silicon wafer 1 is in the range of 0.1 to 0.3 mm, that is, the size of the mask of the wafer placing frame is larger than the size of the silicon wafer in the range of 0.1 to 0.6 mm.

[0030] In summary, the present invention provides a silicon wafer support frame with support points, and support points 3 are distributed around the inner wall of the wafer frame 2. The support points 3 are provided with mask steps to achieve a mask size larger than the size of the silicon wafer 1. The support frame body supports the silicon wafer 1 in the wafer frame 2 during the coating process. The support points 3 are located below the wafer frame 2 and are used to support the silicon wafer 1. The present invention can prevent the target material on the lower surface of the silicon wafer from going around the gap to the top of the silicon wafer and coating on the upper surface of the silicon wafer, and can also increase the proportion of effective coating on the back of the silicon wafer. Thereby reducing the offset rate during the silicon wafer coating process. The offset rate is an indicator used to measure the degree of discreteness relative to its mean. The offset rate during the silicon wafer coating process is reduced from 2.3‰ to less than 1‰. By increasing the effective coating ratio on the back of the silicon wafer, the conversion efficiency of the silicon wafers and the solar cells produced by using the present invention can be increased by 0.2%.

[0031] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

Claims

1. A silicon wafer carrying frame with supporting points, characterized in that: The invention comprises a bearing frame body, wherein the bearing frame body is provided with a plurality of wafer placing frames (2), the inner walls of the wafer placing frames (2) are surrounded by supporting points (3), the supporting points (3) are provided with mask steps, the size of the hollowed-out portion of the wafer placing frames is defined as the mask size, the mask size of the wafer placing frames is larger than the size of the silicon wafer (1), the bearing frame body holds the silicon wafer (1) in the wafer placing frames (2) during the coating process, and the supporting points (3) hold the silicon wafer (1).

2. The silicon wafer carrying frame with supporting points according to claim 1, characterized in that: The supporting frame body is made of metal material.

3. The silicon wafer carrying frame with supporting points according to claim 2, characterized in that: The material of the supporting frame body is stainless steel or titanium alloy.

4. The silicon wafer carrying frame with supporting points according to claim 1, characterized in that: The supporting frame body is made of non-metallic material.

5. The silicon wafer carrying frame with supporting points according to claim 4, characterized in that: The material of the supporting frame body is carbon fiber or PEEK.

6. The silicon wafer carrying frame with supporting points according to claim 1, characterized in that: The center distance between adjacent support points (3) is between 30 mm and 70 mm.

7. The silicon wafer carrying frame with supporting points according to claim 1, characterized in that: The number of supporting points distributed around the inner wall of the film placing frame (2) ranges from 4 to 16.

8. The silicon wafer carrying frame with supporting points according to claim 1, characterized in that: The chamfer dimensions of the front side of the film placing frame (2) are 1.5x20° to 2.5x40°, and the chamfer dimensions of the back side of the film placing frame (2) are 0.5x60° to 1x80°.

9. A silicon wafer carrying frame with supporting points according to any one of claims 1 to 8, characterized in that: Chamfered portions (4) are provided at the four top corners of the wafer placing frame (2), and the chamfered portions (4) imitate the shape of the four corners of the silicon wafer. The clearance between the chamfered edges of the wafer placing frame (2) and the edges of the silicon wafer is in the range of 0.1 to 0.3 mm.

10. A silicon wafer carrying frame with supporting points according to any one of claims 1 to 8, characterized in that: The gap between the wafer placing frame (2) and the silicon wafer (1) is in the range of 0.1 to 0.3 mm, that is, the mask size of the wafer placing frame is larger than the size of the silicon wafer in the range of 0.1 to 0.6 mm.