Production of electroplated nickel-iron layer comprising titanium-copper seed layer

Abstract

The present disclosure relates to the manufacture of an electroplated nickel-iron layer comprising a titanium-copper seed layer. The layered structure includes: a silicon-based substrate including a substrate surface; a titanium-copper seed layer disposed on the substrate surface, where the titanium-copper seed layer includes a titanium layer and a copper layer, where the titanium layer is disposed on the substrate surface such that covalent bonds are formed between the titanium layer and the silicon of the silicon-based substrate, and where the copper layer is disposed directly on the titanium layer such that the titanium layer is disposed between the substrate surface and the copper layer; and a nickel-iron plating layer disposed directly on the copper layer of the titanium-copper seed layer such that the titanium-copper seed layer is disposed between the silicon-based substrate and the nickel-iron plating layer.

Description

Background Art

[0001] The seed layer is often used in pattern plating processes, such as electro-galvanic deposition (e.g., electroplating) of a metal layer. The seed layer can help to evenly distribute the current on the wafer to achieve uniform growth and correct lattice structure of the galvanically-deposited metal layer. The seed layer should provide good adhesion between the galvanically-deposited metal layer and the wafer, so that the galvanically-deposited metal layer can grow evenly on the wafer, and define a stable lattice structure of the galvanically-deposited metal layer. In order to enable the galvanically-deposited metal layer to grow evenly on the wafer, the seed layer should have a suitable conductivity so that the current can be evenly distributed in the seed layer during the galvanically-deposited process. Summary of the invention

[0002] In some implementations, the layered structure includes: a silicon-based substrate including a substrate surface; a titanium-copper seed layer disposed on the substrate surface, wherein the titanium-copper seed layer includes a titanium layer and a copper layer, wherein the titanium layer is disposed on the substrate surface so that a covalent bond is formed between the titanium layer and silicon of the silicon-based substrate, and wherein the copper layer is directly disposed on the titanium layer so that the titanium layer is disposed between the substrate surface and the copper layer; and a nickel-iron plating layer disposed directly on the copper layer of the titanium-copper seed layer so that the titanium-copper seed layer is disposed between the silicon-based substrate and the nickel-iron plating layer.

[0003] In some implementations, a magnetic sensor system includes: a magnetic sensor configured to generate a sensor signal in response to a magnetic field incident at the magnetic sensor; and a layered structure including: a silicon-based substrate including a substrate surface; a titanium-copper seed layer disposed on the substrate surface, wherein the titanium-copper seed layer includes a titanium layer and a copper layer, wherein the titanium layer is disposed on the substrate surface such that a covalent bond is formed between the titanium layer and silicon of the silicon-based substrate, and wherein the copper layer is directly disposed on the titanium layer such that the titanium layer is disposed between the substrate surface and the copper layer; and a nickel-iron plating layer disposed directly on the copper layer of the titanium-copper seed layer such that the titanium-copper seed layer is disposed between the silicon-based substrate and the nickel-iron plating layer, wherein the nickel-iron plating layer has a plating pattern configured to manipulate the magnetic field incident at the magnetic sensor.

[0004] In some implementations, a method of manufacturing an electroplated structure includes: providing a silicon-based substrate including a substrate surface; directly forming a titanium layer on the substrate surface, such that a covalent bond is formed between the titanium layer and silicon of the silicon-based substrate; directly forming a copper layer on the titanium layer, such that the titanium layer is disposed between the silicon-based substrate and the copper layer; and directly forming a nickel-iron plating layer on the copper layer by current deposition, such that the copper layer is disposed between the titanium layer and the nickel-iron plating layer.

[0005] In some implementations, a semiconductor device includes: a layered structure integrated in the semiconductor device, the layered structure including: a silicon-based substrate including a substrate surface; a titanium-copper seed layer arranged on the substrate surface, wherein the titanium-copper seed layer includes a titanium layer and a copper layer, wherein the titanium layer is arranged on the substrate surface so that a covalent bond is formed between the titanium layer and silicon of the silicon-based substrate, and wherein the copper layer is directly arranged on the titanium layer so that the titanium layer is arranged between the substrate surface and the copper layer; and a nickel-iron plating layer directly arranged on the copper layer of the titanium-copper seed layer so that the titanium-copper seed layer is arranged between the silicon-based substrate and the nickel-iron plating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Implementations are described herein with reference to the accompanying drawings.

[0007] Figure 1 is a cross-section of a layered structure according to one or more implementations.

[0008] Figures 2A-2D Example processes for fabricating electroplated structures are described in accordance with one or more implementations.

[0009] Figure 3A Magnetic sensor systems are described in accordance with one or more implementations.

[0010] Figure 3B Magnetic sensor systems are described in accordance with one or more implementations.

[0011] Figure 3C Magnetic sensor systems are described in accordance with one or more implementations. DETAILED DESCRIPTION

[0012] In the following, details are set forth to provide a more comprehensive explanation of example implementations. However, it will be apparent to those skilled in the art that these implementations may be practiced without these specific details. In other cases, well-known structures and devices are shown in block diagram form or schematic form rather than in detail to avoid obscuring the implementations. In addition, unless otherwise specified, the features of the different implementations described below may be combined with each other.

[0013] In addition, in the following description, equivalent or similar elements or elements having equivalent or similar functions are indicated by equivalent or similar reference numerals. Since the same or functionally equivalent elements are given the same reference numerals in the drawings, repeated descriptions of the elements having the same reference numerals may be omitted. Therefore, the descriptions provided for the elements having the same or similar reference numerals may be interchangeable.

[0014] The orientation of various elements in the figure is shown as an example, and the illustrated example can be rotated relative to the depicted orientation. The description provided herein and the subsequent claims relate to any structure having the relationship between various features, regardless of whether the structure is in the specific orientation of the accompanying drawings or is rotated relative to this orientation. Similarly, for ease of description, spatial relative terms are used herein, such as "top", "bottom", "below", "lower", "above", "upper", "middle", "left side" and "right side", to describe the relationship between an element and one or more other elements illustrated in the figures. In addition to the orientation depicted in the figures, spatial relative terms are intended to cover different orientations of elements, structures, and / or components in use or operation. Structures and / or components can be oriented (rotated 90 degrees or in other orientations) in other ways, and the spatial relative descriptors used in this article can be interpreted accordingly. In addition, in order to simplify the accompanying drawings, unless otherwise stated, the cross-sectional views in the accompanying drawings only show the features in the plane of the cross section, without showing the material behind the plane of the cross section.

[0015] It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected to or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0016] In the implementations described herein or shown in the accompanying drawings, any direct electrical connection or coupling (e.g., any connection or coupling without additional intermediate elements) may also be implemented through an indirect connection or coupling (e.g., a connection or coupling with one or more additional intermediate elements, or vice versa), as long as the general purpose of the connection or coupling (e.g., transmitting a certain signal or transmitting certain information) is substantially maintained. Features from different implementations may be combined to form other implementations. For example, unless otherwise stated, changes or modifications described with respect to one implementation in the implementation may also apply to other implementations.

[0017] As used herein, the terms "substantially" and "approximately" mean "within reasonable tolerances of manufacturing and measurement." For example, the terms "substantially" and "approximately" may be used herein to illustrate small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry without departing from aspects of the implementations described herein. For example, a resistor having an approximate resistance value may actually have a resistance within 5% of the approximate resistance value. As another example, a signal having an approximate signal value may actually have a signal value within 5% of the approximate signal value.

[0018] In the present disclosure, expressions including ordinal numbers, such as "first", "second", etc., can modify various elements. However, these elements are not limited by these expressions. For example, these expressions do not limit the order and / or importance of elements. On the contrary, these expressions are only used for the purpose of distinguishing elements from other elements. For example, although both are boxes, the first box and the second box indicate different boxes. For another example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can also be referred to as the first element.

[0019] Seed layers are commonly used in pattern plating processes, such as current deposition of metal layers (e.g., electroplating). The seed layer can help to evenly distribute current on the wafer to achieve uniform growth and correct lattice structure of the current deposited metal layer. The seed layer should meet three requirements: provide good adhesion between the current deposited metal layer and the wafer, so that the current deposited metal layer can grow evenly on the wafer, and define a stable lattice structure of the current deposited metal layer. In order to enable the current deposited metal layer to grow evenly on the wafer, the seed layer should have a suitable conductivity so that the current can be evenly distributed in the seed layer during the current deposition process. The uniform growth and stable lattice structure of the current deposited metal layer can contribute to the adhesion quality between the current deposited metal layer and the wafer. Better uniform growth and higher lattice structure stability can improve adhesion.

[0020] Soft magnetic alloys such as nickel-iron (NiFe) can have many uses in magnetic field applications. For example, nickel-iron can be used to provide magnetic field shielding, magnetic field focusing, and / or magnetic field redirection. The current solution for electroplating NiFe onto silicon (Si)-based substrates may not meet all of the above-mentioned seed layer requirements, or may be improved. For example, nickel-iron has a high tensile stress, which increases with the increase in the thickness of the nickel-iron layer. If sufficient adhesion is not achieved between the nickel-iron layer and the seed layer, the high tensile stress may cause the nickel-iron layer to separate from the seed layer. In other words, the life of the structure may be limited to the amount of time that the nickel-iron layer can remain adhered to the seed layer. Therefore, the thickness of the nickel-iron layer can be limited to the amount of tensile stress that the adhesion between the nickel-iron layer and the seed layer can tolerate. In some cases, the thickness of the nickel-iron layer must be kept less than 5 microns (μm), so that the tensile stress induced by the nickel-iron layer will not cause the adhesion between the nickel-iron layer and the seed layer to fail. This small thickness of the nickel-iron layer may limit practical applications that may benefit from the nickel-iron layer being bonded to a silicon-based substrate. Seed layers of NiCr, NiFe, TiWCu, Ti, and Ta are all insufficient in this regard.

[0021] Therefore, some implementations disclosed herein are related to a layered structure, which includes: a silicon-based substrate, including a substrate surface; a titanium-copper seed layer, arranged on the substrate surface; and a nickel-iron plating layer (e.g., an electroplated NiFe layer), which is directly arranged on the titanium-copper seed layer. The titanium-copper (TiCu) seed layer includes a titanium layer and a copper layer, wherein the titanium layer is arranged on the substrate surface of the silicon-based substrate, so that a covalent bond is formed between the titanium layer and the silicon of the silicon-based substrate. The copper layer is directly arranged on the titanium layer, so that the titanium layer is arranged between the substrate surface of the silicon-based substrate and the copper layer. The nickel-iron plating layer is directly arranged on the copper layer of the titanium-copper seed layer, so that the titanium-copper seed layer is arranged between the silicon-based substrate and the nickel-iron plating layer. The nickel-iron plating layer can be formed on the TiCu seed layer via a current deposition process.

[0022] The copper layer has a high electrical conductivity. Therefore, a uniform distribution of current in the TiCu seed layer can be achieved during the current deposition process. Therefore, a uniform current deposition of the nickel-iron coating onto the TiCu seed layer (e.g. onto the copper layer) can be achieved. Therefore, the adhesion strength between the nickel-iron coating and the copper layer is very high.

[0023] In addition, titanium forms very good adhesion with silicon. For example, due to the formation of a titanium-silicon phase layer (such as a titanium silicide layer or a titanium disilicide layer) at the interface where titanium contacts silicon, titanium establishes a firm connection with silicon. In other words, the covalent bond formed between the titanium layer and the silicon of the silicon-based substrate provides a high adhesion strength between the titanium layer and the silicon-based substrate. Therefore, the lattice structure of the titanium-silicon phase layer and the nickel-iron coating is very stable. For example, adhesion tests (such as adhesion tests using Sebastian five tensile testers) of different seed layer materials have confirmed a good and stable connection between titanium and silicon. The force required to destroy the connection between the bonding stamp and the pad on the seed layer surface is significantly higher in the case of having a TiCu seed layer than in the case of having a TiWCu, NiCr or NiFe seed layer. Furthermore, the experiments proved that for all the titanium-containing seed layer samples, only glue was detected on the surface of the bonding stamp after the experiment, while for other seed layer samples (e.g., with NiFe seed layer or NiCr seed layer), the metal elements of the corresponding seed layer were detected on the surface of the bonding stamp. In other words, titanium forms a stronger connection with silicon than a connection formed by another material with silicon.

[0024] Due to the strong adhesion between all adjacent layers of the layered structure, a nickel-iron plating layer having a thickness equal to or greater than 5 μm (e.g., between 5 μm-20 μm) can be formed without compromising the integrity of the adhesion between one or more of the layers of the layered structure. Therefore, a longer product life can be achieved, and a thicker NiFe layer having a thickness between 5 μm-20 μm formed on a silicon-based substrate can be used in additional applications where otherwise a NiFe layer having a thickness less than 5 μm on a silicon-based substrate would be impractical.

[0025] Figure 1 is a cross-section of a layered structure 100 according to one or more implementations. The layered structure 100 includes a silicon-based substrate 102 having a substrate surface 104, a titanium-copper (TiCu) seed layer 106 disposed on the substrate surface 104, and a nickel-iron plating layer 108 (e.g., an electroplated NiFe layer) disposed directly on the titanium-copper seed layer 106. The silicon-based substrate 102 may be a silicon layer or a silicon oxide (SiOx) layer.

[0026] The titanium-copper seed layer 106 includes a titanium (Ti) layer 110 and a copper (Cu) layer 112. The titanium layer 110 may be made of only titanium. The copper layer 112 may be made of only copper. The titanium layer 110 may be arranged on the substrate surface 104 of the silicon-based substrate 102, so that a covalent bond is formed between the titanium layer 110 and the silicon of the silicon-based substrate 102. For example, the titanium atoms of the titanium layer 110 and the silicon atoms of the silicon-based substrate 102 may be combined to form a titanium-silicon phase layer 114, such as titanium silicide or titanium disilicide, at the interface of the silicon-based substrate 102 and the titanium layer 110. The copper layer 112 may be arranged directly on the titanium layer 110, so that the titanium layer 110 is arranged between the substrate surface 104 of the silicon-based substrate 102 and the copper layer 112.

[0027] The nickel-iron plating layer 108 is disposed directly on the copper layer 112 of the titanium-copper seed layer 106, so that the titanium-copper seed layer 106 is disposed between the silicon-based substrate 102 and the nickel-iron plating layer 108. The nickel-iron plating layer 108 may be formed on the titanium-copper seed layer 106 via a current deposition process.

[0028] The thickness of the nickel-iron plating layer 108 may be 5 μm-20 μm. The thickness of the titanium layer 110 may be less than 350 nanometers (nm), and the thickness of the copper layer 112 may be 100 nm-350 nm. Thus, a thick nickel-iron plating layer 108 may be formed on the titanium-copper seed layer 106 without compromising the integrity of the adhesion between one or more of the layers of the layered structure 100.

[0029] In addition, the copper layer 112 can define the lattice structure of the nickel-iron coating. For example, due to the high electrical conductivity of the copper layer, a uniform distribution of current in the titanium-copper seed layer 106 can be achieved during the current deposition process. Therefore, uniform current deposition of the nickel-iron coating 108 onto the titanium-copper seed layer 106 (e.g., onto the copper layer 112) can be achieved, so that the nickel-iron coating 108 has a uniform lattice structure.

[0030] Due to the strong adhesion between all adjacent layers of the layered structure 100, a nickel-iron plating layer 108 having a thickness equal to or greater than 5 μm (e.g., between 5 μm-20 μm) can be formed without compromising the integrity of the adhesion between one or more of the layers of the layered structure 110. Therefore, a longer product life can be achieved, and a thicker NiFe layer having a thickness between 5 μm-20 μm formed on the silicon-based substrate 102 can be used in additional applications, otherwise a NiFe layer having a thickness less than 5 μm on the silicon-based substrate is not practical. For example, the layered structure 100 can be integrated in a semiconductor device (e.g., a semiconductor chip) and / or a magnetic field sensor system. In some implementations, the silicon-based substrate 102 can be a medium in which an integrated circuit is formed, including a plurality of circuit components (e.g., transistors, diodes, and / or other electronic components). In some implementations, the nickel-iron plating layer 108 can have a plating pattern that is configured to receive an initial magnetic field and focus the initial magnetic field so as to output a focused magnetic field having an enhanced field strength relative to the initial magnetic field. In some implementations, the nickel-iron plating layer 108 may have a plating pattern configured to attract a magnetic field so as to redirect at least a portion of the magnetic field away from the region, so that the field strength of the magnetic field in the region is reduced. In some implementations, the nickel-iron plating layer 108 may have a plating pattern configured to receive a magnetic field and redirect at least a portion of the magnetic field from an incoming direction to a redirecting direction, so that the field strength of the magnetic field in the redirecting direction is increased.

[0031] As indicated above, Figure 1 Other examples may be combined with Figure 1 The examples described are different.

[0032] Figure 2A-2D An example process for fabricating an electroplated structure is described according to one or more implementations. The electroplated structure may correspond to a combination of Figure 1 A layered structure 100 is described.

[0033] Figure 2A Illustrated process step 200A includes providing a silicon-based substrate 102 including a substrate surface 104 .

[0034] Figure 2BOther process steps 200B are described, including forming a titanium-copper seed layer 106 directly on the substrate surface 104 of the silicon-based substrate 102. Forming the titanium-copper seed layer 106 directly on the substrate surface 104 of the silicon-based substrate 102 may include forming a titanium layer 110 directly on the substrate surface 104, so that a covalent bond is formed between the titanium layer 110 and the silicon of the silicon-based substrate 102. Therefore, titanium atoms of the titanium layer 110 and silicon atoms of the silicon-based substrate 102 may be combined to form a titanium-silicon phase layer 114 at the interface of the silicon-based substrate 102 and the titanium layer 110. Forming the titanium-copper seed layer 106 directly on the substrate surface 104 of the silicon-based substrate 102 may also include forming a copper layer 112 directly on the titanium layer 110, so that the titanium layer 110 is disposed between the silicon-based substrate 102 and the copper layer 112.

[0035] The titanium layer 110 and the copper layer 112 may be formed by respective physical vapor deposition (PVD) processes. Each respective PVD process may include descumming and surface pre-cleaning prior to depositing the respective seed layer coating. The titanium and copper may be sputtered in separate chambers without vacuum break, or in one chamber with different targets.

[0036] Figure 2C Other process steps 200C are described, including forming a patterned resist layer 202 on the copper layer 112, and after forming the patterned resist layer 202 (e.g., a negative resist layer), directly forming the nickel-iron plated layer 108 on the copper layer 112 by galvanic deposition, so that the copper layer 112 is disposed between the titanium layer 110 and the nickel-iron plated layer 108. The nickel-iron plated layer 108 may be galvanically deposited by applying an electric current to the copper layer 112 while in an aqueous electrolyte solution.

[0037] The patterned resist layer 202 may have a pattern that covers a portion of the copper layer 112 and exposes the remaining portion of the copper layer 112. The patterning of the patterned resist layer 202 may be performed using a photolithography process. The patterning of the patterned resist layer 202 causes some areas of the copper layer 112 to be exposed for NiFe electroplating. Therefore, the nickel-iron plating layer 108 may be formed on the remaining (exposed) portion of the copper layer 112 by current deposition. Therefore, the nickel-iron plating layer 108 may have a pattern corresponding to the exposed area of ​​the copper layer 112 without the patterned resist layer 202. It is also possible to use other types of resists (e.g., positive resists).

[0038] Figure 2DOther process steps 200D are described, including removing the patterned resist layer 202 after forming the nickel-iron plating layer 108, and after removing the patterned resist layer 202, removing the copper layer 112 and the titanium layer 110 from the area not between the nickel-iron plating layer 108 and the silicon-based substrate 102. Therefore, only the portions of the copper layer 112 and the titanium layer 110 directly disposed between the nickel-iron plating layer 108 and the silicon-based substrate 102 (e.g., vertically disposed therebetween) may remain.

[0039] The patterned resist layer 202 may be removed by a resist removal process, such as using oxygen plasma and / or wet chemical resist stripping.

[0040] The copper layer 112 and the titanium layer 110 may be removed using a wet chemical (eg, phosphoric acid) or ion etching process, such as reactive ion etching with an inert gas in a chlorine or fluorine atmosphere, or ion beam etching with an inert gas alone.

[0041] As indicated above, Figure 2A-2D Other examples may be related to Figure 2A-2D Described differently.

[0042] Figure 3A A magnetic sensor system 300A according to one or more implementations is described. The magnetic sensor system 300A includes a substrate 302 and one or more magnetic sensors 304 formed on the substrate 302. Each magnetic sensor 304 may be a sensor unit configured to generate a corresponding sensor signal in response to a magnetic field incident at the magnetic sensor 304. The magnetic sensor system 300A may also include a combination of Figure 1 The layered structure 100 is described. Here, only the nickel-iron plating layer 108 (e.g., NiFe) of the layered structure 100 is shown. The nickel-iron plating layer 108 may have a plating pattern that is configured to manipulate the magnetic field incident at the magnetic sensor. For example, the nickel-iron plating layer 108 may have a plating pattern that is configured to focus the magnetic field onto one or more magnetic sensors 304. In other words, the nickel-iron plating layer 108 can receive the magnetic field and provide a focused magnetic field to the one or more magnetic sensors 304 so as to increase the magnetic field strength (e.g., magnetic flux density) at the one or more magnetic sensors 304.

[0043] Thus, one or more magnetic sensors 304 may be able to sense weaker magnetic fields that would not be possible without placing one or more magnetic sensors 304 very close to the magnetic field source of the magnetic field. For example, the layered structure 100 may be used in low current applications that inherently produce weak magnetic fields. Thus, one or more magnetic sensors 304 may be placed farther from the magnetic field source, which may relax the design constraints of the magnetic sensor system. Additionally or alternatively, the focused magnetic field may be better distinguished from noise and interference, thereby more accurately sensing the focused magnetic field.

[0044] As indicated above, Figure 3A Other examples may be combined with Figure 3A Described differently.

[0045] Figure 3B A magnetic sensor system 300B according to one or more implementations is described. The magnetic sensor system 300B includes a substrate 302 and one or more magnetic sensors 304 formed on the substrate 302. Each magnetic sensor 304 may be a sensor unit configured to generate a corresponding sensor signal in response to a magnetic field incident at the magnetic sensor 304. The magnetic sensor system 300B may also include a combination of Figure 1 The layered structure 100 described. Here, only the nickel-iron plating 108 (e.g., NiFe) of the layered structure 100 is shown. The nickel-iron plating 108 can have a plating pattern that is configured to manipulate the magnetic field incident at the magnetic sensor. For example, the nickel-iron plating 108 can have a plating pattern that is configured to redirect at least a portion of the magnetic field away from the one or more magnetic sensors 304. For example, the nickel-iron plating 108 can attract a portion of the magnetic field away from the one or more magnetic sensors 304, so that only a portion (e.g., a reduced portion) of the magnetic field passes through the one or more magnetic sensors 304. Therefore, the nickel-iron plating 108 can be used in applications that benefit from reducing strong magnetic fields to within the sensing range of one or more magnetic sensors 304, for example to avoid saturation.

[0046] As indicated above, Figure 3B Other examples may be combined with Figure 3B Described differently.

[0047] Figure 3C A magnetic sensor system 300C according to one or more implementations is described. The magnetic sensor system 300C includes a substrate 302 and one or more magnetic sensors 304 formed on the substrate 302. Each magnetic sensor 304 may be a sensor unit configured to generate a corresponding sensor signal in response to a magnetic field incident at the magnetic sensor 304. The magnetic sensor system 300C may also include a combination of Figure 1The layered structure 100 described herein is shown. Here, only the nickel-iron plating layer 108 (e.g., NiFe) of the layered structure 100 is shown. The nickel-iron plating layer 108 may have a plating pattern that is configured to manipulate the magnetic field incident at the magnetic sensor. For example, the nickel-iron plating layer 108 may have a plating pattern that is configured to redirect at least a portion of the magnetic field from the entry direction to the redirection direction, so that the field strength of the magnetic field in the redirection direction is increased. Therefore, the magnetic field can be redirected to align with the sensitive axis of one or more magnetic sensors 304, which can enable one or more magnetic sensors 304 to sense a magnetic field that was not initially aligned with the sensitive axis.

[0048] As indicated above, Figure 3C Other examples may be combined with Figure 3C Described differently.

[0049] The following provides an overview of some aspects of the disclosure:

[0050] Aspect 1: A layered structure comprising: a silicon-based substrate, comprising a substrate surface; a titanium-copper seed layer, arranged on the substrate surface, wherein the titanium-copper seed layer comprises a titanium layer and a copper layer, wherein the titanium layer is arranged on the substrate surface so that a covalent bond is formed between the titanium layer and the silicon of the silicon-based substrate, and wherein the copper layer is directly arranged on the titanium layer so that the titanium layer is arranged between the substrate surface and the copper layer; and a nickel-iron plating layer, directly arranged on the copper layer of the titanium-copper seed layer so that the titanium-copper seed layer is arranged between the silicon-based substrate and the nickel-iron plating layer.

[0051] Aspect 2: The layered structure according to aspect 1, wherein titanium atoms of the titanium layer and silicon atoms of the silicon-based substrate are combined to form a titanium-silicon phase layer at the interface between the silicon-based substrate and the titanium layer.

[0052] Aspect 3: The layered structure according to any one of Aspects 1 to 2, wherein the silicon-based substrate is a silicon substrate or a silicon oxide substrate.

[0053] Aspect 4: The layered structure according to any one of Aspects 1 to 3, wherein the thickness of the nickel-iron plating layer is 5 micrometers to 20 micrometers (μm).

[0054] Aspect 5: The layered structure according to aspect 4, wherein the thickness of the titanium layer is less than 350 nanometers (nm), and the thickness of the copper layer is 100 nm to 350 nm.

[0055] Aspect 6: The layered structure according to any one of aspects 1 to 5, wherein the copper layer defines a lattice structure of the nickel-iron plating layer.

[0056] Aspect 7: A layered structure according to any one of Aspects 1 to 6, wherein the nickel-iron plating layer has a plating pattern configured to receive an initial magnetic field and focus the initial magnetic field so as to output a focused magnetic field having an enhanced field strength relative to the initial magnetic field.

[0057] Aspect 8: The layered structure according to any one of aspects 1 to 7, wherein the nickel-iron plating layer has a plating pattern configured to attract the magnetic field so as to redirect at least a portion of the magnetic field away from the region, thereby reducing the field strength of the magnetic field in the region.

[0058] Aspect 9: A layered structure according to any one of Aspects 1 to 8, wherein the nickel-iron plating layer has a plating pattern configured to receive a magnetic field and redirect at least a portion of the magnetic field from an incoming direction to a redirecting direction, thereby increasing the field strength of the magnetic field in the redirecting direction.

[0059] Aspect 10: A magnetic sensor system comprising: a magnetic sensor configured to generate a sensor signal in response to a magnetic field incident at the magnetic sensor; and a layered structure comprising: a silicon-based substrate comprising a substrate surface; a titanium-copper seed layer arranged on the substrate surface, wherein the titanium-copper seed layer comprises a titanium layer and a copper layer, wherein the titanium layer is arranged on the substrate surface so that a covalent bond is formed between the titanium layer and silicon of the silicon-based substrate, and wherein the copper layer is directly arranged on the titanium layer so that the titanium layer is arranged between the substrate surface and the copper layer; and a nickel-iron plating layer directly arranged on the copper layer of the titanium-copper seed layer so that the titanium-copper seed layer is arranged between the silicon-based substrate and the nickel-iron plating layer, wherein the nickel-iron plating layer has a plating pattern configured to manipulate the magnetic field incident at the magnetic sensor.

[0060] Aspect 11: The magnetic sensor system according to aspect 10, wherein the nickel-iron plating layer has a plating pattern configured to focus the magnetic field onto the magnetic sensor.

[0061] Aspect 12: The magnetic sensor system according to any one of aspects 10 to 11, wherein the nickel-iron plating layer has a plating pattern configured to redirect at least a portion of the magnetic field away from the magnetic sensor.

[0062] Aspect 13: The magnetic sensor system according to any one of Aspects 10 to 12, wherein the nickel-iron plating layer has a plating pattern configured to redirect at least a portion of the magnetic field from an incoming direction to a redirecting direction, so that the field strength of the magnetic field in the redirecting direction is increased.

[0063] Aspect 14: A method for manufacturing an electroplated structure, the method comprising: providing a silicon-based substrate including a substrate surface; directly forming a titanium layer on the substrate surface, so that a covalent bond is formed between the titanium layer and silicon of the silicon-based substrate; directly forming a copper layer on the titanium layer, so that the titanium layer is arranged between the silicon-based substrate and the copper layer; and directly forming a nickel-iron plating layer on the copper layer by current deposition, so that the copper layer is arranged between the titanium layer and the nickel-iron plating layer.

[0064] Aspect 15: The method according to Aspect 14 further includes: before forming the nickel-iron plating layer, forming a patterned resist layer on the copper layer, wherein the patterned resist layer has a pattern covering a portion of the copper layer and exposing the remaining portion of the copper layer, and wherein the nickel-iron plating layer is formed on the remaining portion of the copper layer by current deposition.

[0065] Aspect 16: The method according to Aspect 15 further comprises: removing the patterned resist layer after forming the nickel-iron plating layer; and removing the copper layer and the titanium layer from the area not between the nickel-iron plating layer and the silicon-based substrate after removing the patterned resist layer.

[0066] Aspect 17: The method according to any one of Aspects 14 to 16, wherein the titanium layer and the copper layer are formed by physical vapor deposition (PVD).

[0067] Aspect 18: The method according to any one of Aspects 14 to 17, wherein titanium atoms of the titanium layer and silicon atoms of the silicon-based substrate are combined to form a titanium-silicon phase layer at the interface between the silicon-based substrate and the titanium layer.

[0068] Aspect 19: The method according to any one of Aspects 14 to 18, wherein the silicon-based substrate is a silicon substrate or a silicon oxide substrate.

[0069] Aspect 20: A method according to any one of Aspects 14 to 19, wherein the thickness of the nickel-iron plating layer is 5 micrometers to 20 micrometers (μm), and wherein the thickness of the titanium layer is less than 350 nanometers (nm), and the thickness of the copper layer is 100nm to 350nm.

[0070] Aspect 21: The method according to any one of aspects 14 to aspect 20, wherein the copper layer defines a lattice structure of the nickel-iron plating layer.

[0071] Aspect 22: A system configured to perform one or more operations according to one or more of Aspects 14 to 21.

[0072] Aspect 23: A semiconductor device, comprising: a layered structure, integrated in the semiconductor device, the layered structure comprising: a silicon-based substrate, comprising a substrate surface; a titanium-copper seed layer, arranged on the substrate surface, wherein the titanium-copper seed layer comprises a titanium layer and a copper layer, wherein the titanium layer is arranged on the substrate surface so that a covalent bond is formed between the titanium layer and the silicon of the silicon-based substrate, and wherein the copper layer is directly arranged on the titanium layer so that the titanium layer is arranged between the substrate surface and the copper layer; and a nickel-iron plating layer, directly arranged on the copper layer of the titanium-copper seed layer so that the titanium-copper seed layer is arranged between the silicon-based substrate and the nickel-iron plating layer.

[0073] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations may be made in light of the foregoing disclosure or may be acquired from practice of implementation.

[0074] Some implementations may be described herein in conjunction with thresholds. As used herein, "satisfying" a threshold may refer to a value greater than a threshold, more than a threshold, above a threshold, greater than or equal to a threshold, less than a threshold, less than a threshold, below a threshold, less than or equal to a threshold, equal to a threshold, etc.

[0075] As used herein, the term "component" is intended to be broadly understood as hardware, firmware, or a combination of hardware and software. The systems and / or methods described herein may be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods is not limited to implementation. Therefore, without reference to specific software codes, the operation and behavior of the systems and / or methods are described herein-it is understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0076] Any processing component can be implemented as a central processing unit (CPU) or other processor that reads and executes a software program from a non-transitory computer-readable recording medium such as a hard disk or a semiconductor memory device. For example, instructions can be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPLAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuit devices. Therefore, the term "processor" as used herein refers to any of the aforementioned structures or any other structure suitable for implementing the technology described herein. Software can be stored on a non-transitory computer-readable medium, so that the non-transitory computer-readable medium includes a program code or program algorithm stored thereon, and when executed, the program code or program algorithm causes the processor to perform the steps of the method via a computer program.

[0077] A controller including hardware may also perform one or more techniques of the present disclosure. A controller including one or more processors may use electrical signals and digital algorithms to perform its reception, analysis, and control functions, which may also include correction functions. This hardware, software, and firmware may be implemented in the same device or in separate devices to support the various techniques described in the present disclosure.

[0078] Signal processing circuitry and / or signal conditioning circuitry may receive one or more signals (e.g., measurement signals) in the form of raw measurement data from one or more components, and may derive other information from the measurement signals. "Signal conditioning" as used herein refers to manipulating an analog signal in such a way that the signal meets the requirements of further processing at the next level. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other process required to make the signal suitable for post-conditioning processing.

[0079] Although the specific combination of features is stated in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the implementation described herein. Many of these features can be combined in a manner that is not specifically stated in the claims and / or not specifically disclosed in the specification. For example, the disclosure includes the combination of each dependent claim in the claim set with each other independent claim in the claim set and each combination of multiple claims in the claim set. As used herein, the phrase "at least one" referring to the list of items refers to any combination of those items including a single member. As an example, "at least one of a, b, or c" is intended to cover any combination of a, b, c, a and b, a and c, b and c, and a and b and c and multiple identical elements (such as a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c or any other ordering of a, b and c.

[0080] In addition, it should be understood that the disclosure of multiple actions or functions disclosed in the specification or claims may not be interpreted as being in a specific order. Therefore, the disclosure of multiple actions or functions will not limit these actions or functions to a specific order unless these actions or functions are not interchangeable due to technical reasons. In addition, in some implementations, a single action may include or may be divided into multiple sub-actions. Unless explicitly excluded, these sub-actions may be included and may be part of the disclosure of the single action.

[0081] Unless explicitly described as key or necessary, the elements, actions, or instructions used herein should not be interpreted as key or necessary. In addition, as used herein, the articles "one" and "an" are intended to include one or more items, and can be used interchangeably with "one or more". Further, as used herein, the article "the" is intended to include one or more items quoted in conjunction with the article "the", and can be used interchangeably with "the one or more". Wherein only one item is intended, the phrase "only one", "single" or similar language is used. In addition, as used herein, the terms "has", "have", "having" etc. are intended to be open terms, and the elements modified by them are not limited (for example, "having" A elements can also have B). Further, unless otherwise explicitly stated, the phrase "based on" means "based on at least in part". As used herein, the term "multiple" can be replaced with "a plurality of", and vice versa. Furthermore, as used herein, the term "or" is intended to be inclusive when used in a series and may be used interchangeably with "and / or" unless expressly stated otherwise (eg, when used in conjunction with "either" or "only one").

Claims

1. A layered structure comprising: A silicon-based substrate, including a substrate surface; a titanium-copper seed layer disposed on the surface of the substrate, wherein the titanium-copper seed layer comprises a titanium layer and a copper layer, wherein the titanium layer is disposed on the substrate surface so that covalent bonds are formed between the titanium layer and silicon of the silicon-based substrate, and wherein the copper layer is disposed directly on the titanium layer, such that the titanium layer is disposed between the substrate surface and the copper layer; and A nickel-iron plated layer is disposed directly on the copper layer of the titanium-copper seed layer, so that the titanium-copper seed layer is disposed between the silicon-based substrate and the nickel-iron plated layer. 2 . The layered structure according to claim 1 , wherein titanium atoms of the titanium layer and silicon atoms of the silicon-based substrate are combined to form a titanium-silicon phase layer at an interface between the silicon-based substrate and the titanium layer. The layered structure according to claim 1 , wherein the silicon-based substrate is a silicon substrate or a silicon oxide substrate.

4. The layered structure according to claim 1, wherein the nickel-iron coating has a thickness of 5 micrometers to 20 micrometers (μm).

5. The layered structure of claim 4, wherein the titanium layer has a thickness of less than 350 nanometers (nm), and the copper layer has a thickness of 100 nm to 350 nm.

6. The layered structure of claim 1, wherein the copper layer defines a lattice structure of the nickel-iron coating.

7. The layered structure according to claim 1, wherein the nickel-iron plating layer has a plating pattern, and the plating pattern is configured to receive an initial magnetic field and focus the initial magnetic field so as to output a focused magnetic field with an enhanced field strength relative to the initial magnetic field.

8. The layered structure of claim 1, wherein the nickel-iron plating has a plating pattern configured to attract a magnetic field so as to redirect at least a portion of the magnetic field away from a region such that a field strength of the magnetic field in the region is reduced.

9. The layered structure of claim 1, wherein the nickel-iron plating layer has a plating pattern configured to receive a magnetic field and redirect at least a portion of the magnetic field from an incoming direction to a redirecting direction, thereby increasing the field strength of the magnetic field in the redirecting direction.

10. A magnetic sensor system comprising: a magnetic sensor configured to generate a sensor signal in response to a magnetic field incident at the magnetic sensor; as well as Layered structure, including: A silicon-based substrate, including a substrate surface; a titanium-copper seed layer disposed on the surface of the substrate, wherein the titanium-copper seed layer comprises a titanium layer and a copper layer, wherein the titanium layer is disposed on the substrate surface so that covalent bonds are formed between the titanium layer and silicon of the silicon-based substrate, and wherein the copper layer is disposed directly on the titanium layer, such that the titanium layer is disposed between the substrate surface and the copper layer; and A nickel-iron plated layer is disposed directly on the copper layer of the titanium-copper seed layer, so that the titanium-copper seed layer is disposed between the silicon-based substrate and the nickel-iron plated layer, wherein the nickel-iron plated layer has a plating pattern, and the plating pattern is configured to manipulate the magnetic field incident at the magnetic sensor. 11 . The magnetic sensor system of claim 10 , wherein the nickel-iron plating layer has a plating pattern configured to focus the magnetic field onto the magnetic sensor. 12 . The magnetic sensor system of claim 10 , wherein the nickel-iron plating has a plating pattern configured to redirect at least a portion of the magnetic field away from the magnetic sensor.

13. The magnetic sensor system of claim 10, wherein the nickel-iron plating layer has a plating pattern configured to redirect at least a portion of the magnetic field from an incoming direction to a redirecting direction, so that a field strength of the magnetic field in the redirecting direction is increased.

14. A method for manufacturing an electroplated structure, the method comprising: providing a silicon-based substrate including a substrate surface; forming a titanium layer directly on the surface of the substrate so that covalent bonds are formed between the titanium layer and silicon of the silicon-based substrate; forming a copper layer directly on the titanium layer so that the titanium layer is disposed between the silicon-based substrate and the copper layer; as well as A nickel-iron plating layer is formed directly on the copper layer by galvanic deposition, so that the copper layer is arranged between the titanium layer and the nickel-iron plating layer.

15. The method according to claim 14, further comprising: Before forming the nickel-iron plating layer, a patterned resist layer is formed on the copper layer, wherein the patterned resist layer has a pattern covering a portion of the copper layer and exposing a remaining portion of the copper layer, and wherein the nickel-iron plated layer is formed on the remaining portion of the copper layer by the current deposition.

16. The method according to claim 15, further comprising: After forming the nickel-iron plating layer, removing the patterned resist layer; as well as After removing the patterned resist layer, the copper layer and the titanium layer are removed from a region not between the nickel-iron plated layer and the silicon-based substrate.

17. The method of claim 14, wherein the titanium layer and the copper layer are formed by physical vapor deposition (PVD). 18 . The method of claim 14 , wherein titanium atoms of the titanium layer and silicon atoms of the silicon-based substrate are combined to form a titanium-silicon phase layer at an interface of the silicon-based substrate and the titanium layer. The method according to claim 14 , wherein the silicon-based substrate is a silicon substrate or a silicon oxide substrate.

20. The method according to claim 14, wherein the thickness of the nickel-iron coating is 5 micrometers to 20 micrometers (μm), and The thickness of the titanium layer is less than 350 nanometers (nm), and the thickness of the copper layer is 100 nm-350 nm.

21. The method of claim 14, wherein the copper layer defines a lattice structure of the nickel-iron coating.

22. A semiconductor device comprising: A layered structure is integrated in the semiconductor device, the layered structure comprising: A silicon-based substrate, including a substrate surface; a titanium-copper seed layer disposed on the surface of the substrate, wherein the titanium-copper seed layer comprises a titanium layer and a copper layer, wherein the titanium layer is disposed on the substrate surface so that covalent bonds are formed between the titanium layer and silicon of the silicon-based substrate, and wherein the copper layer is disposed directly on the titanium layer, such that the titanium layer is disposed between the substrate surface and the copper layer; and A nickel-iron plated layer is disposed directly on the copper layer of the titanium-copper seed layer, so that the titanium-copper seed layer is disposed between the silicon-based substrate and the nickel-iron plated layer.

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