CMOS fluxgate sensor

Abstract

The invention relates to the field of current detection, in particular to a CMOS (Complementary Metal Oxide Semiconductor) fluxgate sensor, which comprises an inductance coil for generating a corresponding magnetic field according to a magnetic field generated by a cable through which to-be-detected current passes, so that the magnetic flux tends to be zero, the two ends of the inductance coil are connected with a driving tube for amplifying voltage and a transmission tube for transmitting the exchanged voltage to the driving tube in a one-to-one correspondence mode, the driving tube is connected with a fifth NMOS tube, and a source electrode of the fifth NMOS tube is connected with a differential amplification circuit and a first comparator capable of turning off the fifth NMOS tube. The differential amplification circuit is connected with an MCU circuit which samples and quantifies the amplified voltage and outputs the voltage, and first diodes which allow reverse current to pass through are connected in parallel between the source electrode and the drain electrode of the driving tube, the source electrode and the drain electrode of the transmission tube and the source electrode and the drain electrode of the fifth NMOS tube, so that when the states of the driving tube, the transmission tube and the fifth NMOS tube are switched, the reverse current passes through the first diodes. The circuit enables the current in the main path to flow through the diodes connected in parallel, thereby reducing the possibility that the driving tube, the transmission tube and the fifth NMOS tube are damaged.

Description

Technical Field

[0001] The present application relates to the field of current detection, and in particular to a CMOS fluxgate sensor. Background Art

[0002] In order to detect the current in the circuit in real time, fluxgate sensors are often used. That is, the wire of the current to be measured passes through the magnetic core of the sensor to detect the current.

[0003] For example, a signal processing system for wide-range closed-loop fluxgate current detection with publication number CN117907674A obtains a compensation current when the magnetic flux is zero and combines it with the corresponding number of coil turns to calculate the current to be measured.

[0004] Regarding the above-mentioned related technologies, multiple transistors are used in the current signal to digital signal module to amplify the sampled voltage. During the transistor state switching process, the coil is prone to generate excessive voltage or current, which can easily damage the transistor. Summary of the invention

[0005] In order to reduce the possibility of transistor damage, the present application provides a CMOS fluxgate sensor.

[0006] A CMOS fluxgate sensor provided in the present application adopts the following technical solution.

[0007] A CMOS fluxgate sensor comprises an inductor coil which generates a corresponding magnetic field according to the magnetic field generated by a cable through which a current to be measured passes so as to make the magnetic flux tend to zero, a driving tube for amplifying a voltage and a transmission tube for transmitting the exchanged voltage to the driving tube are connected one by one at both ends of the inductor coil, the driving tube is connected to a fifth NMOS tube, the source of the fifth NMOS tube is connected to a differential amplifier circuit and a first comparator capable of turning off the fifth NMOS tube, the differential amplifier circuit is connected to an MCU circuit for sampling and quantizing the amplified voltage and outputting the voltage, and a first diode for reverse current to pass is connected in parallel between the source and drain of each of the driving tube, the transmission tube and the fifth NMOS tube.

[0008] By adopting the above technical solution, when the states of the driving tube, the transmission tube and the fifth NMOS tube are switched, the circuit will make the current in the main path freewheel through the parallel diode to reduce the possibility of the driving tube, the transmission tube and the fifth NMOS tube being subjected to excessive voltage or current, and reduce the possibility of damage to the driving tube, the transmission tube and the fifth NMOS tube.

[0009] Optionally, the driving tube includes a group of upper driving branches connected in series with the inductor coil and a group of lower driving branches connected in parallel with the inductor coil, and the transmission tube includes an upper transmission branch connected to the upper driving branch and a lower transmission branch connected to the lower driving branch.

[0010] By adopting the above technical solution, the current in the circuit is shared, the burden of the single upper driving branch pipe and the lower driving branch pipe is reduced, and the possibility of damage to the driving pipe is reduced.

[0011] Optionally, the upper driving branch includes a first PMOS tube and a second PMOS tube, and the lower driving branch includes a first NMOS tube and a second NMOS tube, the source of the second PMOS tube is connected to the power supply voltage and the drain is connected to the input end of the inductor coil, the drain of the first NMOS tube is connected to the output end of the inductor coil and the source is connected to the drain of the fifth NMOS tube, the source of the first PMOS tube is connected to the source of the second PMOS tube and the drain is connected to the output end of the inductor coil, the drain of the second NMOS tube is connected to the input end of the inductor coil and the source is connected to the drain of the fifth NMOS tube; The upper transmission branch includes a third PMOS tube and a fourth PMOS tube, and the lower transmission branch includes a third NMOS tube and a fourth NMOS tube. The source of the third PMOS tube is connected to the gate of the first PMOS tube and the drain is connected to the drain of the second PMOS tube. The source of the fourth PMOS tube is connected to the gate of the second PMOS tube and the drain is connected to the output end of the inductor coil. The drain of the third NMOS tube is connected to the drain of the second PMOS tube and the source is connected to the gate of the first NMOS tube. The drain of the fourth NMOS tube is connected to the output end of the inductor coil and the source is connected to the gate of the second NMOS tube.

[0012] By adopting the above technical solution, the voltage in the circuit can be shared and the current can be controlled more accurately, which also helps to increase the current capacity and improve the overall stability of the circuit.

[0013] Optionally, the gate of the third PMOS tube and the gate of the fourth PMOS tube are connected to a second diode, the cathode of the second diode is connected to the power supply voltage, the gate of the third NMOS tube and the gate of the fourth NMOS tube are connected to a third diode, the anode of the third diode is grounded, a fifth resistor is connected in series between the second diode and the third diode, the input end of the fifth resistor is connected to the gate of the third PMOS tube and the gate of the fourth PMOS tube, and the output end of the fifth resistor is connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube.

[0014] By adopting the above technical solution, a stable bias voltage is provided for the upper transmission branch pipe and the lower transmission branch pipe.

[0015] Optionally, a ninth resistor is connected to the output end of the inductor coil, and a fifth capacitor is connected in series between the ninth resistor and the MCU circuit.

[0016] By adopting the above technical solution, the ECLK clock signal is transmitted to the MCU circuit as a timing signal for triggering ADC sampling in the MCU circuit.

[0017] Optionally, the second diode is connected in parallel with a third capacitor, and the third diode is connected in parallel with a fourth capacitor.

[0018] By adopting the above technical solution, the crosstalk of the source-drain switching clock of the transmission tube to the bias voltage provided to the upper transmission branch tube and the lower transmission branch tube is reduced, thereby reducing the impact on the overall circuit working performance.

[0019] Optionally, the source of the fifth NMOS tube is connected to an eleventh resistor connected to the ground, the differential amplifier circuit includes a sixth resistor connected to the source of the fifth NMOS tube, a second comparator having a negative input terminal connected to the sixth resistor, a seventh resistor connected to the positive input terminal of the second comparator and connected to the reference voltage, and an eighth resistor connected in parallel to the negative input terminal and the output terminal of the second comparator, and the relationship between the compensation current Is, the sampling voltage Vcs and the output voltage Vout is: Vcs=Is Rshunt Vout=R8 / R6 Vcs+Vref Wherein, Rshunt is the resistance value of the eleventh resistor, R8 is the resistance value of the eighth resistor, R6 is the resistance value of the sixth resistor, and Vref is the reference voltage value input to the positive input terminal of the second comparator.

[0020] By adopting the above technical solution, the value of the compensation current is obtained and then the current to be measured is obtained through corresponding calculation.

[0021] Optionally, a fourth resistor connected to a power supply voltage is connected to the output terminal of the first comparator.

[0022] By adopting the above technical solution, it is ensured that the output end of the comparator can maintain a stable low-level state when outputting a low level, thereby improving the anti-interference ability of the comparator output.

[0023] Optionally, the positive input terminal of the first comparator is connected to a grounded tenth resistor, the tenth resistor is connected in parallel with a second capacitor, and the positive input terminal of the first comparator is connected to a third resistor connected to a reference voltage.

[0024] Optionally, the negative input terminal of the first comparator is connected to a grounded second resistor and a first capacitor, and the negative input terminal of the first comparator is connected to a first resistor connected to the source of the fifth NMOS tube.

[0025] By adopting the above technical solution, the input terminal of the first comparator is prevented from being suspended, the fluctuation of the input potential of the first comparator is reduced, and the circuit stability is improved.

[0026] In summary, the present application includes at least the following beneficial effects.

[0027] The overall circuit structure is simple and easy to implement, while having high detection accuracy and reducing the possibility of transistor damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram showing the circuit principle of the present application, and the direction of the compensation current Is is shown by a dotted line with an arrow; Figure 2 It is a timing diagram of each key node of this application.

[0029] Explanation of the reference numerals: 2, driving tube; 3, transmission tube; 5, differential amplifier circuit; 52, MCU circuit. DETAILED DESCRIPTION

[0030] The present application is further described in detail below in conjunction with the accompanying drawings.

[0031] The present application embodiment discloses a CMOS fluxgate sensor, referring to Figure 1 , including an inductor L that generates a corresponding magnetic field according to the magnetic field generated by the cable through which the current to be measured passes, so that the magnetic flux tends to zero, and the two ends of the inductor L are connected to a driving tube 2 and a transmission tube 3 in a one-to-one correspondence, the driving tube 2 amplifies the voltage in the circuit, and the transmission tube 3 is used to transmit the exchanged voltage to the driving tube 2. The driving tube 2 is connected to a fifth NMOS tube N5, and the fifth NMOS tube N5 is connected to a differential amplifier circuit 5 that amplifies the sampling voltage Vcs. The output end of the differential amplifier circuit 5 is connected to an MCU circuit 52, and the sampling voltage Vcs is amplified by a proportional operational amplifier and then given to the ADC in the MCU circuit 52 for sampling and quantization to obtain an output voltage Vout.

[0032] Reference Figure 1, the fifth NMOS transistor N5 is connected to the first comparator comp1, the negative input terminal of the first comparator comp1 is connected to the source of the fifth NMOS transistor N5, the positive input terminal of the first comparator comp1 is connected to the third resistor R3, the third resistor R3 is connected to the reference voltage, the output terminal of the first comparator comp1 is connected to the gate of the fifth NMOS transistor N5, so that when the output voltage of the first comparator comp1 jumps from a high level to a low level (maintaining a low level pulse width of about 1us), the corresponding low level will cause the fifth NMOS transistor N5 to be turned off. In addition, the positive input terminal of the first comparator comp1 is connected to the grounded tenth resistor R10, the tenth resistor R10 is connected in parallel with the second capacitor C2, and the negative input terminal of the first comparator comp1 is connected to the first resistor R1, the first resistor R1 is connected to the source of the fifth NMOS transistor N5, and the negative input terminal of the first comparator comp1 is connected to the grounded second resistor 34 and the first capacitor 35. At the same time, the output terminal of the first comparator comp1 is connected to the fourth resistor R4 connected to the power supply voltage, so that the first comparator comp1 can work stably.

[0033] Reference Figure 1 , the fifth NMOS transistor N5 is connected to an eleventh resistor R11 connected to ground. The differential amplifier circuit 5 includes a second comparator comp2, a negative input terminal of the second comparator comp2 is connected to a sixth resistor R6, the sixth resistor R6 is connected to the source of the fifth NMOS transistor N5, a positive input terminal of the second comparator comp2 is connected to a seventh resistor R7, an eighth resistor R8 is connected in parallel to the negative input terminal and the output terminal of the second comparator comp2, and the relationship between the compensation current Is, the sampling voltage Vcs and the output voltage Vout is as follows.

[0034] Vcs=Is Rshunt Vout=R8 / R6 Vcs+Vref Wherein, Rshunt is the resistance value of the eleventh resistor R11, R8 is the resistance value of the eighth resistor R8, R6 is the resistance value of the sixth resistor R6, and Vref is the reference voltage value input to the positive input terminal of the second comparator comp2. According to the above formula, the compensation current Is can be calculated from the output voltage Vout, and the current to be measured can be calculated according to the number of turns of the corresponding inductor L to realize the current detection function.

[0035] Reference Figure 1 The driving tube 2 includes a group of upper driving branches 55 connected in series with the inductor coil L and a group of lower driving branches 56 connected in parallel with the inductor coil L. The transmission tube 3 includes an upper transmission branch 57 electrically connected to the upper driving branch 55 and a lower transmission branch 58 electrically connected to the lower driving branch 56.

[0036] Reference Figure 1The upper driving branch 55 includes a first PMOS tube P1 and a second PMOS tube P2, and the lower driving branch 56 includes a first NMOS tube N1 and a second NMOS tube N2. The source of the second PMOS tube P2 is connected to the power supply voltage and the drain is connected to the input end of the inductor L. The drain of the first NMOS tube N1 is connected to the output end of the inductor L and the source is connected to the drain of the fifth NMOS tube N5. The source of the first PMOS tube P1 is connected to the source of the second PMOS tube P2 and the drain is connected to the output end of the inductor L. The drain of the second NMOS tube N2 is connected to the input end of the inductor L and the source is connected to the drain of the fifth NMOS tube N5.

[0037] Reference Figure 1 The upper transmission branch 57 includes a third PMOS tube P3 and a fourth PMOS tube P4, and the lower transmission branch 58 includes a third NMOS tube N3 and a fourth NMOS tube N4. The source of the third PMOS tube P3 is connected to the gate of the first PMOS tube P1 and the drain is connected to the drain of the second PMOS tube P2. The source of the fourth PMOS tube P4 is connected to the gate of the second PMOS tube P2 and the drain is connected to the output end of the inductor L. The drain of the third NMOS tube N3 is connected to the drain of the second PMOS tube P2 and the source is connected to the gate of the first NMOS tube N1. The drain of the fourth NMOS tube N4 is connected to the output end of the inductor L and the source is connected to the gate of the second NMOS tube N2.

[0038] Reference Figure 1 and Figure 2 A first diode D1 for reverse current to pass through is connected in parallel between the source and drain of each of the driving tube 2, the transmission tube 3 and the fifth NMOS tube N5, so that when the states of the driving tube 2, the transmission tube 3 and the fifth NMOS tube N5 are switched, the circuit will make the current in the main path freewheeling through the first parallel diode D1.

[0039] Reference Figure 1 The gate of the third PMOS tube P3 and the gate of the fourth PMOS tube P4 are connected to the second diode D2, the cathode of the second diode D2 is connected to the power supply voltage, the gate of the third NMOS tube N3 and the gate of the fourth NMOS tube N4 are connected to the third diode D3, the anode of the third diode D3 is grounded, a fifth resistor R5 is connected in series between the second diode D2 and the third diode D3, the input end of the fifth resistor R5 is connected to the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube P4, and the output end of the fifth resistor R5 is connected to the gate of the third NMOS tube N3 and the gate of the fourth NMOS tube N4, so that the upper transmission branch 57 and the lower transmission branch 58 obtain a fixed bias voltage.

[0040] Reference Figure 1 and Figure 2The inductor L is connected in series with a ninth resistor R9, and the ninth resistor R9 is connected in series with a fifth capacitor C5 connected to the MCU circuit 52, so that the ECLK clock signal is given to the MCU circuit 52 as a timing signal to trigger ADC sampling.

[0041] Reference Figure 1 The second diode D2 is connected in parallel with a third capacitor C3, and the third diode D3 is connected in parallel with a fourth capacitor C4 to reduce the source-drain switching clock crosstalk of the upper transmission branch 57 and the lower transmission branch 58 to the bias voltage.

[0042] The implementation principle of a CMOS fluxgate sensor of the embodiment of the present application is as follows: when the current in the inductor coil L gradually increases and reaches saturation, the voltage at the negative input terminal of the first comparator comp1 reaches the flip threshold, and the output voltage of the first comparator comp1 will jump from a high level to a low level, and the low level will cause the fifth NMOS tube N5 to turn off. In order to maintain the original current, the current in the inductor coil L will generate a reverse induced electromotive force (the voltage value is swapped), and then the swapped voltage value will be transmitted to the driver tube 2 through the transmission tube 3, so that the working state of the driver tube 2 is switched. After the circuit is stable, it will self-oscillate at a fixed frequency.

[0043] The sampling voltage Vcs is related to the magnitude of the current to be measured. After being amplified by a proportional operational amplifier, the sampling voltage Vcs is given to the ADC in the MCU circuit 52 for sampling and quantization. The ECLK clock signal is used as a timing signal to trigger sampling.

[0044] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A CMOS fluxgate sensor, characterized in that: The invention comprises an inductor coil which generates a corresponding magnetic field according to the magnetic field generated by a cable through which a current to be measured passes, so that the magnetic flux tends to zero; two ends of the inductor coil are connected one by one with a driving tube (2) for amplifying the voltage and a transmission tube (3) for transmitting the replaced voltage to the driving tube (2); the driving tube (2) is connected with a fifth NMOS tube; the source of the fifth NMOS tube is connected with a differential amplifier circuit (5) and a first comparator capable of shutting down the fifth NMOS tube; the differential amplifier circuit (5) is connected with an MCU circuit (52) for sampling and quantizing the amplified voltage and outputting the voltage; and a first diode for passing a reverse current is connected in parallel between the source and drain of each of the driving tube (2), the transmission tube (3) and the fifth NMOS tube.

2. A CMOS fluxgate sensor according to claim 1, characterized in that: The driving tube (2) comprises a group of upper driving branch tubes (55) connected in series with the inductor coil and a group of lower driving branch tubes (56) connected in parallel with the inductor coil, and the transmission tube (3) comprises an upper transmission branch tube (57) connected to the upper driving branch tube (55) and a lower transmission branch tube (58) connected to the lower driving branch tube (56).

3. A CMOS fluxgate sensor according to claim 2, characterized in that: The upper drive branch (55) comprises a first PMOS tube and a second PMOS tube, and the lower drive branch (56) comprises a first NMOS tube and a second NMOS tube, the source of the second PMOS tube is connected to the power supply voltage and the drain is connected to the input end of the inductor coil, the drain of the first NMOS tube is connected to the output end of the inductor coil and the source is connected to the drain of the fifth NMOS tube, the source of the first PMOS tube is connected to the source of the second PMOS tube and the drain is connected to the output end of the inductor coil, the drain of the second NMOS tube is connected to the input end of the inductor coil and the source is connected to the drain of the fifth NMOS tube; The upper transmission branch (57) includes a third PMOS tube and a fourth PMOS tube, and the lower transmission branch (58) includes a third NMOS tube and a fourth NMOS tube, the third PMOS tube source is connected to the first PMOS tube gate and the drain is connected to the second PMOS tube drain, the fourth PMOS tube source is connected to the second PMOS tube gate and the drain is connected to the inductor coil output end, the third NMOS tube drain is connected to the second PMOS tube drain and the source is connected to the first NMOS tube gate, the fourth NMOS tube drain is connected to the inductor coil output end and the source is connected to the second NMOS tube gate.

4. A CMOS fluxgate sensor according to claim 3, characterized in that: The third PMOS tube gate and the fourth PMOS tube gate are connected to a second diode, the cathode of the second diode is connected to the power supply voltage, the third NMOS tube gate and the fourth NMOS tube gate are connected to a third diode, the anode of the third diode is grounded, a fifth resistor is connected in series between the second diode and the third diode, the input end of the fifth resistor is connected to the third PMOS tube gate and the fourth PMOS tube gate, and the output end of the fifth resistor is connected to the third NMOS tube gate and the fourth NMOS tube gate.

5. A CMOS fluxgate sensor according to claim 4, characterized in that: The output end of the inductor coil is connected to a ninth resistor, and a fifth capacitor is connected in series between the ninth resistor and the MCU circuit (52).

6. A CMOS fluxgate sensor according to claim 5, characterized in that: The second diode is connected in parallel with a third capacitor, and the third diode is connected in parallel with a fourth capacitor.

7. The CMOS fluxgate sensor according to claim 1, characterized in that: The source of the fifth NMOS tube is connected to an eleventh resistor connected to the ground. The differential amplifier circuit (5) comprises a sixth resistor connected to the source of the fifth NMOS tube, a second comparator having a negative input terminal connected to the sixth resistor, a seventh resistor connected to the positive input terminal of the second comparator and connected to a reference voltage, and an eighth resistor connected in parallel to the negative input terminal and the output terminal of the second comparator. The relationship between the compensation current Is, the sampling voltage Vcs and the output voltage Vout is: Vcs=Is Rshunt Vout=R8 / R6 Vcs+Vref Wherein, Rshunt is the resistance value of the eleventh resistor, R8 is the resistance value of the eighth resistor, R6 is the resistance value of the sixth resistor, and Vref is the reference voltage value input to the positive input terminal of the second comparator.

8. The CMOS fluxgate sensor according to claim 1, characterized in that: A fourth resistor connected to a power supply voltage is connected to the output terminal of the first comparator.

9. The CMOS fluxgate sensor according to claim 1, characterized in that: The positive input terminal of the first comparator is connected to a grounded tenth resistor, the tenth resistor is connected in parallel with a second capacitor, and the positive input terminal of the first comparator is connected to a third resistor connected to a reference voltage.

10. The CMOS fluxgate sensor according to claim 9, characterized in that: The negative input terminal of the first comparator is connected to a grounded second resistor and a first capacitor, and the negative input terminal of the first comparator is connected to a first resistor connected to the source of the fifth NMOS tube.

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