Method and device for detecting impedance interval of printed circuit board and storage medium

Abstract

The invention discloses a method and equipment for detecting an impedance interval of a printed circuit board and a storage medium. The method comprises the following steps: positioning a to-be-tested target circuit in the printed circuit board; the target line is provided with a line interval with to-be-tested impedance; positioning a first bonding pad and a second bonding pad matched with the line interval in the printed circuit board; determining a communication link which takes the first bonding pad as a communication starting point, passes through the target line and takes the second bonding pad as a communication ending point; transmitting the test signal in the communication link to acquire a transmission performance parameter for the communication link; and generating an impedance interval of the line interval according to the communication link and the transmission performance parameter. According to the embodiment, when the impedance of the circuit is detected in a cross-layer mode in the printed circuit board, the impedance interval where the circuit interval is located is corrected, the accuracy of positioning the circuit interval with the impedance to be tested in the impedance curve can be improved, and the impedance fault phenomenon during coverage of cross-layer is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductors, and in particular to a method, a device and a storage medium for detecting an impedance range of a printed circuit board. Background Art

[0002] A printed circuit board (PCB) is usually a multi-layer structure, in which the same impedance specification is designed to connect across layers and to components to achieve signal transmission.

[0003] When producing printed circuit boards, the Coupon simulation test is used according to the requirements of the standard to detect the impedance of a certain line section in the multilayer board structure, and the line section is marked in the impedance curve displayed on the oscilloscope to locate the impedance quality of the multilayer board structure.

[0004] However, if Figure 1 As shown in the figure, when the impedance crosses the layer, the positioning accuracy of the line section is low, and the oscilloscope shows that the impedance curve ( Figure 1 The line sections divided by the curves in the middle and lower layers ( Figure 1 The area between the two dotted lines in the figure shows an impedance fault phenomenon across layers. Summary of the invention

[0005] In view of this, the present invention provides a method, a device and a storage medium for detecting an impedance range of a printed circuit board, so as to improve the accuracy of detecting an impedance range across layers of the printed circuit board.

[0006] A first aspect of the present invention provides a method for detecting an impedance interval of a printed circuit board, comprising:

[0007] Locating a target circuit to be tested in a printed circuit board; a circuit section having an impedance to be tested in the target circuit;

[0008] Positioning a first pad and a second pad matching the circuit section in the printed circuit board; wherein the first pad is located on the first layer board structure of the printed circuit board;

[0009] Determine a communication link having the first pad as a communication starting point, passing through the target line and having the second pad as a communication end point;

[0010] Transmitting a test signal in the communication link to collect transmission performance parameters of the communication link;

[0011] An impedance interval of the line interval is generated according to the communication link and the transmission performance parameter.

[0012] A second aspect of the present invention provides a device for detecting an impedance interval of a printed circuit board, comprising:

[0013] A target circuit positioning module is used to locate a target circuit to be tested in a printed circuit board; the target circuit has a circuit section with an impedance to be tested;

[0014] A pad positioning module, used for positioning a first pad and a second pad matching the circuit section in the printed circuit board; wherein the first pad is located in the first layer board structure of the printed circuit board;

[0015] A communication link determination module, used to determine a communication link with the first pad as a communication starting point, passing through the target line and with the second pad as a communication end point;

[0016] A transmission performance parameter acquisition module, used to transmit a test signal in the communication link to acquire transmission performance parameters of the communication link;

[0017] An impedance interval generating module is used to generate an impedance interval of the line interval according to the communication link and the transmission performance parameter.

[0018] A third aspect of the present invention provides an electronic device, the electronic device comprising:

[0019] at least one processor; and

[0020] a memory communicatively connected to the at least one processor; wherein,

[0021] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the method for detecting impedance intervals on a printed circuit board as described in the first aspect above.

[0022] A fourth aspect of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method for detecting impedance intervals on a printed circuit board as described in the first aspect above.

[0023] A fifth aspect of the present invention provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the method for detecting impedance intervals on a printed circuit board as described in the first aspect above is implemented.

[0024] In this embodiment, a target circuit to be tested is located in a printed circuit board; a circuit section having an impedance to be tested is located in the target circuit; a first pad and a second pad matching the circuit section are located in the printed circuit board; wherein the first pad is located in the first layer board structure of the printed circuit board; a communication link is determined with the first pad as the communication starting point, passing through the target circuit and the second pad as the communication end point; a test signal is transmitted in the communication link to collect transmission performance parameters for the communication link; and an impedance section of the circuit section is generated based on the communication link and the transmission performance parameters. In this embodiment, when detecting the impedance of a circuit across layers in a printed circuit board, the impedance section of the circuit section where the impedance to be tested is located is corrected based on the properties of the communication line itself and the performance parameters when transmitting signals, which can improve the accuracy of positioning the circuit section of the impedance to be tested in the impedance curve and avoid the impedance fault phenomenon when covering the cross-layer.

[0025] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 This is an example of a cross-layer impedance curve displayed on an oscilloscope.

[0028] Figure 2 This is a flow chart of a method for detecting an impedance range of a printed circuit board provided in Embodiment 1 of the present invention.

[0029] Figure 3 It is a structural schematic diagram of a printed circuit board provided in Embodiment 1 of the present invention.

[0030] Figure 4 It is a structural schematic diagram of a device for detecting impedance range of a printed circuit board provided by Embodiment 2 of the present invention.

[0031] Figure 5 It is a structural schematic diagram of an electronic device provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can cover sequential implementations other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] Embodiment 1

[0035] See also Figure 2 , shows a flow chart of a method for detecting an impedance range of a printed circuit board provided by a first embodiment of the present invention, the method can be performed by a device for detecting an impedance range of a printed circuit board, the device for detecting an impedance range of a printed circuit board can be implemented in the form of hardware and / or software, and the device for detecting an impedance range of a printed circuit board can be configured in an electronic device. Figure 2 As shown, the method includes:

[0036] Step 201: Locate a target circuit to be tested in a printed circuit board.

[0037] In practical applications, printed circuit boards have multi-layer structures, such as Figure 2 As shown, a target circuit 312 of impedance to be tested can be located in the first-layer board structure and / or non-first-layer board structure of the printed circuit board. The target circuit 312 can be a circuit in a single non-first-layer board structure, or a cross-layer circuit in the first-layer board structure and n (n is a positive integer) non-first-layer board structures, and this embodiment is not limited to this.

[0038] Among them, the target line has a line interval with an impedance to be tested. The line interval is usually represented by a first quantile as a test starting point and a second quantile as a test end point, that is, [Ratio1, Ratio2]. For example, the line interval is [30%, 70%], [50%, 70%], and so on.

[0039] Step 202: Position a first pad and a second pad matching the circuit area in the printed circuit board.

[0040] In this embodiment, if Figure 2 As shown, the first pad 301 and the second pad 302 matching the line section of the impedance to be tested in the target line 312 can be positioned in the printed circuit board according to the direction of the line section of the impedance to be tested in the target line 312 .

[0041] The first pad 301 is located on the first layer of the printed circuit board so that an instrument (especially a probe of the instrument) can be connected to the first pad 301 to test the impedance of the line section in the target line 312 .

[0042] In addition, the second solder pad 302 may be located on the first layer structure of the printed circuit board, or may be located on a non-first layer structure of the printed circuit board, which is not limited in this embodiment.

[0043] In a specific implementation, a test start point (eg, 30%) and a test end point (eg, 70%) are determined in the line section.

[0044] like Figure 2 As shown, a through hole to which the target line 312 is connected and which is connected to the test starting point is located in the printed circuit board as the first target hole 321 .

[0045] A first pad 301 directly or indirectly connected to the first target hole 321 is positioned in the first layer board structure of the printed circuit board, that is, there may be no other pads between the first pad 301 and the first target hole 321 or there may be other pads between the first pad 301 and the first target hole 321 .

[0046] Two through holes connected to the target line 312 and connected to the test end point are located in the printed circuit board as the second target hole 322 .

[0047] The second pad 302 directly or indirectly connected to the second target hole 322 is positioned in any layer structure of the printed circuit board, that is, there may be no other pads between the second pad 302 and the second target hole 322 or there may be other pads between the second pad 302 and the second target hole 322 .

[0048] Step 203: Determine a communication link that takes the first pad as a communication start point, passes through the target line, and has the second pad as a communication end point.

[0049] In this embodiment, if Figure 2 As shown, a complete communication link can be constructed with the first pad 301 as the communication starting point, passing through the target line 312 and the second pad 302 as the communication end point.

[0050] In a specific implementation, the first auxiliary circuit 311 between the first pad 301 and the first target hole 321 may be positioned in a first layer board structure and / or a non-first layer board structure of the printed circuit board.

[0051] The second auxiliary circuit 313 between the second pad 302 and the second target hole 322 is positioned in the first layer board structure and / or the non-first layer board structure of the printed circuit board.

[0052] A communication link is determined which takes the first pad 301 as the communication starting point, passes through the first auxiliary line 311, the target line 312, the second auxiliary line 313 in sequence, and takes the second pad 302 as the communication end point.

[0053] Further, in the case where there are multiple communication links, for each communication link, the sum of the length of the first auxiliary line and the length of the second auxiliary line is calculated as the total link length.

[0054] The total link lengths of the various communication links are compared to determine that the communication link with the smallest total link length is valid, the communication link with the smallest total link length is retained, and the communication links with non-smallest total link lengths are filtered out.

[0055] In this way, the proportion of the target route in the communication link can be increased as much as possible, and the accuracy of the impedance interval of the positioning line interval can be improved.

[0056] Step 204: Transmit a test signal in the communication link to collect transmission performance parameters of the communication link.

[0057] In this embodiment, a tool such as inplan or SI9000 may be used to transmit a test signal in a communication link, during which transmission performance parameters of the communication link are collected.

[0058] In a specific implementation, a test signal may be transmitted in a communication link to collect a first time delay for a first auxiliary line, a second time delay for a target line, and a third time delay for a second auxiliary line as transmission performance parameters.

[0059] Step 205: Generate an impedance interval of the line interval according to the communication link and transmission performance parameters.

[0060] In practical applications, the test principle of time domain reflection is used to incorporate the properties of the communication link itself and the transmission performance parameters into the calculation, so that the impedance interval of the line section can be generated before testing the impedance, which is conducive to the accurate reading of the impedance.

[0061] In one embodiment of the present invention, step 205 may include the following steps:

[0062] Step 2051: Calculate the total time domain index according to the first auxiliary line and the first delay, the target line and the second delay, the second auxiliary line and the third delay.

[0063] In this embodiment, the testing principle of time domain reflection is used to calculate the total time domain index of the entire communication link according to the first auxiliary line and the first delay, the target line and the second delay, the second auxiliary line and the third delay.

[0064] For example, on one hand, the total number of through holes between the first pad and the second pad may be counted in the communication link, and the fourth delay set for the through holes may be queried.

[0065] On the other hand, the length of the first auxiliary line, the length of the target line, and the length of the second auxiliary line may be queried.

[0066] The product between the length of the first auxiliary line and the first delay, the product between the length of the target line and the second delay, the product between the length of the second auxiliary line and the second delay, and the product between the total number and the preset fourth delay are added to obtain a total time domain indicator.

[0067] Step 2052: Calculate the first sub-time domain index according to the test starting point of the line section based on the first auxiliary line and the first delay, the target line and the second delay.

[0068] In this embodiment, the test principle of time domain reflection is used to calculate the first sub-time domain index according to the test starting point of the line section of the first auxiliary line and the first delay, the target line and the second delay.

[0069] Exemplarily, on one hand, the number of first segments of the through hole between the first pad and the test start point of the line section can be counted in the communication link to query the fourth delay set for the through hole.

[0070] On the other hand, the length of the first auxiliary line and the length of the target line can be queried, and the first quantile (such as 30%, 50%, etc.) of the test starting point of the line section in the target line can be determined.

[0071] The product of the length of the first auxiliary line and the first delay, the product of the length of the target line, the second delay and the first quantile, and the product of the first segment number and the preset fourth delay are added to obtain a first sub-time domain indicator.

[0072] Step 2053: Calculate the second sub-time domain index for the test endpoint of the line section according to the first auxiliary line and the first delay, the target line and the second delay.

[0073] In this embodiment, the test principle of time domain reflection is used to calculate the second sub-time domain index according to the test end point of the line section based on the first auxiliary line and the first delay, the target line and the second delay.

[0074] Exemplarily, on one hand, the number of second segments of the through hole between the second pad and the test end point of the line section can be counted in the communication link to query the fourth delay set for the through hole.

[0075] Generally, the sum of the first segment quantity of the through holes and the second segment quantity of the through holes is the total quantity of the through holes.

[0076] On the other hand, the length of the second auxiliary line and the length of the target line can be queried, and the second quantile (such as 70%) of the test end point of the line section in the target line can be determined.

[0077] The product of the length of the first auxiliary line and the first delay, the product of the length of the target line, the second delay and the second quantile, and the product of the second segment number and the preset fourth delay are added to obtain a second sub-time domain indicator.

[0078] Step 2054: Calculate the ratio between the first sub-time domain index and the total time domain index as the first time domain ratio of the test starting point of the line section.

[0079] In this embodiment, the ratio between the first sub-time domain index and the total time domain index may be calculated as the first time domain ratio of the test starting point of the line section.

[0080] Exemplarily, the first time domain ratio can be expressed as: (a*t a +b*t b *Ratio1+d*t i ) / (a*t a +b*t b +c*t c +T*t i ), where a is the length of the first auxiliary line, b is the length of the target line, c is the length of the second auxiliary line, T is the total number of through holes, d is the number of first segments of the through holes, t a is the first delay, t b is the second delay, t c is the third delay, t i is the fourth delay, and Ratio1 is the first quantile.

[0081] Step 2055: Calculate the ratio between the second sub-time domain index and the total time domain index as the second time domain ratio of the test end point of the line section.

[0082] In this embodiment, the ratio between the second sub-time domain index and the total time domain index may be calculated as the second time domain ratio of the test end point of the line section.

[0083] Exemplarily, the second time domain ratio can be expressed as: (a*t a +b*t b *Ratio2+e*t i ) / (a*t a +b*t b +c*t c +T*t i ), where a is the length of the first auxiliary line, b is the length of the target line, c is the length of the second auxiliary line, T is the total number of through holes, e is the number of second segments of the through holes, t a is the first delay, t b is the second delay, t c is the third delay, t i is the fourth delay, and Ratio2 is the second quantile.

[0084] Step 2056: Combine the first time domain ratio and the second time domain ratio to form an impedance interval of the line interval.

[0085] In this embodiment, the first time domain ratio may be used as the interval start point and the second time domain ratio may be used as the interval end point to form an impedance interval of the impedance to be tested in the line interval.

[0086] Thereafter, the impedance interval may be output to an oscilloscope, the impedance interval in the oscilloscope may be corrected, and the impedance interval may be displayed using a dotted line or the like, so that the impedance curve of the printed circuit board may be divided according to the corrected impedance interval.

[0087] In this embodiment, a target circuit to be tested is located in a printed circuit board; a circuit section having an impedance to be tested is located in the target circuit; a first pad and a second pad matching the circuit section are located in the printed circuit board; wherein the first pad is located in the first layer board structure of the printed circuit board; a communication link is determined with the first pad as the communication starting point, passing through the target circuit and the second pad as the communication end point; a test signal is transmitted in the communication link to collect transmission performance parameters for the communication link; and an impedance section of the circuit section is generated based on the communication link and the transmission performance parameters. In this embodiment, when detecting the impedance of a circuit across layers in a printed circuit board, the impedance section of the circuit section where the impedance to be tested is located is corrected based on the properties of the communication line itself and the performance parameters when transmitting signals, which can improve the accuracy of positioning the circuit section of the impedance to be tested in the impedance curve and avoid the impedance fault phenomenon when covering the cross-layer.

[0088] Embodiment 2

[0089] See also Figure 4, shows a schematic diagram of the structure of a device for detecting impedance intervals of a printed circuit board provided by Embodiment 2 of the present invention. Figure 4 As shown, the device comprises:

[0090] The target circuit positioning module 401 is used to locate the target circuit to be tested in the printed circuit board; the target circuit has a circuit section with an impedance to be tested;

[0091] A pad positioning module 402 is used to position a first pad and a second pad matching the circuit section in the printed circuit board; wherein the first pad is located in the first layer board structure of the printed circuit board;

[0092] A communication link determination module 403, configured to determine a communication link having the first pad as a communication start point, passing through the target line and having the second pad as a communication end point;

[0093] A transmission performance parameter acquisition module 404, configured to transmit a test signal in the communication link to acquire transmission performance parameters of the communication link;

[0094] The impedance interval generating module 405 is used to generate the impedance interval of the line interval according to the communication link and the transmission performance parameter.

[0095] In one embodiment of the present invention, the pad positioning module 402 includes:

[0096] An interval endpoint determination module, used to determine a test start point and a test end point in the line area;

[0097] A first target hole positioning module, used for positioning a through hole in the printed circuit board to which the target circuit is connected and which is connected to the test starting point, as a first target hole;

[0098] A first pad positioning module, used for positioning a first pad in a first layer board structure of the printed circuit board that is communicatively connected to the first target hole;

[0099] A second target hole positioning module, used for positioning two through holes connected to the target circuit and the test end point in the printed circuit board as second target holes;

[0100] The second pad positioning module is used to position a second pad in communication connection with the second target hole in any layer structure of the printed circuit board.

[0101] In one embodiment of the present invention, the communication link determination module 403 includes:

[0102] A first auxiliary circuit positioning module, used for positioning a first auxiliary circuit between the first pad and the first target hole in the printed circuit board;

[0103] A second auxiliary circuit positioning module, used for positioning a second auxiliary circuit between the second pad and the second target hole in the printed circuit board;

[0104] The communication link composition module is used to determine a communication link that takes the first pad as a communication starting point, passes through the first auxiliary line, the target line, the second auxiliary line, and has the second pad as a communication end point.

[0105] In one embodiment of the present invention, the communication link determination module 403 further includes:

[0106] A link total length calculation module, used for calculating, for each of the communication links, the sum of the length of the first auxiliary line and the length of the second auxiliary line as the link total length;

[0107] A valid determination module, used to determine that the communication link with the smallest total link length is valid;

[0108] The communication link filtering module is used to filter out the communication link whose total link length is not the minimum.

[0109] In one embodiment of the present invention, the transmission performance parameter collection module 404 includes:

[0110] The delay acquisition module is used to transmit a test signal in the communication link to respectively acquire a first delay for the first auxiliary line, a second delay for the target line, and a third delay for the second auxiliary line as transmission performance parameters.

[0111] In one embodiment of the present invention, the impedance interval generation module 405 includes:

[0112] A total time domain index calculation module, configured to calculate a total time domain index according to the first auxiliary line and the first delay, the target line and the second delay, the second auxiliary line and the third delay;

[0113] A first sub-time domain indicator calculation module, configured to calculate a first sub-time domain indicator for a test starting point of the line section according to the first auxiliary line and the first delay, the target line and the second delay;

[0114] A second sub-time domain indicator calculation module, configured to calculate a second sub-time domain indicator for a test endpoint of the line section according to the first auxiliary line and the first delay, the target line and the second delay;

[0115] A first time domain ratio calculation module, used for calculating the ratio between the first sub-time domain index and the total time domain index as the first time domain ratio of the test starting point of the line section;

[0116] A second time domain ratio calculation module, used for calculating the ratio between the second sub-time domain index and the total time domain index as the second time domain ratio of the test end point of the line section;

[0117] An impedance interval composition module is used to combine the first time domain ratio and the second time domain ratio to form an impedance interval of the line interval.

[0118] In one embodiment of the present invention, the total time domain index calculation module includes:

[0119] A total number counting module, used for counting the total number of through holes between the first pad and the second pad in the communication link;

[0120] a total time domain index determination module, configured to add the product of the length of the first auxiliary line and the first time delay, the product of the length of the target line and the second time delay, the product of the length of the second auxiliary line and the second time delay, and the product of the total number and a preset fourth time delay to obtain a total time domain index;

[0121] The first sub-time domain indicator calculation module includes:

[0122] A first segment quantity counting module, used for counting the first segment quantity of the through hole between the first pad and the test starting point of the line section in the communication link;

[0123] A first quantile determination module, used to determine a first quantile at which the test starting point of the route section is located in the target route;

[0124] a first sub-time domain indicator determination module, configured to add a product of a length of the first auxiliary line and the first time delay, a product of a length of the target line, the second time delay and the first quantile, and a product of the first segment number and a preset fourth time delay, to obtain a first sub-time domain indicator;

[0125] The second sub-time domain indicator calculation module includes:

[0126] A second segment quantity counting module, used for counting the second segment quantity of the through hole between the second pad and the test end point of the line section in the communication link;

[0127] A second quantile determination module, used to determine a second quantile at which the test end point of the route section is located in the target route;

[0128] The second sub-time domain indicator determination module is used to add the product between the length of the first auxiliary line and the first delay, the product between the length of the target line, the second delay and the second quantile, and the product between the number of second segments and a preset fourth delay to obtain a second sub-time domain indicator.

[0129] In one embodiment of the present invention, it also includes:

[0130] The impedance interval output module is used to output the impedance interval to an oscilloscope so as to divide the impedance curve of the printed circuit board according to the impedance interval.

[0131] The device for detecting impedance intervals on a printed circuit board provided in the embodiment of the present invention can execute the method for detecting impedance intervals on a printed circuit board provided in any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method for detecting impedance intervals on a printed circuit board.

[0132] Embodiment 3

[0133] See also Figure 5 , shows a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0134] like Figure 5 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0135] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0136] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a method for detecting an impedance interval for a printed circuit board.

[0137] In some embodiments, the method for detecting an impedance interval on a printed circuit board may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the method for detecting an impedance interval on a printed circuit board described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the method for detecting an impedance interval on a printed circuit board in any other appropriate manner (e.g., by means of firmware).

[0138] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0139] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0140] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0141] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0142] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0143] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0144] Embodiment 4

[0145] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the method for detecting impedance intervals on a printed circuit board provided in any embodiment of the present invention is implemented.

[0146] In the process of implementation, the computer program product can be written in one or more programming languages ​​or a combination thereof to perform the computer program code of the present invention, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0147] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0148] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for detecting an impedance range of a printed circuit board, characterized in that: include: Locating a target circuit to be tested in a printed circuit board; A line section having an impedance to be tested in the target line; Positioning a first pad and a second pad matching the circuit section in the printed circuit board; wherein the first pad is located on the first layer board structure of the printed circuit board; Determine a communication link having the first pad as a communication starting point, passing through the target line and having the second pad as a communication end point; Transmitting a test signal in the communication link to collect transmission performance parameters of the communication link; An impedance interval of the line interval is generated according to the communication link and the transmission performance parameter.

2. The method according to claim 1, characterized in that The method of positioning a first pad and a second pad matching the circuit section in the printed circuit board includes: Determine a test start point and a test end point in the line section; Locating a through hole in the printed circuit board to which the target circuit is connected and which is connected to the test starting point as a first target hole; Positioning a first pad in a first layer board structure of the printed circuit board that is communicatively connected to the first target hole; Positioning two through holes in the printed circuit board to which the target circuit is connected and which are connected to the test endpoint as second target holes; A second pad is positioned in any layer structure of the printed circuit board and is communicatively connected to the second target hole.

3. The method according to claim 2, characterized in that The determining of a communication link having the first pad as a communication starting point, passing through the target line and having the second pad as a communication end point includes: positioning a first auxiliary circuit between the first pad and the first target hole in the printed circuit board; positioning a second auxiliary circuit between the second pad and the second target hole in the printed circuit board; A communication link is determined, which has the first pad as a communication starting point, passes through the first auxiliary line, the target line, the second auxiliary line, and has the second pad as a communication end point.

4. The method according to claim 3, characterized in that The determining of a communication link having the first pad as a communication starting point, passing through the target line and having the second pad as a communication end point also includes: For each of the communication links, calculating the sum of the length of the first auxiliary line and the length of the second auxiliary line as the total link length; Determining that the communication link with the smallest total link length is valid; The communication links whose total link length is not the minimum are filtered out.

5. The method according to claim 3, characterized in that: The transmitting of the test signal in the communication link to collect transmission performance parameters of the communication link includes: A test signal is transmitted in the communication link to collect a first delay for the first auxiliary line, a second delay for the target line, and a third delay for the second auxiliary line as transmission performance parameters.

6. The method according to claim 5, characterized in that The step of generating the impedance interval of the line interval according to the communication link and the transmission performance parameter comprises: Calculate the total time domain index according to the first auxiliary line and the first delay, the target line and the second delay, the second auxiliary line and the third delay; Calculate a first sub-time domain indicator for a test starting point of the line section according to the first auxiliary line and the first delay, the target line and the second delay; Calculate a second sub-time domain indicator for a test endpoint of the line section according to the first auxiliary line and the first delay, the target line and the second delay; Calculating a ratio between the first sub-time domain index and the total time domain index as a first time domain ratio of a test starting point of the line section; Calculating a ratio between the second sub-time domain index and the total time domain index as a second time domain ratio of the test end point of the line section; The first time domain ratio and the second time domain ratio are combined to form an impedance interval of the line interval.

7. The method according to claim 6, characterized in that The calculating the total time domain index according to the first auxiliary line and the first delay, the target line and the second delay, the second auxiliary line and the third delay includes: Counting the total number of through holes between the first pad and the second pad in the communication link; Adding the product of the length of the first auxiliary line and the first time delay, the product of the length of the target line and the second time delay, the product of the length of the second auxiliary line and the second time delay, and the product of the total number and a preset fourth time delay to obtain a total time domain indicator; The calculating the first sub-time domain indicator at the test starting point of the line section according to the first auxiliary line and the first delay, the target line and the second delay includes: Counting the number of first segments of through holes between the first pad and the test starting point of the line section in the communication link; Determine a first quantile of a test starting point of the route section in the target route; Adding the product of the length of the first auxiliary line and the first time delay, the product of the length of the target line, the second time delay and the first quantile, and the product of the first segment number and a preset fourth time delay to obtain a first sub-time domain indicator; The calculating the second sub-time domain indicator for the test endpoint of the line section according to the first auxiliary line and the first delay, the target line and the second delay includes: Counting the number of second segments of the through hole between the second pad and the test end point of the line section in the communication link; Determine a second quantile of a test endpoint of the route section in the target route; The product of the length of the first auxiliary line and the first delay, the product of the length of the target line, the second delay and the second quantile, and the product of the second segment number and the preset fourth delay are added to obtain a second sub-time domain indicator.

8. The method according to any one of claims 1 to 7, characterized in that Also includes: The impedance interval is output to an oscilloscope, so as to divide the impedance curve of the printed circuit board according to the impedance interval.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the method for detecting impedance intervals on a printed circuit board according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for detecting an impedance interval on a printed circuit board according to any one of claims 1 to 8 is implemented.

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