GPU video memory and bandwidth adjusting method and system based on bus bandwidth monitoring

Abstract

The invention provides a GPU video memory and bandwidth adjusting method and system based on bus bandwidth monitoring, and the method comprises the steps: calculating the size of a video memory and the read-back time of display data needed by each internal module and external display equipment through monitoring the information of each internal module, bus and external display equipment of a GPU chip in real time; the priority and the access time of accessing the video memory are configured according to the bus bandwidth, so that the utilization rate of the bus bandwidth is improved, the bus bandwidth is effectively reduced, and the problems of image tearing, blurred screen and frame skipping caused by data loss, coverage and relatively large read-back delay due to bus competition and low bus utilization rate are avoided; the real-time stable display of the image is ensured, and the design method can effectively reduce the power consumption of the system.

Description

Technical Field

[0001] The present invention relates to the field of bus bandwidth monitoring, and more specifically, to a GPU video memory and bandwidth adjustment method and system based on bus bandwidth monitoring. Background Art

[0002] With the continuous improvement of display technology and the update and iteration of office equipment, various industries have higher and higher requirements for display, and the demand for multiple display interfaces and multiple resolutions at the same time is also increasing day by day. The increasingly competitive market also requires energy saving and consumption reduction, so the requirements for bus bandwidth, utilization and transmission rate are also getting higher and higher. Traditional GPU display controllers store pixels in cache according to fixed timing and allocate prefetch mode when registers are initialized, and read from cache when the display is valid. However, as the resolution increases, the amount of data will increase dramatically, and the requirements for data reading rate will become higher and higher. In addition, the replacement or shutdown of external display devices cannot be perceived in time, which will put forward new requirements for the dynamic configuration of bus bandwidth and transmission mode.

[0003] In the mode of multi-resolution and multi-interface working at the same time, when multiple modules access the bus at the same time, the competition between channels and the arbitration of priorities will cause data delay, loss or overwriting, and even tearing, screen distortion and frame skipping of displayed images. The existing methods mainly reduce the resolution of each display device or increase the bus bandwidth. These methods not only waste bus bandwidth and bring high production costs, but also greatly reduce user experience. Summary of the invention

[0004] When multiple resolutions and multiple interfaces are working simultaneously, when multiple modules of a GPU access video memory simultaneously, the bus cannot be effectively utilized because the way of accessing the video memory bus is fixed and the changes of external devices cannot be monitored in time, resulting in problems such as image tearing, screen distortion and frame skipping. The present invention provides a GPU video memory and bandwidth adjustment method and system based on bus bandwidth monitoring.

[0005] According to a first aspect of the present invention, a method for adjusting GPU memory and bandwidth based on bus bandwidth monitoring is provided, comprising:

[0006] Step 1, when the GPU chip is displaying, the registers of each module of the GPU chip are configured, the clock frequency and resolution of each module are configured, and the bandwidth detector is turned on. The modules of the GPU chip include each graphics processor and each display controller;

[0007] Step 2: The bandwidth detector obtains the data volume and rate of each module through the system management bus, and obtains the access information of the current bus;

[0008] Step 3, according to the acquired data volume and rate of each module and the access information of the current bus, the bandwidth, video memory and rate of each module are reallocated, and the allocation information is written into the function register of the bandwidth monitor;

[0009] Step 4, after writing the function register, the bandwidth monitor notifies the host in the form of an interrupt;

[0010] Step 5, the host obtains the allocation information in the function register, configures the CRU module, reallocates the access memory size, bus bandwidth and rate of each module, and completes system initialization;

[0011] Step 6: After initialization is completed, the bandwidth monitor is notified and the system starts working.

[0012] Based on the above technical solution, the present invention can also make the following improvements.

[0013] Optionally, in step 2, obtaining access information of the current bus includes:

[0014] Statistics of read delay time and data storage size of each port of the bus;

[0015] According to the read delay time and data storage size of each port of the bus, the dictionary is searched to determine the clock frequency, data bus bandwidth and address bus bandwidth of the bus, and the burst value and bus pre-read cycle value of the bus are determined.

[0016] Optionally, the dictionary stores bus information, which includes a bus number, an index item and corresponding preferred data, wherein each bus includes multiple index items, an index item includes multiple preferred data, and the index items include clock frequency, data bus width and address bus width.

[0017] Optionally, the step 3, reallocating the bandwidth, video memory and rate of each module according to the acquired data volume and rate of each module and the access information of the current bus, includes:

[0018] If it is detected that the display device is replaced, the bus bandwidth information of the display controller needs to be adjusted;

[0019] If the display device is not replaced, there is no need to adjust the bus bandwidth information.

[0020] Optionally, if it is detected that the display device is replaced, the bus bandwidth information of the display controller needs to be adjusted, including:

[0021] Get the current bus bandwidth and memory access information. If the bus access rate changes, you need to modify the bus rate and configure the bus rate related registers.

[0022] If the amount of data accessing the bus changes, you need to modify the video memory size and configure the video memory related registers;

[0023] If the delay time required to access the bus is changed, the bus bandwidth needs to be modified and the bus bandwidth related registers need to be configured.

[0024] According to a second aspect of the present invention, there is provided a GPU memory and bandwidth adjustment system based on bus bandwidth monitoring, comprising:

[0025] It includes a monitor register, a bus configuration register, a bus monitor, a video memory monitor, a video memory configuration register, an interrupt processing module and a bus management module;

[0026] A monitor register, used to enable the bus bandwidth function and control the switches of the bus monitor, bus configuration register, video memory monitor, video memory configuration register, interrupt processing module and bus management module;

[0027] The video memory monitor is used to monitor the replacement of the external device of the display controller, obtain the information of the current display device and the replacement display device through the system management bus, calculate the video memory size and clock frequency of the display device, write to the display configuration register, and notify the host to obtain the change information;

[0028] Video memory configuration register, used to store the display controller's clock frequency, display resolution, and external display device information;

[0029] The bus monitor is used to monitor the bandwidth, address, clock frequency, burst length, and information of the bus interface connection module of the bus interface, and write the information into the bus configuration register to notify the host to obtain the information and configure various bus interface parameters;

[0030] The bus configuration register is used to store the initialization information, pre-configuration information and current real-time configuration information of the bus;

[0031] The interrupt processing module is used to generate video memory configuration interrupts and bus configuration interrupts, which notify the host in the form of IO and registers, and handle various interrupts of external devices;

[0032] The bus management module is used to manage the configuration of the video memory bus and internal bus, as well as the update and maintenance of configuration information, and communicate with the host and external devices via SMBus, AMBA, and custom buses.

[0033] The present invention provides a GPU video memory and bandwidth adjustment method and system based on bus bandwidth monitoring. The method monitors the information of each internal module, bus and external display device of the GPU chip in real time, calculates the video memory size and display data readback time required by each internal module and external display device, and then configures the priority and access time of the video memory according to the bus bandwidth, thereby improving the bus bandwidth utilization rate, effectively reducing the bus bandwidth, avoiding data loss, overwriting and large readback delay caused by bus competition and low bus utilization, thereby avoiding image tearing, screen distortion and frame skipping problems, ensuring real-time and stable display of images, and the design method can effectively reduce system power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A flow chart of a GPU video memory and bandwidth adjustment method based on bus bandwidth monitoring provided by the present invention;

[0035] Figure 2 It is an overall flow chart of the GPU video memory and bandwidth adjustment method based on bus bandwidth monitoring;

[0036] Figure 3 A flowchart for obtaining bus access information;

[0037] Figure 4 A schematic diagram of the data structure of a dictionary for storing bus information;

[0038] Figure 5 A schematic diagram of bus read cycle and read delay;

[0039] Figure 6 A flowchart for modifying configuration information when replacing an external display device;

[0040] Figure 7 A block diagram of a GPU display memory and bandwidth adjustment system based on bus bandwidth monitoring provided by the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be arbitrarily combined with each other to form a feasible technical solution. This combination is not subject to the constraints of the sequence of steps and / or the structural composition mode, but must be based on the ability of ordinary technicians in this field to achieve. When the combination of technical solutions is contradictory or cannot be achieved, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0042] Existing bandwidth monitoring methods monitor bus bandwidth for data errors, read back data, or implement data pre-fetching through multi-level caches, and reduce bus load by reducing bus clock frequency. Existing methods cannot avoid display distortion and image tearing, nor can they improve bus exchange efficiency under existing bandwidth, and reasonably adjust bus priority and burst length.

[0043] Based on this, the present invention monitors in real time whether each internal module, bus and external display device of the GPU chip has been changed, calculates the video memory size and display data read-back time required by each internal module and external display device through a calculation module, and then configures the priority and access time of the video memory according to the bus bandwidth, thereby improving the bus bandwidth utilization rate, effectively reducing the bus bandwidth, avoiding data loss, overwriting and large read-back delay caused by bus competition and low bus utilization, thereby avoiding image tearing, screen distortion and frame skipping problems, ensuring real-time and stable display of the image, and the design method can effectively reduce system power consumption.

[0044] Figure 1 A flowchart of a GPU video memory and bandwidth adjustment method based on bus bandwidth monitoring provided by the present invention is shown in FIG. Figure 1 Shown and Figure 2 , methods include:

[0045] Step 1: When the GPU chip is displaying, the registers of each module of the GPU chip are configured, the clock frequency and resolution of each module are configured, and the bandwidth detector is turned on. The modules of the GPU chip include each graphics processor and each display controller.

[0046] Specifically, when the GPU chip is displaying, it is necessary to configure the registers of each internal graphics processing module and each display controller, configure the clock and resolution of different display controllers, and enable the function register of the bandwidth monitor.

[0047] Step 2: The bandwidth detector obtains the data volume and rate of each module through the system management bus, and obtains the access information of the current bus.

[0048] Specifically, the bandwidth monitor obtains the data throughput of each graphics processing module through the system management bus, as well as detailed information and resolution requirements of the external display device of the display controller, such as the size of the external display device, supported standard resolution and non-standard resolution.

[0049] The bandwidth detector obtains the data volume and rate of each module through the system management bus, and obtains the access information on the current bus. Figure 3 , obtain the access information on the current bus, including: counting the read delay time and data storage size of each port of the bus; according to the read delay time and data storage size of each port of the bus, look up the dictionary to determine the clock frequency, data bus bandwidth and address bus bandwidth of the bus, and determine the burst value of the bus and the bus pre-read cycle value.

[0050] The data structure of the dictionary storing bus information can be found in Figure 4 The dictionary stores bus information, which includes bus number, index item and corresponding preferred data. Each bus includes multiple index items, such as the clock frequency, data bus width and address bus width of the bus. An index item includes multiple preferred data, that is, multiple preferred data are configured for an index item, such as multiple preferred clock frequencies.

[0051] According to the data volume and read delay information of the bus, the clock frequency, data bus width and address bus width of the bus are determined, and the burst value and bus pre-read cycle value of the bus are determined. The process is as follows: Figure 5 As shown in the figure, the data delay of each module on the bus is minimized and the bus transmission efficiency is maximized.

[0052] Step 3, according to the acquired data volume and rate of each module and the access information of the current bus, the bandwidth, video memory and rate of each module are reallocated, and the allocation information is written into the function register of the bandwidth monitor.

[0053] For details, see Figure 6 , the step 3, reallocates the bandwidth, video memory and rate of each module according to the acquired data volume and rate of each module and the access information of the current bus, including: if it is detected that the display device is replaced, the bus bandwidth information of the display controller needs to be adjusted; if the display device is not replaced, there is no need to adjust the bus bandwidth information.

[0054] Among them, if it is detected that the display device is replaced, the bus bandwidth information of the display controller needs to be adjusted, including: obtaining the current bus bandwidth and memory access information; if the rate of accessing the bus changes, the bus rate needs to be modified and the bus rate related registers need to be configured; if the amount of data accessing the bus changes, the video memory size needs to be modified and the video memory related registers need to be configured; if the delay time required to access the bus changes, the bus bandwidth needs to be modified and the bus bandwidth related registers need to be configured.

[0055] It is understandable that the size and bandwidth of the bus and video memory are reallocated according to different change information of the display device, and the reallocation information is stored in the register, wherein the register stores the module that needs to be reallocated and what information the module reallocates, for example, whether to modify the bus rate, the video memory size, or the bus bandwidth, and the reallocation information is stored in the relevant register.

[0056] Step 4: After writing the function register, the bandwidth monitor notifies the host via an interrupt.

[0057] It is understandable that when the reallocated information is written to the register, the host is notified in the form of an interrupt, informing the host that the bandwidth monitor detects that the rate, bandwidth or resolution information of the corresponding module needs to be adjusted.

[0058] Step 5: The host obtains the allocation information in the function register, configures the CRU module, reallocates the access memory size, bus bandwidth and rate of each module, and completes system initialization.

[0059] It is understandable that after receiving the interrupt, the host accesses the register of the bandwidth monitor, obtains the modification information (reallocation information), and then configures the CRU (clock reset unit) to change the bus clock rate of the corresponding module, sets the bus memory access size, bus burst size and other registers, configures the bus data width, and completes the initialization of the configuration module.

[0060] Step 6: After initialization is completed, the bandwidth monitor is notified and the system starts working.

[0061] It is understandable that after the configuration module is initialized, the register is written to notify the bus monitor, the configuration is completed, and the system starts working.

[0062] See also Figure 7 The present invention also provides a GPU video memory and bandwidth adjustment system based on bus bandwidth monitoring, which can realize GPU video memory and bandwidth adjustment. The system mainly includes a monitor register, a bus configuration register, a bus monitor, a video memory monitor, a video memory configuration register, an interrupt processing module and a bus management module.

[0063] The monitor register is used to enable the bus bandwidth function and control the switches of the bus monitor, bus configuration register, video memory monitor, video memory configuration register, interrupt processing module and bus management module;

[0064] The video memory monitor is used to monitor the replacement of the external device of the display controller, obtain the information of the current display device and the replacement display device through the system management bus, calculate the video memory size and clock frequency of the display device, write to the display configuration register, and notify the host to obtain the change information;

[0065] Video memory configuration register, used to store the display controller's clock frequency, display resolution, and external display device information;

[0066] The bus monitor is used to monitor the bandwidth, address, clock frequency, burst length, and information of the bus interface connection module of the bus interface, and write the information into the bus configuration register to notify the host to obtain the information and configure various bus interface parameters;

[0067] The bus configuration register is used to store the initialization information, pre-configuration information and current real-time configuration information of the bus;

[0068] The interrupt processing module is used to generate video memory configuration interrupts and bus configuration interrupts, which notify the host in the form of IO and registers, and handle various interrupts of external devices;

[0069] The bus management module is used to manage the configuration of the video memory bus and internal bus, as well as the update and maintenance of configuration information, and communicate with the host and external devices via SMBus, AMBA, and custom buses.

[0070] It is understandable that the GPU video memory and bandwidth adjustment system provided by the present invention can realize the allocation of video memory and bandwidth of each module in the GPU chip and the display controller. When the system is initialized, the bus monitor, bus configuration register, video memory monitor, video memory configuration register and interrupt processing module are enabled by configuring the monitor register. The video memory monitor obtains the display resolution and current display resolution of each display controller external device through the video memory configuration register and the system management bus. And the interrupt processing module generates an interrupt to notify the host to obtain display information and allocate the video memory size of each display device. The bus monitor obtains the protocol type, transmission bandwidth, clock frequency, burst length and actual transmission information of each bus through the bus configuration register and the system management bus. And the interrupt processing module generates an interrupt to notify the host to obtain bus information. The host calculates the bandwidth, address, clock frequency, burst length and priority of the bus according to the module function connected to each bus port, and then configures the bus configuration register through the system management module to complete the configuration and monitor the bus changes in real time.

[0071] It can be understood that the GPU video memory and bandwidth adjustment system based on bus bandwidth monitoring provided by the present invention corresponds to the GPU video memory and bandwidth adjustment method based on bus bandwidth monitoring provided by the aforementioned embodiments. The relevant technical features of the GPU video memory and bandwidth adjustment system based on bus bandwidth monitoring can refer to the relevant technical features of the GPU video memory and bandwidth adjustment method based on bus bandwidth monitoring, which will not be repeated here.

[0072] The GPU memory and bandwidth adjustment method and system based on bus bandwidth monitoring provided by the embodiment of the present invention have the following advantages:

[0073] (1) The system does not need to increase storage and bus bandwidth. By adding a logic control module, real-time allocation and flexible scheduling can be achieved from the hardware. By real-time monitoring of each module and bus, and monitoring whether the external display device has changed, the required video memory size and display data readback time of the module are calculated, and the priority and access time of the video memory are configured according to the bus bandwidth.

[0074] (2) Implement bus bandwidth monitoring configuration and video memory monitoring configuration with minimal resources, improve bus bandwidth utilization, effectively reduce bus bandwidth, avoid data loss, overwriting, and large read-back delays caused by bus competition and low bus utilization, thereby avoiding image tearing, screen distortion, and frame skipping problems, which is beneficial to the real-time and accuracy of image display, reduces system overhead, saves production costs, and improves user experience.

[0075] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0076] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0077] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0078] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0079] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0080] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0081] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A GPU memory and bandwidth adjustment method based on bus bandwidth monitoring, characterized in that: include: Step 1, when the GPU chip is displaying, the registers of each module of the GPU chip are configured, the clock frequency and resolution of each module are configured, and the bandwidth detector is turned on. The modules of the GPU chip include each graphics processor and each display controller; Step 2, the bandwidth detector obtains the data volume and rate of each module through the system management bus, and obtains the access information of the current bus; Step 3, according to the acquired data volume and rate of each module and the access information of the current bus, the bandwidth, video memory and rate of each module are reallocated, and the allocation information is written into the function register of the bandwidth monitor; Step 4, after writing the function register, the bandwidth monitor notifies the host in the form of an interrupt; Step 5, the host obtains the allocation information in the function register, configures the CRU module, reallocates the access memory size, bus bandwidth and rate of each module, and completes system initialization; Step 6: After initialization is completed, the bandwidth monitor is notified and the system starts working.

2. The GPU video memory and bandwidth adjustment method according to claim 1, characterized in that: In the step 2, obtaining the access information of the current bus includes: Statistics of read delay time and data storage size of each port of the bus; According to the read delay time and data storage size of each port of the bus, the dictionary is searched to determine the clock frequency, data bus bandwidth and address bus bandwidth of the bus, and the burst value and bus pre-read cycle value of the bus are determined.

3. The GPU memory and bandwidth adjustment method according to claim 2, characterized in that: The dictionary stores bus information, which includes bus number, index items and corresponding preferred data, wherein each bus includes multiple index items, one index item includes multiple preferred data, and the index items include clock frequency, data bus width and address bus width.

4. The GPU video memory and bandwidth adjustment method according to claim 3, characterized in that: The step 3, based on the acquired data volume and rate of each module and the access information of the current bus, reallocates the bandwidth, video memory and rate of each module, including: If it is detected that the display device is replaced, the bus bandwidth information of the display controller needs to be adjusted; If the display device is not replaced, there is no need to adjust the bus bandwidth information.

5. The GPU video memory and bandwidth adjustment method according to claim 4, characterized in that: If it is detected that the display device is replaced, the bus bandwidth information of the display controller needs to be adjusted, including: Get the current bus bandwidth and memory access information. If the bus access rate changes, you need to modify the bus rate and configure the bus rate related registers. If the amount of data accessing the bus changes, you need to modify the video memory size and configure the video memory related registers; If the delay time required to access the bus is changed, the bus bandwidth needs to be modified and the bus bandwidth related registers need to be configured.

6. A GPU memory and bandwidth adjustment system based on bus bandwidth monitoring, used to implement the GPU memory and bandwidth adjustment method of claim 1, characterized in that: It includes a monitor register, a bus configuration register, a bus monitor, a video memory monitor, a video memory configuration register, an interrupt processing module and a bus management module; A monitor register, used to enable the bus bandwidth function and control the switches of the bus monitor, bus configuration register, video memory monitor, video memory configuration register, interrupt processing module and bus management module; The video memory monitor is used to monitor the replacement of the external device of the display controller, obtain the information of the current display device and the replacement display device through the system management bus, calculate the video memory size and clock frequency of the display device, write to the display configuration register, and notify the host to obtain the change information; Video memory configuration register, used to store the display controller's clock frequency, display resolution, and external display device information; The bus monitor is used to monitor the bandwidth, address, clock frequency, burst length, and information of the bus interface connection module of the bus interface, and write the information into the bus configuration register to notify the host to obtain the information and configure various bus interface parameters; The bus configuration register is used to store the initialization information, pre-configuration information and current real-time configuration information of the bus; The interrupt processing module is used to generate video memory configuration interrupts and bus configuration interrupts, which notify the host in the form of IO and registers, and handle various interrupts of external devices; The bus management module is used to manage the configuration of the video memory bus and internal bus, as well as the update and maintenance of configuration information, and communicate with the host and external devices via SMBus, AMBA, and custom buses.

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