Package-compatible heterogeneous multi-core chip starting expansion method and device and chip

Abstract

The invention discloses a package-compatible heterogeneous multi-core chip start expansion method and device and a chip, the method comprises the following steps: S1, configuring a start configuration bit, setting a configuration bit of an expansion start mode in the start configuration bit, the expansion start mode being a mode of using a non-main start XPU core as a host to complete start; s2, after the chip exits the power-on reset or the thermal reset, reading the value of the start configuration bit, and if the mode is an extended start mode, sending an enable signal; s3, when an enabling signal of the expansion starting mode is received, controlling to start a target peripheral clock, and mapping a target XPU kernel access address space to a target storage space; and S4, programming a starting program required for starting into the target storage space to finish starting configuration of the target XPU kernel. According to the method, the non-main starting XPU kernel can be expanded to be started as the host, and the method has the advantages of being high in application flexibility and expandability, low in implementation cost and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of heterogeneous multi-core microprocessor chips, and in particular to a packaging-compatible heterogeneous multi-core chip startup expansion method, device and chip. Background Art

[0002] Heterogeneous multi-core microprocessor SoC system has ultra-high integration and complexity, and is the current mainstream microprocessor chip. The self-starting solution of heterogeneous multi-core chip is the interactive interface between embedded processor and supporting packaging design solution and board design solution, which is the key to the robust application of embedded processor. Therefore, the self-starting link of chip is the key link to realize high-performance chip.

[0003] For the self-startup of heterogeneous multi-core microprocessor chips, the prior art usually uses a certain type of processing core XPU (general-purpose programmable processing core represented by CPU, DSP, GPU) as the main startup core to complete the initialization configuration of the system startup, that is, specifying a certain XPU core as the only main core to complete the initialization configuration of the startup, and thus only supports one type of XPU core as the main startup core to complete the initialization configuration of the system startup, and all other programmable cores except the main core can only be used as slave cores. However, in actual applications, the user's startup requirements may be diverse, for example, it is necessary to use other XPU cores other than the main startup core to complete the startup, and the above solution that can only support one type of XPU core as the main startup core to complete the system startup cannot meet the user's diverse startup requirements.

[0004] For the released chips, the main boot core configuration of the chip is fixed. The released heterogeneous multi-core microprocessor chip has only one main boot core. In order to meet the needs of users to use different main boot cores to complete system startup, the current solution is to redesign the boot solution. However, since the boot program (ROM Boot Loader, RBL) is usually solidified in the non-erasable non-volatile storage (BOOTROM) in the chip to ensure security and the integration of the heterogeneous multi-core processor, the RBL is difficult to modify. It is necessary to modify the corresponding circuit in the chip, and then redesign the supporting package and board to achieve the purpose of modifying the boot solution, which will greatly increase the implementation cost and extend the product cycle.

[0005] Chinese patent application CN116594953A discloses a multi-core heterogeneous chip, startup method and system based on PCIE interconnection. This solution uses a startup software package to enable each sub-chip in the multi-core heterogeneous chip to independently load the corresponding startup image and run it, so as to realize joint computing of multiple sub-chips. In this type of solution, it can actually only support one type of core as the main startup core to complete the system startup, and still cannot meet the demand of using other non-main startup cores to complete the startup, and additional resources are needed to cooperate to complete the startup. Summary of the invention

[0006] The technical problem to be solved by the present invention is: in view of the technical problems existing in the prior art, the present invention provides a heterogeneous multi-core chip startup expansion method, device and chip with simple operation, flexible applicability, strong scalability, low implementation cost and packaging compatibility. There is no need to change the chip packaging and board design, and the existing resources can be fully utilized to expand the non-main startup XPU core as the host to complete the chip startup initialization configuration.

[0007] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0008] A package-compatible heterogeneous multi-core chip startup extension method is used to extend the use of a non-main startup XPU core as a host to complete chip startup, the steps comprising:

[0009] Step S1. configuring the startup mode for the startup configuration bit, wherein the startup configuration bit is provided with a configuration bit for the extended startup mode, wherein the extended startup mode is a startup mode in which the target XPU core is used as a host to complete chip startup, and the target XPU core is a non-main startup XPU core;

[0010] Step S2. After the chip exits power-on reset or hot reset, the value of the startup configuration bit is read, and the startup mode is determined according to the value of the startup configuration bit. If it is determined to be an extended startup mode, an enable signal of the extended startup mode is sent;

[0011] Step S3. When the enable signal of the extended startup mode is received, the target peripheral clock is turned on and the address space accessible after the target XPU core is powered on is mapped to the storage space connected to the target peripheral;

[0012] Step S4. Burn the startup program required for starting the target XPU core into the storage space connected to the target peripheral device, so that after the target XPU core is powered on, it executes the startup program by accessing the storage space connected to the target peripheral device, completing the startup initialization configuration of the target XPU core as the host.

[0013] Further, in step S1, the reserved bits in the startup configuration bits are used as extended configuration bits to configure the extended startup mode in which the non-main startup XPU core is started as the host, and the bits in the startup configuration bits other than the reserved bits are used as non-extended mode configuration bits to configure the non-extended startup mode in which the main startup XPU core is used as the host to complete the chip startup.

[0014] Further, in step S2, by reading the value of the startup configuration bit in the system-level control register after the chip exits power-on reset or hot reset, if it is determined according to the value of the startup configuration bit that the target XPU core is used as an extended startup mode of the host, an enable signal of the extended startup mode is sent to the on-chip interconnect network and the clock power consumption management module, otherwise, an invalid signal of the extended startup mode is sent to the on-chip interconnect network and the clock power consumption management module.

[0015] Further, in step S3, when the clock power consumption management module receives an enable signal of the extended startup mode, it controls the turning on of the target peripheral clock at the end of the power-on reset and the hot reset; when the clock power consumption management module receives an invalid signal of the extended startup mode, it turns off the peripheral clock at the end of the power-on reset and the hot reset.

[0016] Further, in step S3, when the on-chip interconnect network receives an enable signal of the extended startup mode, the address space accessible to the target XPU core after power-on is mapped to the FLASH space connected to the target peripheral device; when the on-chip interconnect network receives an invalid signal of the extended startup mode, the target XPU core is controlled to complete the startup as a slave.

[0017] Further, in step S3, when an invalid signal of the extended startup mode is received, the address space accessible to the XPU after power-on is divided into two segments, the first segment address is mapped to the end of the on-chip storage space for storing the page table configuration segment of the XPU, and the second segment address is mapped to the designated storage space for storing the jump program, so as to control the target XPU kernel to complete the startup according to the slave.

[0018] Further, in step S4, the startup program required for starting the target XPU core includes a page table configuration program and a jump program. When the target XPU core is powered on, the target XPU core accesses the storage space connected to the target peripheral device to execute the configuration page table and then jumps to execute the main program.

[0019] A package-compatible heterogeneous multi-core chip startup extension device is used to extend the non-main startup XPU core as a host to complete chip startup, including:

[0020] A configuration module, used to configure the startup mode for the startup configuration bit, wherein the startup configuration bit is provided with a configuration bit of an extended startup mode, wherein the extended startup mode is a startup mode in which the target XPU core is used as a host to complete chip startup, and the target XPU core is a non-main startup XPU core;

[0021] A startup mode judgment module is used to read the value of the startup configuration bit after the chip exits power-on reset or hot reset, and judge the startup mode according to the value of the startup configuration bit. If it is judged to be an extended startup mode, an enable signal of the extended startup mode is sent;

[0022] An extended startup mode configuration module, for controlling the start of a destination peripheral clock when receiving an enable signal of the extended startup mode, and mapping an address space accessible to the target XPU core after power-on to a storage space connected to the destination peripheral;

[0023] The program burning module is used to burn the startup program required for starting the target XPU core into the storage space connected to the target peripheral, so that after the target XPU core is powered on, the startup program is executed by accessing the storage space connected to the target peripheral, completing the startup initialization configuration of the target XPU core as the host.

[0024] A heterogeneous multi-core chip includes a processor and a memory, wherein the memory is used to store a computer program, and the processor is used to execute the computer program to perform the above method.

[0025] A computer-readable storage medium storing a computer program, wherein the computer program implements the above method when executed by a processor.

[0026] Compared with the prior art, the present invention has the advantages that: the present invention aims at the startup of a heterogeneous multi-core microprocessor chip that has been released and has only one main startup core, by extending the configuration bit of the extended startup mode in the startup configuration bit, the extended startup mode corresponds to the startup mode of using the non-main startup XPU core as the host to complete the chip startup, after the chip exits the power-on reset or hot reset, the startup mode is judged by reading the value of the startup configuration bit, if it is the extended startup mode, the target peripheral clock is controlled to be turned on and the address space accessible to the target XPU core after power-on is mapped to the storage space connected to the target peripheral, and then the startup program required for the startup of the target XPU core is burned into the storage space connected to the target peripheral and then the startup program is executed, the original non-main startup XPU core can be expanded to the host to complete the initialization configuration of the system startup by using the existing resources on the chip, and there is no need to change the packaging and board design of the original chip, so that the startup extension of the heterogeneous multi-core chip with packaging compatibility can be realized, the production design cost and production design cycle of the chip are reduced, and the scalability, reliability and stability of the chip are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the implementation process of XPU booting as a slave core in the traditional booting solution.

[0028] Figure 2 It is a schematic diagram of the implementation flow of the packaging-compatible heterogeneous multi-core chip startup expansion method of this embodiment. DETAILED DESCRIPTION

[0029] The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0030] As shown in the disclosure of the present invention, unless the context clearly indicates an exception, the words "a", "an", "a kind of" and / or "the" do not specifically refer to the singular, but may also include the plural. The words "first", "second" and similar words used in the disclosure of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0031] For ease of understanding, the relevant technical background of the present invention is first introduced by way of example.

[0032] In order to ensure the reliability of chip self-startup, the heterogeneous multi-core microprocessor chip uses hardware-fixed code to store the RBL in a non-erasable storage body, which is mounted on the on-chip interconnect network bus. Only a certain type of XPU core is configured as the only master core to read the RBL program in the storage body, and then load it into the core through the on-chip interconnect network bus to execute the RBL program. Other XPU cores act as slave cores, which execute the corresponding XPU user program by continuously querying whether there is a value in the entry address register.

[0033] Heterogeneous multi-core microprocessor chips may have multiple main boot cores or only one main boot core. For heterogeneous multi-core microprocessor chips that have been released and have only one main boot core, the main boot core configuration of the chip is fixed. Only the only main boot XPU core can be used as the main core for booting, and the original non-main boot XPU cores can only be used as slave cores for booting. Figure 1 As shown, the non-main boot XPU core loops and queries the entry address register in the ROM space of BOOTROM by default to see if there is a value, jumps to the corresponding address for execution if there is a value, and keeps waiting if it is 0. The main boot XPU core configures the entry address register of the non-main boot XPU core, so that the non-main boot XPU access switches from ROM space to RAM space, thereby jumping to the tail space stored in the chip to execute the page table configuration program, and then jumping to the main program for execution.

[0034] The boot modes of released heterogeneous multi-core microprocessor chips include NoBoot boot, Slave Boot boot and Host Boot boot. Among them, NoBoot boot is to burn the user program into a readable and writable storage space, and the main core can be executed from the specified address; Slave Boot is to place the user program in the peripheral storage, and the RBL program reads the user program from the peripheral memory, loads the user program into the internal readable and writable memory space, and then jumps to the user program to start execution; Host Boot is to first load the user program into the internal storage space of the chip through an external host (PCIE, SRIO, etc.), and then the external host writes the kernel's entry address into the corresponding entry address register, and issues a boot completion flag, indicating that the external host has completed the loading of the user program. At this time, RBL detects that the external host has completed the move and jumps to the user program.

[0035] Currently released heterogeneous multi-core microprocessor chips are usually started in Host Boot and Slave Boot mode. The specific process is usually as follows:

[0036] 1. First, store the configuration segment, user program segment and entry address segment into Boot Image. Boot Image has two formats according to different boot modes: Raw format and BootTable format. Raw format is pure binary format, which is directly burned into the directly addressable readable and writable storage space. It is mainly used for NoBoot boot and Host Boot of some external hosts that can know the internal address of the chip; BootTable format is used for Slave Boot and Host Boot of some external hosts that do not know the internal address space of the chip.

[0037] 2. After the chip is reset, the main core executes the RBL program, reads the startup configuration bits, determines the startup mode, and sets the initialization configuration of the corresponding peripherals according to different user requirements;

[0038] 3. According to different startup modes, the user program is directly read from the directly addressable storage space or moved from the FLASH connected to the peripheral to the destination address (internal readable and writable memory space), or the high-speed peripheral acts as the host to move the user program to the destination address, and the entry address register of the XPU core is written with the corresponding value;

[0039] 4. Other non-master boot XPU cores act as slave cores. When each core detects that there is a value in the entry address register, it jumps to its own user program for execution.

[0040] The startup method of the above heterogeneous multi-core microprocessor chip only supports the only XPU core as the main startup core to complete the initialization configuration of the system startup. Except for the main core, other cores can only be started as slave cores. It cannot support multiple different main startup cores to complete autonomous startup. Therefore, it cannot meet the user's need to start the original non-main startup XPU core as the main core, and cannot meet the usage habits and diversified needs of different users. For the released chips, in order to meet the user's need to use different main startup cores to complete the system startup, the only way is to redesign the startup plan, modify the corresponding circuit, and redesign the supporting packaging and board, which will greatly increase the implementation cost and extend the product cycle.

[0041] Encapsulation Compatibility means allowing new or modified components to be integrated with existing systems without changing the existing system interfaces, keeping the external interfaces unchanged.

[0042] The present invention aims at starting a heterogeneous multi-core microprocessor chip that has been published and has only one main startup core. By extending and setting a configuration bit of an extended startup mode in a startup configuration bit, the extended startup mode corresponds to a startup mode in which a non-main startup XPU core is used as a host to complete chip startup. After the chip exits power-on reset or hot reset, the startup mode is judged by reading the value of the startup configuration bit. If it is the extended startup mode, the clock of the target peripheral is controlled to be turned on and the address space accessible to the target XPU core after power-on is mapped to the storage space connected to the target peripheral. Then, a startup program required for starting the target XPU core is burned into the storage space connected to the target peripheral and then the startup program is executed. The existing resources on the chip can be used to expand the original non-main startup XPU core into the host to complete the initialization configuration of system startup, and there is no need to change the packaging and board design of the original chip. The startup extension of the heterogeneous multi-core chip with packaging compatibility can be realized, the production design cost and production design cycle of the chip are reduced, and the scalability, reliability and stability of the chip are improved.

[0043] The present invention can achieve package-compatible heterogeneous multi-core chip startup expansion, which can not only meet the startup requirements of users with different XPU cores, but also facilitate users to flexibly select different XPU cores for self-booting according to their own needs and usage habits, and can also achieve package compatibility, avoiding circuit modification and package and board redesign due to redesign of startup solutions, greatly reducing the production design cost and production design cycle of chips, and simplifying the chip production and maintenance process, thereby improving the scalability and applicability of heterogeneous multi-core chips during self-startup expansion.

[0044] The present invention will be further described below in conjunction with specific embodiments.

[0045] like Figure 2As shown, the package-compatible heterogeneous multi-core chip startup extension method of this embodiment is used to extend the non-main startup XPU core as the host to complete the chip startup, and the steps include:

[0046] Step S1. configure the startup mode for the startup configuration bit, wherein the startup configuration bit is provided with a configuration bit for the extended startup mode, the extended startup mode is a startup mode in which the target XPU core is used as a host to complete chip startup, and the target XPU core is a non-main startup XPU core.

[0047] In this embodiment, the configuration bit of the extended startup mode is extended in the startup configuration bit to configure the extended startup mode in which the non-main startup XPU core is used as the host to complete the chip startup. Optionally, the reserved bit in the startup configuration bit can be used as an extended configuration bit, that is, by configuring the reserved bit of the startup configuration bit, the startup mode can be configured as a startup mode that requires the non-main startup XPU core to be started as the host. In addition, the bits other than the reserved bits in the startup configuration bit can be used as non-extended mode configuration bits to configure the non-extended startup mode in which the main startup XPU core is used as the host to complete the chip startup, that is, the normal startup mode in which the original main startup XPU core is started as the host.

[0048] It is understandable that other methods may be used to configure the startup configuration bits according to actual needs. For example, different values ​​of the same data bit may be used to correspond to the normal startup mode and the extended startup mode respectively.

[0049] This embodiment modifies the startup configuration bit and adds the original non-main startup XPU core as an extended startup mode for host startup, so that the user can flexibly select the required startup mode through the configuration of the startup configuration bit without adding new on-chip resources.

[0050] Step S2. After the chip exits power-on reset or hot reset, read the value of the startup configuration bit, determine the startup mode according to the value of the startup configuration bit, and if it is determined to be the extended startup mode, send an enable signal for the extended startup mode;

[0051] In this embodiment, by reading the value of the startup configuration bit in the system-level control register after the chip exits power-on reset or hot reset, if it is determined according to the value of the startup configuration bit that the target XPU core is used as the extended startup mode of the host, an enable signal of the extended startup mode is sent to the on-chip interconnect network and the clock power consumption management module, otherwise, an invalid signal of the extended startup mode is sent to the on-chip interconnect network and the clock power consumption management module.

[0052] For example, if the reserved bit of the startup configuration bit is added as the configuration bit of the extended startup mode, then after the power-on reset or hot reset, the value of the startup configuration bit is locked by the system-level control register, and then the value of the startup configuration bit is judged. If it is judged to be a newly added reserved bit configuration, the newly added XPU core is output as a host-started extended startup mode enable signal (valid signal) to the on-chip interconnect network and clock power consumption management module. If it is other values, the newly added XPU core is output as a host-started extended startup mode invalid signal to the on-chip interconnect network and clock power consumption management module.

[0053] Step S3. When an enable signal of the extended startup mode is received, the target peripheral clock is controlled to be turned on, and the address space accessible after the target XPU core is powered on is mapped to the storage space connected to the target peripheral.

[0054] In this embodiment, when the clock power consumption management module receives the enable signal (valid signal) of the extended startup mode, it controls the opening of the target peripheral clock at the end of the power-on reset and the hot reset; when the clock power consumption management module receives the invalid signal of the extended startup mode, it controls the closing of the peripheral clock at the end of the power-on reset and the hot reset. That is, the clock power consumption management module controls the opening or closing of the target peripheral clock at the end of the power-on reset and the hot reset according to whether the enable signal of the extended startup mode is valid. When the enable signal is a valid signal, if it is judged that the power-on reset and the hot reset are over, the target peripheral clock is controlled to be turned on to prepare for the startup based on the newly added XPU core as the host. If the enable signal received is an invalid signal, when it is judged that the power-on reset and the hot reset are over, the peripheral clock is controlled to be turned off to prepare for the startup with the original main startup XPU core as the host.

[0055] In this embodiment, the on-chip interconnect network monitors the enable signal of the extended startup mode in real time. When the on-chip interconnect network receives the enable signal of the extended startup mode, that is, when the enable signal is valid, it controls the address space accessible to the target XPU core after power-on to be mapped to the FLASH space connected to the destination peripheral, which can specifically be a space starting with the FLASH base address. When the on-chip interconnect network receives an invalid signal of the extended startup mode, it controls the target XPU core to complete the startup as a slave.

[0056] Optionally, when the on-chip interconnection network receives an invalid signal of the extended startup mode, the address space accessible to the XPU after power-on is divided into two segments, the first segment address is mapped to the end of the on-chip storage space for storing the page table configuration segment of the XPU, and the second segment address is mapped to the designated storage space for storing the jump program, so as to control the target XPU kernel to complete the startup according to the slave.

[0057] Specifically, the on-chip interconnect network controls the mapping of access addresses by monitoring the enable signal of the extended startup mode. If an enable signal of the newly added XPU core as the host startup is received, the address space accessible after the XPU is powered on is mapped to the FLASH space connected to the target peripheral. If an invalid signal of the XPU host startup is received, the address space accessible after the XPU is powered on is divided into two segments. The on-chip interconnect network maps the first segment address to the end of the on-chip storage space to store the configuration program segment of the XPU, and maps the second segment space address to the BOOTROM space to store the jump program, so that the logic of the XPU completing the startup as a slave is not affected.

[0058] It is understandable that other methods may be used to control the target XPU core to start up as a slave according to actual needs.

[0059] Step S4. Burn the startup program required for starting the target XPU core into the storage space connected to the target peripheral device, so that after the target XPU core is powered on, it executes the startup program by accessing the storage space connected to the target peripheral device, completing the startup initialization configuration of the target XPU core as the host.

[0060] In this embodiment, the startup program required for starting the target XPU kernel includes a page table configuration program and a jump program, etc. If the current judgment is an extended startup mode, the page table configuration program and the main program required for starting the target XPU kernel are burned into the FLASH storage space of the target peripheral. When the target XPU kernel is powered on, it can directly access the FLASH storage space of the peripheral. After the target XPU kernel is powered on, it accesses the storage space connected to the target peripheral to execute the configuration page table and then jumps to execute the main program, thereby realizing a package-compatible heterogeneous multi-core chip startup expansion solution that utilizes existing on-chip resources to expand the original non-main startup XPU kernel into a host to complete the system startup initialization configuration work.

[0061] In a specific application embodiment, the software module corresponding to the above method of the present invention can be used as a startup patch compatible with the packaging of a heterogeneous multi-core embedded processor product. The patch can be used to implement startup extension of a package-compatible heterogeneous multi-core chip, and the original non-main startup core XPU can be flexibly used as the host for startup initialization configuration to meet the usage habits and diversified needs of different users. At the same time, it can avoid re-modifying the circuit, redesigning the packaging and board, etc., greatly reducing the chip design implementation cost and improving the flexible applicability of the chip.

[0062] This embodiment also provides a package-compatible heterogeneous multi-core chip startup extension device, which is used to extend the non-main startup XPU core as a host to complete chip startup, including:

[0063] A configuration module, configured to configure a startup mode for a startup configuration bit, wherein the startup mode includes an extended startup mode in which a target XPU core is used as a host to complete chip startup, and the target XPU core is a non-main startup XPU core;

[0064] A startup mode judgment module is used to read the value of the startup configuration bit after the chip exits power-on reset or hot reset, and judge the startup mode according to the value of the startup configuration bit. If it is judged to be an extended startup mode, an enable signal of the extended startup mode is sent;

[0065] An extended startup mode configuration module, for controlling the start of a destination peripheral clock when receiving an enable signal of the extended startup mode, and mapping an address space accessible to the target XPU core after power-on to a storage space connected to the destination peripheral;

[0066] The program burning module is used to burn the startup program required for starting the target XPU core into the storage space connected to the target peripheral, so that after the target XPU core is powered on, the startup program is executed by accessing the storage space connected to the target peripheral, completing the startup initialization configuration of the target XPU core as the host.

[0067] The package-compatible heterogeneous multi-core chip startup expansion device of this embodiment corresponds one-to-one to the package-compatible heterogeneous multi-core chip startup expansion method described above, and will not be described one by one here.

[0068] This embodiment further provides a heterogeneous multi-core chip, including a processor and a memory, the memory is used to store a computer program, and the processor is used to execute the computer program to perform the above method.

[0069] It is understandable that the above method of this embodiment can be executed by a single device, such as a computer or server, etc., and can also be applied to a distributed scenario and completed by multiple devices in cooperation with each other. In the case of a distributed scenario, one of the multiple devices can only execute one or more steps in the above method of this embodiment, and multiple devices interact to complete the above method. The processor can be implemented in the form of a general-purpose CPU, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, etc., for executing related programs to implement the above method of this embodiment. The memory can be implemented in the form of a read-only memory ROM, a random access memory RAM, a static storage device, and a dynamic storage device. The memory can store an operating system and other applications. When the above method of this embodiment is implemented by software or firmware, the relevant program code is stored in the memory and called and executed by the processor.

[0070] This embodiment further provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the above method is implemented.

[0071] Those skilled in the art will appreciate that the above-mentioned embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0072] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A package-compatible heterogeneous multi-core chip startup extension method for extending the non-main startup XPU core as a host to complete chip startup, characterized in that the steps include: Step S1. configuring the startup mode for the startup configuration bit, wherein the startup configuration bit is provided with a configuration bit for the extended startup mode, wherein the extended startup mode is a startup mode in which the target XPU core is used as a host to complete chip startup, and the target XPU core is a non-main startup XPU core; Step S2. After the chip exits power-on reset or hot reset, the value of the startup configuration bit is read, and the startup mode is determined according to the value of the startup configuration bit. If it is determined to be an extended startup mode, an enable signal of the extended startup mode is sent; Step S3. When the enable signal of the extended startup mode is received, the target peripheral clock is turned on and the address space accessible after the target XPU core is powered on is mapped to the storage space connected to the target peripheral; Step S4. Burn the startup program required for starting the target XPU core into the storage space connected to the target peripheral device, so that after the target XPU core is powered on, it executes the startup program by accessing the storage space connected to the target peripheral device, completing the startup initialization configuration of the target XPU core as the host.

2. The package-compatible heterogeneous multi-core chip startup expansion method according to claim 1, characterized in that: In step S1, the reserved bits in the startup configuration bits are used as extended configuration bits to configure the extended startup mode in which the non-main startup XPU core is started as the host, and the bits in the startup configuration bits other than the reserved bits are used as non-extended mode configuration bits to configure the non-extended startup mode in which the main startup XPU core is used as the host to complete the chip startup.

3. The package-compatible heterogeneous multi-core chip startup expansion method according to claim 1, characterized in that: In step S2, by reading the value of the startup configuration bit in the system-level control register after the chip exits power-on reset or hot reset, if it is determined according to the value of the startup configuration bit that the target XPU core is used as the extended startup mode of the host, an enable signal of the extended startup mode is sent to the on-chip interconnect network and the clock power consumption management module, otherwise an invalid signal of the extended startup mode is sent to the on-chip interconnect network and the clock power consumption management module.

4. The package-compatible heterogeneous multi-core chip startup expansion method according to claim 3, characterized in that: In step S3, when the clock power consumption management module receives the enable signal of the extended startup mode, it controls to turn on the target peripheral clock at the end of power-on reset and hot reset; when the clock power consumption management module receives the invalid signal of the extended startup mode, it turns off the peripheral clock at the end of power-on reset and hot reset.

5. The package-compatible heterogeneous multi-core chip startup expansion method according to claim 4, characterized in that: In step S3, when the on-chip interconnect network receives an enable signal of the extended startup mode, the address space accessible to the target XPU core after power-on is mapped to the FLASH space connected to the target peripheral. When the on-chip interconnect network receives an invalid signal of the extended startup mode, the target XPU core is controlled to complete the startup as a slave.

6. The package-compatible heterogeneous multi-core chip startup expansion method according to any one of claims 1 to 5, characterized in that: In step S3, when an invalid signal of the extended startup mode is received, the address space accessible to the XPU after power-on is divided into two segments, the first segment address is mapped to the end of the on-chip storage space for storing the page table configuration segment of the XPU, and the second segment address is mapped to the designated storage space for storing the jump program, so as to control the target XPU kernel to complete the startup according to the slave.

7. The package-compatible heterogeneous multi-core chip startup expansion method according to any one of claims 1 to 5, characterized in that: In step S4, the startup program required for the target XPU core to start up includes a page table configuration program and a jump program. When the target XPU core is powered on, the target XPU core accesses the storage space connected to the target peripheral device to execute the configuration page table and then jumps to execute the main program.

8. A package-compatible heterogeneous multi-core chip startup expansion device, used to expand the non-main startup XPU core as the host to complete the chip startup, characterized in that: include: A configuration module, used to configure the startup mode for the startup configuration bit, wherein the startup configuration bit is provided with a configuration bit of an extended startup mode, wherein the extended startup mode is a startup mode in which the target XPU core is used as a host to complete chip startup, and the target XPU core is a non-main startup XPU core; A startup mode judgment module is used to read the value of the startup configuration bit after the chip exits power-on reset or hot reset, and judge the startup mode according to the value of the startup configuration bit. If it is judged to be an extended startup mode, an enable signal of the extended startup mode is sent; An extended startup mode configuration module, for controlling the start of a destination peripheral clock when receiving an enable signal of the extended startup mode, and mapping an address space accessible to the target XPU core after power-on to a storage space connected to the destination peripheral; The program burning module is used to burn the startup program required for starting the target XPU core into the storage space connected to the target peripheral, so that after the target XPU core is powered on, the startup program is executed by accessing the storage space connected to the target peripheral, completing the startup initialization configuration of the target XPU core as the host.

9. A heterogeneous multi-core chip, comprising a processor and a memory, wherein the memory is used to store a computer program, characterized in that: The processor is configured to execute the computer program to perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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