RAM write protection method and module based on register control device
By setting up a write protection module containing enable registers and logic AND gates before the write input port of the RAM in the register control device, the problems of complexity of existing RAM write protection methods and waste of resources are solved, and the effectiveness of proprietary RAM is achieved Protection and high reliability write protection.
Patent Information
- Application Number
- CN202411665551.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-02-25
AI Technical Summary
The existing RAM write protection methods are too complex, have high requirements for programmers and are difficult to understand, and there is a problem of waste of resources.
Design a RAM write protection method based on a register control device. By setting a write protection module before the write input port of the RAM in the register control device, the module includes an enable register and a logic AND gate, and control using the enable register Timing protects the write input of RAM.
It realizes effective protection of proprietary RAM, avoids misoperation of other software, is simple to understand, and requires very few additional resources to control, reduces costs and improves the reliability of RAM write protection.
Smart Images
Figure CN119512990A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of register hardware design, and in particular relates to a RAM write protection method and module based on a register control device. Background Art
[0002] When software and hardware interact, there is often a many-to-one situation in which software operates hardware, which brings many risks of misoperation during operation. In particular, some proprietary special RAMs do not allow miswrite operations by non-specified software, otherwise it will cause process errors or even system crashes.
[0003] One of the existing write protection methods is the limit protection method: multiple limit registers are set in the RAM, and each software program occupies a pair of limit registers. When reading and writing are executed, the upper and lower limits are stored in the limit registers. This protection method protects the storage block and is applied to segment management.
[0004] The second existing write protection method is the key protection method: each page of the memory is set as a storage device, and a key number is assigned, which is stored in the table entry of the block table. For each page of each user's software program, a program key is also set and a key number is assigned. When the page is accessed, the page number and its key number are registered in the block table, and the program key number is sent to the program status word. Each time the memory is accessed, the key number is compared first. Access is allowed only if the key numbers are equal, just like a key can only open one lock. The allocation of storage key and program key numbers is completed by the core operating system.
[0005] The existing write protection method is too complicated, has high requirements on programmers, and is difficult to understand. The method of adding an additional block table will cause a waste of resources. Summary of the invention
[0006] In order to solve the above problems existing in the prior art, the present invention provides a RAM write protection method and module based on a register control device. The technical problem to be solved by the present invention is achieved through the following technical solutions:
[0007] In a first aspect, the present invention provides a RAM write protection method based on a register control device, comprising:
[0008] Acquire a peripheral port of a RAM in a register control device; the peripheral port includes a write input terminal;
[0009] Designing a write protection module before the write input terminal;
[0010] The write input of the RAM is protected according to the control timing of the write protection module.
[0011] Optionally, the peripheral port also includes a data input terminal, and the write protection module includes an enable register and a logic AND gate; the output and data input terminal of the enable register are both connected to the input of the logic AND gate, and the output of the logic AND gate is connected to the write input terminal.
[0012] Optionally, the enable register is provided with a power supply terminal, a ground terminal, a clock terminal, an address input terminal, a data terminal, a reset terminal and an enable output terminal; the enable output terminal is connected to the first input terminal of the logic AND gate.
[0013] Optionally, before protecting the write input of the RAM according to the control timing of the write protection module, the RAM write protection method based on the register control device further includes:
[0014] Configuring the clock terminal to input a periodic clock signal;
[0015] The reset terminal is configured as 1 or 0, wherein the configuration as 1 indicates that the user configuration is reset, and the configuration as 0 indicates that the user configuration is not reset;
[0016] The data terminal is configured as 1 or 0, wherein 1 indicates input data and 0 indicates no input data;
[0017] The enable output terminal is configured to output 1 or 0, wherein output 1 indicates enable, and output 0 indicates disable.
[0018] Optionally, protecting the write input of the RAM according to the control timing of the write protection module includes:
[0019] According to the control timing of the enable register outputting a 0 disable signal in the initial state, an enable signal outputting a 1 in the enabled state, and a 0 disable signal in the disabled state, the output of the logic AND gate is controlled to protect the write input of the RAM.
[0020] Optional,
[0021] The enable register is in an initial state when it is powered on for the first time or the user configures the reset terminal to be 1;
[0022] When the enable register is in a normal working state and the data terminal is configured as 1, it is in an enabled state;
[0023] When the enable register is in a normal working state and the data terminal is configured as 0, it is in a non-enabled state.
[0024] In a second aspect, the present invention provides a RAM write protection module based on a register control device, wherein the write protection module is arranged before the write input port of the RAM in the register control device, and is used to protect the write input of the RAM.
[0025] Optionally, the write protection module includes an enable register and a logic AND gate; the output of the enable register and the data input of the RAM are both connected to the input of the logic AND gate; and the output of the logic AND gate is connected to the write input of the RAM.
[0026] Optionally, the enable register is provided with a power supply terminal, a ground terminal, a clock terminal, an address input terminal, a data terminal, a reset terminal and an enable output terminal; the enable output terminal is connected to the first input terminal of the logic AND gate.
[0027] Optionally, the clock terminal is configured to input a periodic clock signal; the reset terminal is configured to 1 or 0, where 1 indicates user-configured reset, and 0 indicates user-configured non-reset; the data terminal is configured to 1 or 0, where 1 indicates input data, and 0 indicates no input data; the enable output terminal is configured to output 1 or 0, where output 1 indicates enable, and output 0 indicates disable.
[0028] Beneficial effects:
[0029] The present invention provides a RAM write protection method and module based on a register control device, and provides a write protection module, which includes a special EN register. The designated software only needs to bind the register to safely operate the proprietary RAM, and cooperates with the control of the register to protect the proprietary RAM from being misoperated by other software in the entire operation process. The present invention is simple to operate and easy for programmers to understand. The additional resources required for control are very small, which reduces the cost. The present application improves the reliability of RAM write protection in the lowest cost and most effective way.
[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 It is a flow chart of a RAM write protection method based on a register control device provided by the present invention;
[0032] Figure 2 It is a schematic diagram of the connection between the write protection module and the RAM provided by the present invention;
[0033] Figure 3 is a schematic diagram of an enable register provided by the present invention;
[0034] Figure 4 It is a control timing diagram of the enable register provided by the present invention. DETAILED DESCRIPTION
[0035] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.
[0036] Combination Figure 1 and Figure 2 The present invention provides a RAM write protection method based on a register control device, comprising:
[0037] S1, obtaining a peripheral port of a RAM in a register control device; the peripheral port includes a write input terminal; the peripheral port of the present application also includes a data input terminal.
[0038] S2, designing a write protection module before the write input terminal;
[0039] refer to Figure 3 The write protection module includes an enable register and a logic AND gate; the output and data input of the enable register are connected to the input of the logic AND gate, and the output of the logic AND gate is connected to the write input. The enable register is provided with a power supply terminal, a ground terminal, a clock terminal, an address input terminal, a data terminal, a reset terminal and an enable output terminal; the enable output terminal is connected to the first input terminal of the logic AND gate.
[0040] S3, protecting the write input of the RAM according to the control timing of the write protection module.
[0041] The present invention provides a RAM write protection method based on a register control device. The present invention provides a special write protection module, which includes a special EN register. The designated software only needs to bind the register to safely operate the proprietary RAM, and cooperate with the control of the register to protect the proprietary RAM from being misoperated by other software in the entire operation process. The present invention is simple to operate and easy for programmers to understand. The additional resources required for control are very small, which reduces the cost. The present application improves the reliability of RAM write protection in the lowest cost and most effective way.
[0042] As an optional implementation manner of the present invention, before protecting the write input of the RAM according to the control timing of the write protection module, the RAM write protection method based on the register control device further includes:
[0043] Configuring the clock terminal to input a periodic clock signal;
[0044] The reset terminal is configured as 1 or 0, wherein the configuration as 1 indicates that the user configuration is reset, and the configuration as 0 indicates that the user configuration is not reset;
[0045] The data terminal is configured as 1 or 0, wherein 1 indicates input data and 0 indicates no input data;
[0046] The enable output terminal is configured to output 1 or 0, wherein output 1 indicates enable, and output 0 indicates disable.
[0047] As an optional implementation manner of the present invention, protecting the write input of the RAM according to the control timing of the write protection module includes:
[0048] According to the control timing of the enable register outputting a 0 disable signal in the initial state, an enable signal outputting a 1 in the enabled state, and a 0 disable signal in the disabled state, the output of the logic AND gate is controlled to protect the write input of the RAM.
[0049] Among them, the enable register is in an initial state when it is powered on for the first time or the user configures the reset end to 1; when the enable register is in a normal working state and the data end is configured to 1, it is in an enabled state; when the enable register is in a normal working state and the data end is configured to 0, it is in a disabled state.
[0050] like Figure 2 As shown, the present invention provides a RAM write protection module based on a register control device, wherein the write protection module is arranged before the write input port of the RAM in the register control device, and is used to protect the write input of the RAM.
[0051] This application adds a write protection module to the original software and hardware interaction process. The write protection module uses the EN register to control the write protection, that is, Figure 2 The EN_device circuit in the system is simple to operate, easy to understand, and highly reliable, which improves the robustness of the system when multiple programs frequently access the internal RAM of the device during operation.
[0052] refer to Figure 3 , the write protection module includes an enable register EN_device and a logic AND gate; the output of the enable register and the data input of the RAM are both connected to the input of the logic AND gate; the output of the logic AND gate is connected to the write input of the RAM. The enable register is a register, which is provided with a power supply terminal, a ground terminal, a clock terminal, an address input terminal, a data terminal, a reset terminal and an enable output terminal; the enable output terminal is connected to the first input terminal of the logic AND gate.
[0053] The clock terminal CLK is configured to input a periodic clock signal; the reset terminal Rst is configured to 1 or 0, where 1 indicates a user-configured reset, and 0 indicates a user-configured non-reset; the data terminal Data is configured to 1 or 0, where 1 indicates input data, and 0 indicates no input data; the enable output terminal EN_OUT is configured to output 1 or 0, where output 1 indicates enable, and output 0 indicates disable. Addr is the address input terminal, power is the power supply terminal, and GND is the ground terminal.
[0054] The control timing of the enable register block EN_device of the present invention is as follows: Figure 4 As shown, when the enable register EN_device is powered on for the first time or the user configures a reset (Rst), the EN_device is in the initial state, and the default output is 0, that is, the RAM is in the non-enabled state by default; when the EN_device is in the normal working state, when the user configures the Data to 1, the EN_device logic is in the enabled state, and the output is 1, that is, the RAM enters the enabled state; when the EN_device is in the normal working state, when the user configures the Data to 0, the EN_device logic is in the non-enabled state, and the output is 0, that is, the RAM enters the non-enabled state.
[0055] The present invention provides a RAM write protection module based on a register control device, the write protection module includes a special EN register, and the designated software can safely operate the proprietary RAM only after binding the register, and cooperate with the control of the register to protect the proprietary RAM from being misoperated by other software in the entire operation process. The present invention is simple to operate and easy for programmers to understand, and requires very few additional resources for control, thereby reducing costs; the present application improves the reliability of RAM write protection in the lowest cost and most effective way.
[0056] It is worth noting that the terms "first" and "second" in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0057] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components or steps.
[0058] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.
Claims
1. A RAM write protection method based on a register control device, characterized in that: include: Acquire a peripheral port of a RAM in a register control device; the peripheral port includes a write input terminal; Designing a write protection module before the write input terminal; The write input of the RAM is protected according to the control timing of the write protection module.
2. The RAM write protection method based on the register control device according to claim 1, characterized in that: The peripheral port also includes a data input terminal, and the write protection module includes an enable register and a logic AND gate; the output and data input terminal of the enable register are both connected to the input of the logic AND gate, and the output of the logic AND gate is connected to the write input terminal.
3. The RAM write protection method based on the register control device according to claim 2, characterized in that: The enable register is provided with a power supply terminal, a ground terminal, a clock terminal, an address input terminal, a data terminal, a reset terminal and an enable output terminal; the enable output terminal is connected to the first input terminal of the logic AND gate.
4. The RAM write protection method based on the register control device according to claim 3, characterized in that: Before protecting the write input of the RAM according to the control timing of the write protection module, the RAM write protection method based on the register control device further includes: Configuring the clock terminal to input a periodic clock signal; The reset terminal is configured as 1 or 0, wherein the configuration as 1 indicates that the user configuration is reset, and the configuration as 0 indicates that the user configuration is not reset; The data terminal is configured as 1 or 0, wherein 1 indicates input data and 0 indicates no input data; The enable output terminal is configured to output 1 or 0, wherein output 1 indicates enable, and output 0 indicates disable.
5. The RAM write protection method based on the register control device according to claim 4, characterized in that: The protecting the write input of the RAM according to the control timing of the write protection module includes: According to the control timing of the enable register outputting a 0 disable signal in the initial state, an enable signal outputting a 1 in the enabled state, and a 0 disable signal in the disabled state, the output of the logic AND gate is controlled to protect the write input of the RAM.
6. The RAM write protection method based on the register control device according to claim 5, characterized in that: The enable register is in an initial state when it is powered on for the first time or the user configures the reset terminal to be 1; When the enable register is in a normal working state and the data terminal is configured as 1, it is in an enabled state; When the enable register is in a normal working state and the data terminal is configured as 0, it is in a non-enabled state.
7. A RAM write protection module based on a register control device, characterized in that: The write protection module is arranged before the write input port of the RAM in the register control device, and is used for protecting the write input of the RAM.
8. The RAM write protection module based on the register control device according to claim 7, characterized in that: The write protection module includes an enable register and a logic AND gate; the output of the enable register and the data input terminal of the RAM are both connected to the input of the logic AND gate; the output of the logic AND gate is connected to the write input terminal of the RAM.
9. The RAM write protection module based on the register control device according to claim 8, characterized in that: The enable register is provided with a power supply terminal, a ground terminal, a clock terminal, an address input terminal, a data terminal, a reset terminal and an enable output terminal; the enable output terminal is connected to the first input terminal of the logic AND gate.
10. The RAM write protection module based on the register control device according to claim 9, characterized in that: The clock terminal is configured to input a periodic clock signal; the reset terminal is configured to 1 or 0, where 1 indicates a user-configured reset, and 0 indicates a user-configured non-reset; the data terminal is configured to 1 or 0, where 1 indicates input data, and 0 indicates no input data; the enable output terminal is configured to output 1 or 0, where output 1 indicates enable, and output 0 indicates disable.