A complex instruction set verification method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a complex instruction set verification method and device, electronic equipment and storage medium, the method comprising: obtaining a target excitation signal; determining random data corresponding to the target excitation signal according to the target excitation signal, wherein the random data at least includes input instruction data and input instruction that can be operated; determining a random calculation result corresponding to the random data according to the random data; determining a verification result corresponding to the target excitation signal according to the random calculation result and the preset output result, in the embodiments of the present application, the UVM verification methodology is used to construct a verification platform to verify the complex instruction set of the chip, which aims to verify the complex instruction set by using all input instruction data in the random complex instruction set calculation process, and to judge the correctness of the complex instruction set in the chip, thereby providing the verification efficiency of the instruction set in the chip and saving manpower and material resources.

Description

TECHNICAL FIELD

[0001] The application relates to the chip testing technical field, in particular to a complex instruction set verification method and device, electronic equipment and storage medium. BACKGROUND

[0002] With the progress of society, the development of chip technology is becoming more and more rapid, and the requirements for chips are also becoming higher and higher. The complexity of the chip is higher, and the complexity of the verification work is also increased, which leads to the verification work occupying most of the chip design cycle.

[0003] The traditional verification method is to use the verilog language to build a verification platform. After the verification platform is built, the instruction set of the chip is verified. In actual application, the chip can be applied to different projects, and the instructions corresponding to different functions of the chip need to be verified. Therefore, professional personnel need to modify the verification code of the verification platform, which has poor portability and needs to spend a lot of manpower and material resources for maintenance. Therefore, how to improve the chip instruction verification efficiency is an urgent problem to be solved. SUMMARY

[0004] Some embodiments of the application aim to provide a complex instruction set verification method and device, electronic equipment and storage medium. Through the technical scheme of the embodiments of the application, the target excitation signal is obtained. According to the target excitation signal, the random data corresponding to the target excitation signal is determined, wherein the random data at least includes input instruction data and input instruction operation. According to the random data, the random calculation result corresponding to the random data is determined. According to the random calculation result and the preset output result, the verification result corresponding to the target excitation signal is determined, wherein the preset output result is determined according to the reference model stored in advance. In the embodiments of the application, the UVM verification methodology is used to build a verification platform to verify the complex instruction set of the chip. The purpose is to verify the complex instruction set by fully using all input instruction data in the random complex instruction set calculation process, and to judge the correctness of the complex instruction set in the chip. The verification efficiency of the instruction set in the chip is provided, and the manpower and material resources are saved.

[0005] In a first aspect, some embodiments of the application provide a complex instruction set verification method, comprising:

[0006] obtaining a target excitation signal;

[0007] determining random data corresponding to the target excitation signal according to the target excitation signal, wherein the random data at least includes input instruction data and input instruction operation;

[0008] determining a random calculation result corresponding to the random data according to the random data;

[0009] Based on the random calculation results and the preset output results, a verification result corresponding to the target excitation signal is determined, wherein the preset output results are determined based on a pre-stored reference model.

[0010] Some embodiments of this application construct a verification platform using the UVM verification methodology to verify the complex instruction set of the chip. The aim is to verify the complex instruction set by using all input instruction data in the process of fully random complex instruction set calculation, and to determine the correctness of the complex instruction set within the chip. This improves the verification efficiency of the instruction set within the chip and saves manpower and resources.

[0011] Optionally, determining the verification result corresponding to the target excitation signal based on the random calculation result and the preset output result includes:

[0012] If the random calculation result matches the preset output result, then the instruction set to be verified is successfully verified according to the target excitation signal;

[0013] If the random calculation result does not match the preset output result, the verification of the instruction set to be verified fails according to the target excitation signal.

[0014] Some embodiments of this application compare the actual calculated random calculation results with the preset output results to judge the instruction set to be verified, thereby improving the accuracy of instruction set verification.

[0015] Optionally, the pre-stored reference model includes at least the correspondence between excitation signals and preset output results.

[0016] Optionally, matching the random calculation result with the preset output result includes:

[0017] Generate the first array from the preset output results;

[0018] The random calculation results are used to generate a second array;

[0019] The first array and the second array are output to the scoreboard so that the scoreboard matches the first array and the second array.

[0020] Optionally, the method further includes:

[0021] Based on the target excitation signal and the random calculation result, the functional coverage corresponding to the target excitation signal is determined.

[0022] Some embodiments of this application statistically analyze the coverage of all input data and ensure, after thorough verification, that the corresponding range of all input data is covered.

[0023] Secondly, some embodiments of this application provide a complex instruction set verification apparatus, including:

[0024] The acquisition module is used to acquire the target excitation signal;

[0025] A generation module is used to determine random data corresponding to the target excitation signal based on the target excitation signal, wherein the random data includes at least input instruction data and operable data in the input instruction;

[0026] The calculation module is used to determine the random calculation result corresponding to the random data based on the random data;

[0027] The verification module is used to determine the verification result corresponding to the target excitation signal based on the random calculation result and the preset output result, wherein the preset output result is determined based on a pre-stored reference model.

[0028] Some embodiments of this application construct a verification platform using the UVM verification methodology to verify the complex instruction set of the chip. The aim is to verify the complex instruction set by using all input instruction data in the process of fully random complex instruction set calculation, and to determine the correctness of the complex instruction set within the chip. This improves the verification efficiency of the instruction set within the chip and saves manpower and resources.

[0029] Optionally, the verification module is used for:

[0030] The random calculation result is matched with the preset output result;

[0031] If the random calculation result matches the preset output result, then the instruction set to be verified is successfully verified according to the target excitation signal;

[0032] If the random calculation result does not match the preset output result, the verification of the instruction set to be verified fails according to the target excitation signal.

[0033] Some embodiments of this application compare the actual calculated random calculation results with the preset output results to judge the instruction set to be verified, thereby improving the accuracy of instruction set verification.

[0034] Optionally, the pre-stored reference model includes at least the correspondence between excitation signals and preset output results.

[0035] Optionally, the verification module is used for:

[0036] Generate the first array from the preset output results;

[0037] The random calculation results are used to generate a second array;

[0038] The first array and the second array are output to the scoreboard so that the scoreboard matches the first array and the second array.

[0039] Optionally, the verification module is used for:

[0040] Based on the target excitation signal and the random calculation result, the functional coverage corresponding to the target excitation signal is determined.

[0041] Some embodiments of this application statistically analyze the coverage of all input data and ensure, after thorough verification, that the corresponding range of all input data is covered.

[0042] Thirdly, some embodiments of this application provide an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, can implement the complex instruction set verification method as described in any embodiment of the first aspect.

[0043] Fourthly, some embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the complex instruction set verification method as described in any embodiment of the first aspect.

[0044] Fifthly, some embodiments of this application provide a computer program product, the computer program product including a computer program, wherein when the computer program is executed by a processor, it can implement the complex instruction set verification method as described in any embodiment of the first aspect. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of some embodiments of this application, the accompanying drawings used in some embodiments of this application will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A flowchart illustrating a complex instruction set verification method provided in an embodiment of this application;

[0047] Figure 2 A flowchart illustrating another complex instruction set verification method provided in this application embodiment;

[0048] Figure 3 A flowchart illustrating another complex instruction set verification method provided in an embodiment of this application;

[0049] Figure 4A schematic diagram of a complex instruction set verification device provided in an embodiment of this application;

[0050] Figure 5 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0051] The technical solutions of some embodiments of this application will now be described with reference to the accompanying drawings.

[0052] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0053] With societal progress, chip technology is developing rapidly, and the requirements for chips are becoming increasingly stringent. The more complex the chip, the more complex the verification process becomes, resulting in verification taking up most of the entire chip design cycle.

[0054] Traditional verification methods utilize Verilog to build a verification platform. Once the platform is built, the chip's instruction set is verified. However, in practical applications, chips can be used in different projects, requiring verification of instructions corresponding to different chip functions. This necessitates modification of the verification platform's code by professionals, resulting in poor portability and requiring significant manpower and resources for maintenance. Therefore, improving chip instruction verification efficiency is a pressing issue. In light of this, some embodiments of this application provide a complex instruction set verification method. This method includes acquiring a target stimulus signal; determining random data corresponding to the target stimulus signal based on the target stimulus signal; and... The random data includes at least input instruction data and operable operations within the input instructions. Based on the random data, a random calculation result corresponding to the random data is determined. Based on the random calculation result and the preset output result, a verification result corresponding to the target excitation signal is determined. The preset output result is determined based on a pre-stored reference model. In this embodiment, a verification platform is constructed using the UVM verification methodology to verify the complex instruction set of the chip. The aim is to verify the complex instruction set by using all input instruction data in the process of fully randomizing the complex instruction set and to determine the correctness of the complex instruction set within the chip. This improves the verification efficiency of the instruction set within the chip and saves manpower and resources.

[0055] like Figure 1 As shown, an embodiment of this application provides a method for verifying complex instruction sets, the method comprising:

[0056] S101. Obtain the target excitation signal;

[0057] Specifically, a simulation platform is installed on the terminal device and connected to the chip to be verified through the simulation platform. According to the project requirements, the target excitation signal of the chip to be verified is set. The target excitation signal can be a digital signal, such as a square wave signal, or other test data.

[0058] S102. Based on the target excitation signal, determine the random data corresponding to the target excitation signal, wherein the random data includes at least the input instruction data and the operable data in the input instruction;

[0059] Specifically, the terminal device finds the random data corresponding to the target excitation signal in a pre-stored instruction set based on the input target excitation signal. The random data includes input instruction data and operable operations in the input instruction, wherein the operable operations in the input instruction include at least saturation and rounding.

[0060] For example, if the input target excitation signal is a digital signal, then the input instruction data corresponding to the digital signal is determined based on the digital signal, and the random number of times the input instruction data is generated is set.

[0061] S103. Based on the random data, determine the random calculation result corresponding to the random data;

[0062] Specifically, the terminal device transmits the random data to the design under test, and by executing the design under test, obtains the random calculation result corresponding to the random data.

[0063] S104. Based on the random calculation results and the preset output results, determine the verification result corresponding to the target excitation signal, wherein the preset output results are determined based on the pre-stored reference model.

[0064] Specifically, the terminal device has a reference model pre-stored. The excitation signal is input into the reference model to obtain a preset output result. After obtaining the random calculation result, the terminal device compares the random calculation result with the preset output result and determines the verification result corresponding to the target excitation signal based on the comparison result.

[0065] Some embodiments of this application construct a verification platform using the UVM (Universal Verification Methodology) verification methodology to verify the complex instruction set of the chip. The aim is to verify the complex instruction set by using all input instruction data in the process of fully random complex instruction set calculation, and to determine the correctness of the complex instruction set within the chip. This improves the verification efficiency of the instruction set within the chip and saves manpower and resources.

[0066] Another embodiment of this application further supplements the description of the complex instruction set verification method provided in the above embodiments.

[0067] Optionally, based on the random calculation results and preset output results, the verification result corresponding to the target excitation signal is determined, including:

[0068] The random calculation result is matched with the preset output result;

[0069] If the random calculation result matches the preset output result, then the verification of the instruction set to be verified is successful based on the target excitation signal;

[0070] If the random calculation result does not match the preset output result, the verification of the instruction set to be verified will fail according to the target excitation signal.

[0071] Some embodiments of this application compare the actual calculated random calculation results with the preset output results to judge the instruction set to be verified, thereby improving the accuracy of instruction set verification.

[0072] Optionally, the pre-stored reference model includes at least the correspondence between excitation signals and preset output results.

[0073] Optionally, matching the random calculation result with the preset output result includes:

[0074] Generate the first array from the preset output results;

[0075] The random calculation results are used to generate a second array;

[0076] The first array and the second array are output to the scoreboard so that the scoreboard matches the first array and the second array.

[0077] Specifically, the comparison function is performed by the scoreboard. The comparison method is to provide the output, input, and random calculation results from the reference model to the scoreboard for data comparison. This is done by providing the two sets of data to an array and then comparing the arrays.

[0078] Optionally, the method further includes:

[0079] Based on the target excitation signal and the random calculation results, determine the functional coverage corresponding to the target excitation signal.

[0080] Some embodiments of this application statistically analyze the coverage of all input data and ensure, after thorough verification, that the corresponding range of all input data is covered.

[0081] Figure 2 A flowchart illustrating another complex instruction set verification method provided in this application embodiment is shown below. Figure 2As shown, this application provides a UVM-based complex instruction set verification method. By constructing a verification platform using the UVM verification methodology, the method verifies the complex instruction set. The aim is to verify the correctness of the complex instruction set calculation by using all input data in the process of fully randomizing the complex instruction set calculation. Furthermore, the method ensures the sufficiency of the verification by guaranteeing that all data within the 32-bit range is randomly selected through functional coverage. This verification method is simple, highly reusable, and greatly improves the verification efficiency.

[0082] The terminal device in this embodiment is equipped with a verification platform, which includes at least the following modules: 1. DUT - Design Under Test, 2. interface, 3. hdl-top, hvl-top - top-level verification layer, 4. testcase, 5. sequence - stimulus, 6. virtual - virtual stimulus, 7. sequencer - stimulus generator, 8. virtualsequencer - virtual stimulus generator, 9. reference model, 10. scoreboard, 11. cov - functional coverage, 12. driver, 13. monitor, 14. env - verification environment, 15. agent transaction, 16. seq_item - randomly generated data based on the input used to calculate the instruction set, 17. agent_config - parameter configuration;

[0083] in:

[0084] hdl-top - Verification top layer, used to instantiate drivers, monitors, and interfaces and generate clock and reset signals.

[0085] hvl-top - The top-level validation layer, used to start the entire validation platform via run_test.

[0086] interface - an interface used for communication between the verification platform and the design under test (DUT).

[0087] Test cases are used to select a suitable virtual sequence of virtual stimulus generators to implement a function. Each test case represents an implementation of a complex instruction.

[0088] sequence-stimulus is used to generate instruction types and random number of iterations.

[0089] Virtual sequence - virtual stimulus, is used to collect the stimulus sequence required for a random instruction to achieve hierarchical verification, making the platform more prominent.

[0090] The sequencer is an excitation generator used to generate excitations by sending random data generated by seq_item (randomly generated data based on the input used to calculate the instruction set) to the driver.

[0091] Virtual sequencer - A virtual stimulus generator used for organizing and managing virtual sequence stimulus generators.

[0092] Reference model - A model used to perform the same functions as the design under test (DUT).

[0093] The scoreboard is used to compare the calculation results of the reference model with the data obtained from the monitor, and to determine whether the design under test (DUT) is correct based on the comparison results.

[0094] cov - Functional coverage is used to calculate the coverage of all input data and ensure that the corresponding range of all input data is covered after sufficient validation.

[0095] The driver is used to apply stimuli to the design under test (DUT) via an interface based on random input data received from the stimulus sequencer from the seq_item (randomly generated data used to compute the inputs according to the instruction set).

[0096] The monitor is used to collect port data of the design under test (DUT) through an interface and send it to the scoreboard.

[0097] env - Validation environment, used to instantiate the transaction agent, reference model, scoreboard and connect the monitor and scoreboard as well as the virtual sequencer and sequencer.

[0098] The agent-transaction base is used to instantiate the driver, monitor, and sequencer stimuli, and to connect the virtual interface seq_item_port in the driver to the output interface seq_item_export in the sequencer.

[0099] agent_config - Parameter configuration, used to standardize parameters used in all verification platforms, such as the number of instructions generated for each test case.

[0100] Figure 3A flowchart illustrating another complex instruction set verification method provided in this application embodiment is shown below. Figure 3 As shown, the process for implementing specific instruction calculation functions provided in this application includes:

[0101] Step 1: On the simulation platform, select the excitation sequence, i.e., the target excitation signal, according to the project requirements. The target excitation signal can be a digital signal or data, etc. The excitation sequence randomly generates seq_item (data randomly generated from the input used to calculate the instruction set) and then randomly calculates all the contents used in the instruction calculation, including: input data and the operations that can be performed in the input instruction, such as saturation, rounding, etc.

[0102] Step 2: The driver continuously requests seq_item from the sequencer stimulus generator until it obtains seq_item, and then sends it to the DUT for calculation.

[0103] Step 3: The monitor collects the input and output data of the DUT and sends the collected input and output data to the scoreboard.

[0104] Step 4: The scoreboard calls the reference model to obtain the preset output result, calculates based on the input data obtained from the monitor, and compares the calculated result (i.e., the random calculation result) with the preset output result to obtain the verification result.

[0105] Step 5: If the result is correct, the verification passes; if it is incorrect, the verification fails and needs to be recalculated.

[0106] It should be noted that each of the implementable methods in this embodiment can be implemented individually or in any combination without conflict. This application does not limit this.

[0107] Another embodiment of this application provides a complex instruction set verification apparatus for executing the complex instruction set verification method provided in the above embodiments.

[0108] like Figure 4 The diagram shown is a structural schematic of a complex instruction set verification device provided in an embodiment of this application. The complex instruction set verification device includes an acquisition module 401, a generation module 402, a calculation module 403, and a verification module 404, wherein:

[0109] The acquisition module 401 is used to acquire the target excitation signal;

[0110] The generation module 402 is used to determine random data corresponding to the target excitation signal based on the target excitation signal, wherein the random data includes at least input instruction data and operable data in the input instruction;

[0111] The calculation module 403 is used to determine the random calculation result corresponding to the random data based on the random data;

[0112] The verification module 404 is used to determine the verification result corresponding to the target excitation signal based on the random calculation result and the preset output result, wherein the preset output result is determined based on the pre-stored reference model.

[0113] Regarding the apparatus in this embodiment, the specific manner in which each module performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0114] Some embodiments of this application construct a verification platform using the UVM verification methodology to verify the complex instruction set of the chip. The aim is to verify the complex instruction set by using all input instruction data in the process of fully random complex instruction set calculation, and to determine the correctness of the complex instruction set within the chip. This improves the verification efficiency of the instruction set within the chip and saves manpower and resources.

[0115] Another embodiment of this application further supplements the description of the complex instruction set verification device provided in the above embodiments.

[0116] Optionally, the verification module is used for:

[0117] The random calculation result is matched with the preset output result;

[0118] If the random calculation result matches the preset output result, then the verification of the instruction set to be verified is successful based on the target excitation signal;

[0119] If the random calculation result does not match the preset output result, the verification of the instruction set to be verified will fail according to the target excitation signal.

[0120] Some embodiments of this application compare the actual calculated random calculation results with the preset output results to judge the instruction set to be verified, thereby improving the accuracy of instruction set verification.

[0121] Optionally, the pre-stored reference model includes at least the correspondence between excitation signals and preset output results.

[0122] Optionally, the verification module is used for:

[0123] Generate the first array from the preset output results;

[0124] The random calculation results are used to generate a second array;

[0125] The first array and the second array are output to the scoreboard so that the scoreboard matches the first array and the second array.

[0126] Optionally, the verification module is used for:

[0127] Based on the target excitation signal and the random calculation results, determine the functional coverage corresponding to the target excitation signal.

[0128] Some embodiments of this application statistically analyze the coverage of all input data and ensure, after thorough verification, that the corresponding range of all input data is covered.

[0129] Regarding the apparatus in this embodiment, the specific manner in which each module performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0130] It should be noted that each of the implementable methods in this embodiment can be implemented individually or in any combination without conflict. This application does not limit this.

[0131] This application also provides a computer-readable storage medium storing a computer program thereon. When the program is executed by a processor, it can implement the operation of any of the methods corresponding to the complex instruction set verification methods provided in the above embodiments.

[0132] This application also provides a computer program product, which includes a computer program, wherein when the computer program is executed by a processor, it can implement the operation of any of the methods corresponding to the embodiments of the complex instruction set verification method provided in the above embodiments.

[0133] like Figure 5 As shown, some embodiments of this application provide an electronic device 500, which includes: a memory 510, a processor 520, and a computer program stored in the memory 510 and executable on the processor 520. When the processor 520 reads the program from the memory 510 via a bus 530 and executes the program, it can implement any of the methods included in the above-described complex instruction set verification method.

[0134] Processor 520 can process digital signals and can include various computing architectures. For example, it can be a complex instruction set computer architecture, a reduced instruction set computer architecture, or an architecture that implements multiple instruction set combinations. In some examples, processor 520 can be a microprocessor.

[0135] The memory 510 can be used to store instructions executed by the processor 520 or data related to the execution of instructions. These instructions and / or data may include code for implementing some or all of the functions of one or more modules described in the embodiments of this application. The processor 520 of this disclosure embodiment can be used to execute the instructions in the memory 510 to implement the methods shown above. The memory 510 includes dynamic random access memory, static random access memory, flash memory, optical memory, or other memories well known to those skilled in the art.

[0136] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0137] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0138] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for verifying complex instruction sets, characterized in that, The method includes: Obtain the target stimulus signal; According to the target excitation signal, random data corresponding to the target excitation signal is searched in the pre-stored instruction set. The random data includes at least input instruction data and operable operations in the input instructions. The operable operations in the input instructions include at least saturation and rounding. Based on the random data, determine the random calculation result corresponding to the random data; Based on the random calculation results and the preset output results, a verification result corresponding to the target excitation signal is determined, wherein the preset output results are determined according to a pre-stored reference model, and the pre-stored reference model includes at least the correspondence between the excitation signal and the preset output results; The step of determining the verification result corresponding to the target excitation signal based on the random calculation result and the preset output result includes: matching the random calculation result and the preset output result; The matching of the random calculation result and the preset output result includes: Generate the first array from the preset output results; The random calculation results are used to generate a second array; The first array and the second array are output to the scoreboard so that the scoreboard matches the first array and the second array.

2. The complex instruction set verification method according to claim 1, characterized in that, The step of determining the verification result corresponding to the target excitation signal based on the random calculation result and the preset output result includes: The random calculation result is matched with the preset output result; If the random calculation result matches the preset output result, then the instruction set to be verified is successfully verified according to the target excitation signal; If the random calculation result does not match the preset output result, the verification of the instruction set to be verified fails according to the target excitation signal.

3. The complex instruction set verification method according to claim 1, characterized in that, The method further includes: Based on the target excitation signal and the random calculation result, the functional coverage corresponding to the target excitation signal is determined.

4. A complex instruction set verification device, characterized in that, The device includes: The acquisition module is used to acquire the target excitation signal; The generation module is used to search for random data corresponding to the target excitation signal in a pre-stored instruction set according to the target excitation signal, wherein the random data includes at least input instruction data and operable data in the input instruction; The calculation module is used to determine the random calculation result corresponding to the random data based on the random data; The verification module is used to determine the verification result corresponding to the target excitation signal based on the random calculation result and the preset output result, wherein the preset output result is determined based on a pre-stored reference model, and the pre-stored reference model includes at least the correspondence between the excitation signal and the preset output result. The step of determining the verification result corresponding to the target excitation signal based on the random calculation result and the preset output result includes: matching the random calculation result and the preset output result; The matching of the random calculation result and the preset output result includes: Generate the first array from the preset output results; The random calculation results are used to generate a second array; The first array and the second array are output to the scoreboard so that the scoreboard matches the first array and the second array.

5. The complex instruction set verification device according to claim 4, characterized in that, The verification module is used for: If the random calculation result matches the preset output result, then the instruction set to be verified is successfully verified according to the target excitation signal; If the random calculation result does not match the preset output result, the verification of the instruction set to be verified fails according to the target excitation signal.

6. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, can implement the complex instruction set verification method according to any one of claims 1-3.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, characterized in that, when the program is executed by a processor, it can implement the complex instruction set verification method according to any one of claims 1-3.

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