Layout design system and design method
By providing a layout design system in integrated circuit design and automatically replacing modules of different design models, the problem of difficult to maintain data consistency during the verification process of multiple design model modules is solved, and efficient and accurate module function verification is achieved.
Patent Information
- Application Number
- CN202411529388.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-02-25
AI Technical Summary
In integrated circuit design, it is difficult for multiple design and design modules to maintain data consistency during the verification process, which makes verification and comparison time-consuming and labor-intensive. The different differences in different design and design models will affect the standards for subsequent chip testing.
It provides a layout design system that stores reference layout and layout to be replaced by a database, and uses object reading modules, copy modules and replacement modules to automatically distinguish and replace functional modules in the design model to ensure the accuracy and efficiency of module efficacy verification of different design models.
It realizes that the modules of different design models are automatically replaced under the premise of design rules inspection and layout principles consistency verification, which improves the accuracy and efficiency of module function verification, simplifies batch module design model testing, and improves the testing efficiency.
Smart Images
Figure CN119514485A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a layout design system and a design method. Background Art
[0002] In integrated circuit design, there are often multiple design models for modules with the same function, so it is necessary to verify modules of different design models to distinguish the module functions of different design models. However, in the design of the layout, there are situations where the chip preset layer design needs to be modified due to circuit design or design rule check (DRC), layout principle consistency verification (LVS), etc. Manual operation modifies the design in the chip so that different design models involved in the verification have the same preset layer. It is difficult to achieve data consistency, verification and comparison are time-consuming and labor-intensive, and once there are many differences in multiple design models involved in the verification, the replacement of the preset layer will seriously affect the standards of subsequent chip testing. Therefore, the chips of multiple design models are placed on the same wafer for processing verification, and it is difficult to balance test efficiency and accuracy. Summary of the invention
[0003] The purpose of the present invention is to provide a layout design system and a design method, which can improve the efficiency and accuracy of layout verification.
[0004] To solve the above technical problems, the present invention is implemented through the following technical design model:
[0005] The present invention provides a layout design system, comprising:
[0006] A database storing a reference layout and at least one layout to be replaced, wherein the reference layout has a first test object, the layout to be replaced has a second test object, and the first test object and the second test object are the same functional module of the design layout;
[0007] An object reading module, which distinguishes a reference layout and the layout to be replaced from a plurality of design layouts, and obtains the first test object and the second test object;
[0008] a copy module connected to the database and outputting a plurality of copied reference layouts as copy layouts; and
[0009] A replacement module is connected to the copy module, wherein the replacement module replaces the first test object in the copy layout with the second test object, and the replacement module replaces the to-be-replaced layout with the replaced copy layout.
[0010] In one embodiment of the present invention, the first test object and the second test object have different layout design types.
[0011] In one embodiment of the present invention, the layout design system includes a naming module, which stores multiple named objects, wherein the named objects include the database, the preset layer of the reference layout, the preset layer of the layout to be replaced, the first test object and the second test object, and the naming module outputs the names of the named objects, and different named objects have different names.
[0012] In one embodiment of the present invention, the preset layer includes at least a top layer of the layout.
[0013] In one embodiment of the present invention, the copy module synchronously copies the name of the first test object when copying the data of the reference layout, and the replacement module replaces the name of the first test object with the name of the second test object when replacing the first test object.
[0014] In one embodiment of the present invention, the layout design system includes a duplicate checking module, and the duplicate checking module searches for and deletes the same preset layer names in the database according to the preset layer names of the layout to be replaced.
[0015] In one embodiment of the present invention, the database stores a file list, the file list stores the name of the named object, the naming module is allowed to update the file list, and the replacement module and the copy module are allowed to read the file list.
[0016] In one embodiment of the present invention, in the file list, the hierarchical names of the layout are sorted according to the hierarchical order of the layout, and when the first test object is replaced with the second test object according to the layout, the first test object is replaced layer by layer according to the hierarchical order of the layout, wherein the hierarchy replacement priority close to the preset layer is higher than the hierarchy replacement priority far from the preset layer.
[0017] In an embodiment of the present invention, the reference layout and the replaced layout to be replaced are arranged on the same wafer.
[0018] The present invention provides a layout design method, based on the layout design system as described above, comprising the following steps:
[0019] Get multiple design layouts from the database;
[0020] Distinguishing a reference layout and at least one layout to be replaced from the plurality of design layouts, wherein the reference layout has a first test object, the layout to be replaced has a second test object, and the first test object and the second test object are the same functional module of the design layout;
[0021] Copying a plurality of the reference layouts as copy layouts; and
[0022] The first test object in the copy layout is replaced by the second test object, and the copy layout after replacement is replaced by the layout to be replaced.
[0023] As described above, the present invention provides a layout design system and design method, which can realize automatic replacement of layout design models under the premise of design rule checking and satisfying layout principle consistency verification, thereby improving the module efficacy verification accuracy and efficiency of different design models. In addition, the layout design system and design method provided by the present invention can replace multiple layouts at the same time, and can automatically identify the layouts and modules that need to be replaced, with high replacement efficiency and extremely high replacement accuracy. For batch module design model testing, the test efficiency can be greatly improved. Based on the layout design system and design method provided by the present invention, the degree of freedom of layout design can be improved, and the efficiency of layout design and layout verification can be improved.
[0024] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical design model of the embodiment of the present invention, the drawings required for describing the embodiment will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0026] Figure 1 It is a schematic diagram of the layout design of multiple chips in one embodiment of the present invention.
[0027] Figure 2 Schematic diagram of the structure of a layout design system in one embodiment of the present invention.
[0028] Figure 3 The figure is a flow chart of a layout design method in one embodiment of the present invention.
[0029] Figure 4 FIG. 1 is a flow chart of step S200 in an embodiment of the present invention.
[0030] In the figure: 100, layout design system; 110, database upgrade; 120, input and output module; 130, object reading module; 140, naming module; 150, duplicate checking module; 160, copying module; 170, replacement module. DETAILED DESCRIPTION
[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical design model in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0032] In layout design, design rule checking is used to automatically check whether the layout design meets the design requirements of all parties. For example, the design rule checking includes bus electrical errors and component symbol errors. Bus electrical errors include bus index branch out of range, bus range syntax errors, illegal bus range values, illegal bus definitions, incorrect sorting of bus branch network labels, bus / wire connection errors, bus width errors, bus naming rule errors, etc. Layout principle consistency verification uses tools to compare the connectivity of the layout and logic diagram at the transistor level, and outputs all inconsistencies to verify whether the layout and logic diagram match. The types of errors read in the layout principle consistency verification include, for example, no device on the matching node, unmatched nodes on the matching device, unmatched devices, redundant layout devices on the matching node, redundant circuit diagram devices on the matching node, unmatched layout and circuit diagram devices on the matching node, mismatched device types (N-type and P-type, polycrystalline resistors or diffusion resistors), mismatched device sizes (W or L), MOS reversibility errors, mismatched substrate connections, mismatched device power connections (multiple power supply situations), etc. Therefore, after the design layout of the functional module comes out, in the verification process, the semiconductor device except for the part of the functional module and the part belonging to the functional module may still be changed, such as the change of the preset layer of the functional module. After verification, these changes in the layout structure will affect the comparative verification and selection of multiple design models of the functional module.
[0033] See also Figure 1 As shown, the present invention provides a layout design system for synchronously verifying multiple design models of a specific functional module. In the present invention, the design content and functional content of the specific functional module are not limited, and the present invention does not limit the number of design models included in the specific functional module. In this embodiment, Figure 1As shown, there are, for example, four module design models involved in the verification, and they are marked as design model A, design model B, design model C, and design model D. The functional modules involved in the test are marked as M, wherein the functional module M in the design model A is marked as M1, the functional module M in the design model A is marked as M2, the functional module M in the design model A is marked as M3, and the functional module M in the design model A is marked as M4. J, K, and L are used to refer to modules of the semiconductor device other than the functional module M involved in the test. The present invention does not limit the module contents of J, K, and L.
[0034] See also Figure 1 and Figure 2 As shown, the present invention provides a layout design system 100, which includes multiple databases 110, as well as an input and output module 120, an object reading module 130, an assignment module 140, a duplicate checking module 150, a copy module 160 and a replacement module 170. In this embodiment, in the layout design, when multiple design models of the functional modules of the design layout are to be verified and compared, after the design rule check and the layout principle consistency verification, the layout design system 100 is started to adjust the design layout structure of the semiconductor device involved in the test. It should be noted that when the layout design system 100 is not started, the database 110 can also be called and used to store relevant information and data of the design layout. The database 110 has a file list, which is used to store the name of the design layout in each version, the hierarchical name of the design layout, the design layout and the name of the functional module, etc.
[0035] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the database 110 is used to store layout design data, including wiring information of the design layout and size data of the design layout, as well as layout information of the design layout. The wiring information of the design layout includes wiring diagram data of the design layout. The size data of the design layout includes line width data, line length data, wiring spacing data, and the like. The layout information of the design layout includes the name and number of the database 110, the name and number of the design layout, the name and number of each level in the design layout, the name and number of each functional module in the design layout, and the like. Among them, the layout design system 100 includes multiple databases 110. Multiple databases 110 can be used to store information of different design layouts. In the present invention, different databases 110 have different names and numbers. In this embodiment, different databases 110 are distinguished by name, and the name of the database 110 is variable, while the number is unique and unchanged.
[0036] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, the input-output module 120 is connected to the database 110. After the layout design system 100 is started, the design layout to be tested is input through the input-output module 120. The design layout to be tested is a design layout of multiple semiconductor devices with different functional modules M. The specific design layout to be tested is determined by the designer or tester, and the present invention does not limit it. In this embodiment, the design layout to be tested has multiple design models, wherein the design models correspond to different functional modules M, such as Figure 1 As shown, the design model of the functional module M includes, for example, M1 of the design model A, M2 of the design model B, M3 of the design model C, and M4 of the design model D. The input-output module 120 is used to output a plurality of design layouts, wherein the plurality of design layouts are the same in terms of interface positions and directions, and layout sizes, except for the structures of the functional modules to be tested.
[0037] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the object reading module 130 is used to set and read the named object. In this embodiment, the named object includes a database 110 participating in the test, a preset layer of the reference layout, a preset layer of the layout to be replaced, a first test object, and a second test object. It should be noted that the names of different objects are different, and the naming rules are different to distinguish different named objects. The name of the named object can be customized by the designer. The data 110 participating in the test is a database 110 of the design layout source participating in the test. The preset layer of the reference layout and the preset layer of the layout to be replaced have the same level, wherein the preset layer includes at least the top layer of the layout. In this embodiment, the preset layer is the top layer of the layout. In other embodiments of the present invention, the preset layer may also include the second top layer of the layout and the next layer of the second top layer of the layout, and so on. The functional module design models of the reference layout and the layout to be replaced are different. Specifically, the reference layout is a layout under any design model. For example, in this embodiment, the layout where the design model A is located is used as the reference layout. Then the layout where the design models B, C, and D are located is used as the layout to be replaced. In this embodiment, the first test object and the second test object are functional modules M. The first test object is a functional module of the reference layout, such as M1, and the second test object is a functional module of the layout to be replaced, such as M2, M3 and M4.
[0038] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, the naming module 140 is used to name the named objects. In this embodiment, the named objects include the database 110 involved in the test, the preset layer of the reference layout, the preset layer of the layout to be replaced, the first test object and the second test object. The naming module 140 names the multiple named objects respectively, and the names of the multiple named objects are different. The names of the multiple named objects can be regular names or randomly generated names. After the naming module 140 completes the naming, the name of the named object is updated to the file list.
[0039] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after the naming module 140 completes the naming, the duplicate checking module 150 searches the database for the preset layer name of the layout to be replaced. If there is an object with the same name, the object with the same name is deleted, thereby avoiding reducing the complexity of replacing data and names. The deleted object is the preset layer of the layout to be replaced. In this embodiment, the preset layer levels of the reference layout and the layout to be replaced are the same, and the hierarchical structure of the preset layer can be the same or different.
[0040] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the copy module 160 copies the reference layout to obtain a copy layout. In this embodiment, the reference layout and the layout to be replaced are located on the same wafer, and there can be multiple reference layouts on the wafer, and there can also be multiple layouts to be replaced. When the copy module 160 performs copying, only one of the multiple reference layouts is copied. In the obtained copy layout, the preset layer and the reference layout are Figure 1 The functional module M is also consistent with the reference version. Figure 1 For example, the design type of the functional module M in the copied layout is M1. In this embodiment, when the reference layout is copied to obtain the copied layout, the layout name, the functional module name and the layout level name are also copied.
[0041] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, after obtaining the copy layout, the replacement module 170 replaces the first test object in the copy layout with the second test object. It should be noted that the design layout has multiple layers, and the functional module M also includes a multi-layer wiring structure. Therefore, in this embodiment, in the step of replacing the first test object with the second test object, the wiring structure of the first test object is replaced with the wiring structure of the second test object layer by layer. In this embodiment, the wiring structure of the first test object can be replaced layer by layer according to the hierarchical name order of the file list. Specifically, the order of the inter-layer names in the file list is the same as the hierarchical order of the layout, wherein in the step of replacing the first test object layer by layer, the hierarchical replacement priority close to the preset layer is higher than the hierarchical replacement priority far from the preset layer. Among them, after the first test object is replaced, the name of the first test object is changed to the name of the second test object, and the hierarchical name of the first test object is also replaced with the hierarchical name of the second test object.
[0042] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in the step of replacing the first test object layer by layer, the coordinates of the first test object are obtained according to the coordinates, and when replacing the second test object, the area where the second test object is located covers the area of the first test object. Specifically, the area of the second test object is equal to the area of the first test object. Among them, the interface position of the second test object coincides with the interface position of the first test object. In this embodiment, the first test objects of multiple replicated layouts are replaced at the same time, and the first test objects of multiple replicated layouts can be replaced with different second test objects respectively. For example, the design type A of the three replicated layouts is replaced with the design type B, the design type C and the design type D respectively. The design type A of the six replicated layouts is replaced with two design types B, two design types C and two design types D respectively. After the replacement is completed, the input-output module 120 outputs the replaced layout as the layout to be replaced to the database 110.
[0043] See also Figures 1 to 3 As shown, the present invention provides a layout design method based on the layout design system 100, wherein the layout design method includes steps S100 to S400.
[0044] Step S100: Acquire multiple design layouts from a database.
[0045] Step S200, distinguishing a reference layout and at least one layout to be replaced from the multiple design layouts, wherein the reference layout has a first test object, the layout to be replaced has a second test object, and the first test object and the second test object are the same functional module of the design layout.
[0046] Step S300: Copy a plurality of the reference layouts as copy layouts.
[0047] Step S400: Replace the first test object in the copy layout with the second test object, and replace the to-be-replaced layout with the replaced copy layout.
[0048] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S100, the design layout obtained from the database 110 is the same design layout, and the functional modules of the multiple design layouts have different design models. Figure 1 The design model A, the design model B, the design model C and the design model D are shown. In step S200, the step of distinguishing the reference layout and the layout to be replaced includes steps S210 to S240.
[0049] Step S210: divide a plurality of design layouts into reference layouts and layouts to be replaced.
[0050] Step S220: Name the database, the preset layer of the reference layout, the preset layer of the layout to be replaced, the first test object, and the second test object.
[0051] Step S230: Determine whether the preset layer name of the layout to be replaced is stored in the database.
[0052] Step S240: When the preset layer name of the layout to be replaced is stored in the database, the preset layer name of the layout to be replaced existing in the database is deleted; when the preset layer name of the layout to be replaced is not stored in the database, step S300 is executed.
[0053] See also Figures 1 to 4As shown, in one embodiment of the present invention, in step S210, a design layout corresponding to any design model is selected as a reference layout. Design layouts other than the reference layout are set as layouts to be replaced. Then, in step S220, they are named one by one. After the naming is completed, the judgment step of step S230 is executed. When the preset layer name of the layout to be replaced is stored in the database 110, step S240 is executed to delete the corresponding preset layer name. If the preset layer name of the layout to be replaced is not found in the database 110, step S300 is executed. In step S300, the reference layout is copied to obtain a copy layout. The number of copy layouts is equal to the number of layouts to be replaced. In step S400, the first test object in the copy layout is replaced with the second test object. Among them, the hierarchical wiring structure of the first test object of the copy layout is replaced layer by layer in the order away from the top layer. After the replacement is completed, the hierarchical name of the copy layout is updated in the file list to the name of the corresponding layout to be replaced. After all levels are replaced, the name of the copied layout is updated to the name of the corresponding layout to be replaced. In the present invention, multiple copied layouts are replaced and their names are updated synchronously, so as to obtain multiple design layouts with completely consistent preset layer distribution and only different functional modules. Using multiple design layouts for testing can not only test the differences between each functional module, but also have a relatively high test accuracy. The design method and design system provided by the present invention can complete the replacement of functional modules of the design layout in large quantities, with high replacement accuracy and high replacement efficiency, which is conducive to the comparison of various design schemes in the layout design stage, and does not affect the layout design verification.
[0054] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A layout design system, characterized in that: include: A database storing a reference layout and at least one layout to be replaced, wherein the reference layout has a first test object, the layout to be replaced has a second test object, and the first test object and the second test object are the same functional module of the design layout; An object reading module, which distinguishes a reference layout and the layout to be replaced from a plurality of design layouts, and obtains the first test object and the second test object; A copy module connected to the database and outputting a plurality of copied reference layouts as copy layouts; as well as A replacement module is connected to the copy module, wherein the replacement module replaces the first test object in the copy layout with the second test object, and the replacement module replaces the to-be-replaced layout with the replaced copy layout.
2. A layout design system according to claim 1, characterized in that: The first test object and the second test object have different layout design types.
3. A layout design system according to claim 1, characterized in that: The layout design system includes a naming module, which stores multiple named objects, wherein the named objects include the database, the preset layer of the reference layout, the preset layer of the layout to be replaced, the first test object and the second test object. The naming module outputs the names of the named objects, and different named objects have different names.
4. A layout design system according to claim 3, characterized in that: The preset layer at least includes the top layer of the layout.
5. A layout design system according to claim 3, characterized in that: The copy module copies the name of the first test object synchronously when copying the data of the reference layout, and the replacement module replaces the name of the first test object with the name of the second test object when replacing the first test object.
6. A layout design system according to claim 3, characterized in that: The layout design system includes a duplicate checking module, which searches for and deletes the same preset layer names in the database according to the preset layer names of the layout to be replaced.
7. A layout design system according to claim 3, characterized in that: The database stores a file list, in which the name of the named object is stored, allowing the naming module to update the file list, and allowing the replacement module and the copy module to read the file list.
8. A layout design system according to claim 7, characterized in that: In the file list, the hierarchical names of the layout are sorted according to the hierarchical order of the layout. When the first test object is replaced with the second test object according to the layout, the first test object is replaced layer by layer according to the hierarchical order of the layout, wherein the hierarchical replacement priority close to the preset layer is higher than the hierarchical replacement priority far from the preset layer.
9. A layout design system according to claim 1, characterized in that: The reference layout and the replaced layout to be replaced are arranged on the same wafer.
10. A layout design method, based on a layout design system as claimed in claim 1, characterized in that: The following steps are involved: Get multiple design layouts from the database; Distinguishing a reference layout and at least one layout to be replaced from the plurality of design layouts, wherein the reference layout has a first test object, the layout to be replaced has a second test object, and the first test object and the second test object are the same functional module of the design layout; Copying a plurality of the reference layouts as copy layouts; as well as The first test object in the copy layout is replaced by the second test object, and the copy layout after replacement is replaced by the layout to be replaced.