Semiconductor multilayer structure and operation method of test circuit of semiconductor multilayer structure

Abstract

The invention provides a semiconductor multilayer structure and an operation method of a test circuit of the semiconductor multilayer structure. The semiconductor multilayer structure includes: a first semiconductor wafer including a plurality of first pads; a second semiconductor wafer including a plurality of second pads combined with the plurality of first pads; and a test circuit configured to apply a first voltage to a reference combination portion in which a preset first reference pad among the plurality of first pads and a preset second reference pad among the plurality of second pads are combined, and applying a second voltage to a comparison combination portion in which at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads, the test circuit compares a voltage distributed based on a resistance ratio of the reference combination portion to the comparison combination portion with a preset reference voltage to determine whether the at least one first pad is aligned with the at least one second pad.

Description

Technical Field

[0001] Embodiments relate to semiconductor wafers and methods of operating test circuits of semiconductor wafers, and more particularly, to a semiconductor wafer including a plurality of layers and a method of operating a test circuit of the semiconductor wafer, the test circuit determining whether misalignment exists in the semiconductor wafer. Background Art

[0002] As semiconductor manufacturing technology improves, people are developing various processes for manufacturing semiconductor devices. One of the various processes includes combining two or more semiconductor bare chips to manufacture one semiconductor device or combining two or more semiconductor wafers to manufacture multiple semiconductor devices.

[0003] When combining two or more semiconductor dies or semiconductor wafers, aligning the semiconductor dies or semiconductor wafers with each other can be an important factor in determining the yield. Moreover, recently developed memory devices can operate according to various specifications, and non-volatile memory devices can each have a three-dimensional structure. In addition, non-volatile memory devices are manufactured on a wafer basis during the manufacturing process, and because the wafers are stacked in a three-dimensional structure, the individual wafers must be aligned with each other. Summary of the invention

[0004] As described above, when a semiconductor device is manufactured by combining two or more semiconductor dies or a plurality of semiconductor devices are manufactured by combining two or more semiconductor wafers, a device and method for determining whether the plurality of semiconductor wafers are aligned with each other is required. However, there is a problem that it is impossible to accurately determine whether the semiconductor wafers are aligned with each other.

[0005] According to one aspect of the present invention, a semiconductor multilayer structure includes: a first semiconductor chip, the first semiconductor chip including a plurality of first pads; a second semiconductor chip, the second semiconductor chip including a plurality of second pads combined with the plurality of first pads; and a test circuit, the test circuit being configured to apply a first voltage to a reference combination portion of a combination of a preset first reference pad among the plurality of first pads and a preset second reference pad among the plurality of second pads, and to apply a second voltage to a comparison combination portion of a combination of at least one first pad among the plurality of first pads and at least one second pad among the plurality of second pads, wherein the test circuit compares a voltage distributed based on a resistance ratio of the reference combination portion to the comparison combination portion with a preset reference voltage to determine whether the at least one first pad is aligned with the at least one second pad.

[0006] According to another aspect of the present invention, a semiconductor multilayer structure includes: a first semiconductor chip, the first semiconductor chip including a plurality of first pads; a second semiconductor chip, the second semiconductor chip including a plurality of second pads combined with the plurality of first pads; and a scanner, the scanner being configured to perform electron beam scanning of a reference combination part and a comparison combination part, wherein a preset first reference pad among the plurality of first pads is combined with a preset second reference pad among the plurality of second pads in the reference combination part, and at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads in the comparison combination part, wherein the scanner determines whether the at least one first pad is aligned with the at least one second pad based on the amount of electrons reflected from the reference combination part and the comparison combination part during the electron beam scanning.

[0007] According to another aspect of the present invention, an operating method of a test circuit for determining whether there is misalignment in a semiconductor multilayer structure including a three-dimensional memory device includes: applying a first voltage to a reference combination part, in which a preset first reference pad among a plurality of first pads in a first wafer is combined with a preset second reference pad among a plurality of second pads in a second wafer; applying a second voltage to a comparison combination part in which at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads; and determining whether the at least one first pad is aligned with the at least one second pad by comparing a voltage distributed based on a resistance ratio of the reference combination part to the comparison combination part with a preset reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 illustrates a semiconductor wafer according to one embodiment;

[0010] Figure 2A and Figure 2B is a block diagram of a semiconductor wafer according to one embodiment;

[0011] Figure 3 is a block diagram illustrating a test circuit according to one embodiment;

[0012] Figure 4A and Figure 4B is a diagram illustrating a process of determining whether a semiconductor wafer is aligned according to one embodiment;

[0013] Figure 5 and Figure 6A process of determining whether a semiconductor wafer is aligned by using a scanner according to one embodiment is illustrated;

[0014] Figure 7 is a flow chart of a method of operating a test circuit according to one embodiment;

[0015] Figure 8 is a flow chart illustrating a method of determining an alignment trend of a first pad and a second pad in an operating method of a test circuit according to one embodiment; and

[0016] Figures 9 to 11 is a view illustrating a three-dimensional V-NAND structure that may be applied to a memory device according to an embodiment. DETAILED DESCRIPTION

[0017] In the following, preferred embodiments of the present invention are described with reference to the accompanying drawings. Below, the details of configuration and structure are provided to help the reader understand the embodiments. Therefore, the embodiments described herein can be changed or modified in various ways without departing from the embodiments.

[0018] Figure 1 A first wafer WAF1 (ie, a first semiconductor wafer) and a second wafer WAF2 (ie, a second semiconductor wafer) according to an embodiment are illustrated.

[0019] refer to Figure 1 , a first wafer WAF1 is combined with a second wafer WAF2 , the first wafer WAF1 may include at least one first die DIE1 , and the second wafer WAF2 may include at least one second die DIE2 . Figure 1 The embodiment illustrates an example in which at least one first die DIE1 is combined with at least one second die DIE2.

[0020] refer to Figure 1 In order to combine the first die DIE1 with the second die DIE2, the first die DIE1 may be rotated 180 degrees in a first direction (eg, a first horizontal direction). Therefore, a coordinate system of the first die DIE1 and a coordinate system of the second die DIE2 may be separately displayed.

[0021] The first die DIE1 may include first pads arranged on an upper surface thereof in a third direction (eg, vertical direction).The first pads may be arranged at equal intervals in a first direction and a second direction (eg, a second horizontal direction perpendicular to the first horizontal direction).

[0022] The second die DIE2 may include second pads arranged on an upper surface thereof in the third direction. The second pads may be arranged at equal intervals in the first direction and the second direction.

[0023] like Figure 1 As illustrated by the cross CRS in FIG. 1 , the first wafer WAF1 and the second wafer WAF2 can be coupled / combined with each other to implement a plurality of semiconductor devices (e.g., nonvolatile memory devices). The plurality of semiconductor devices to which the first semiconductor die DIE1 and the second semiconductor die DIE2 are coupled can be obtained by coupling the first semiconductor wafer WAF1 and the second semiconductor wafer WAF2 and cutting the result of the coupling (e.g., by cutting the combined product of the first semiconductor wafer WAF1 and the second semiconductor wafer WAF2). As used herein, the term "semiconductor multilayer structure" can be used to describe the structure of the combined / coupled first wafer WAF1 and the second wafer WAF.

[0024] When the first wafer WAF1 is combined with the second wafer WAF2, the first pad of the first die DIE1 may be combined with the second pad of the second die DIE2. When the position of the first pad and the position of the second pad are accurately aligned (e.g., aligned with each other within the allowable error range), the combination of the first wafer WAF1 and the second wafer WAF2 may be successful. When the position of the first pad and the position of the second pad are not accurately aligned with each other (e.g., aligned outside the allowable error range), the combination of the first wafer WAF1 and the second wafer WAF2 may fail.

[0025] Figure 2A and Figure 2B is a block diagram of a semiconductor multilayer structure 100 according to one embodiment. Figure 2A The semiconductor multilayer structure 100 in FIG. 1 illustrates an embodiment in which alignment is determined by a test circuit 130 , and Figure 2B The semiconductor multilayer structure 100 in FIG. 1 illustrates an embodiment in which alignment is determined by the scanner 140. For example, the first semiconductor wafer WAF1 and / or the second semiconductor wafer WAF2 may be implemented with the test circuit 130 or the scanner 140.

[0026] The test circuit 130 according to one embodiment may be located on the first wafer WAF1 or the second wafer WAF2. For example, the test circuit 130 may be located on the first wafer WAF1. Alternatively, the test circuit 130 may be located on the second wafer WAF2. The scanner 140 according to one embodiment may be located on a different chip or a different wafer separate from both the first wafer WAF1 and the second wafer WAF2.

[0027] refer to Figure 2A , the semiconductor multilayer structure 100 according to one embodiment may include a reference combination part 110 , a comparison combination part 120 , and a test circuit 130 .

[0028] The reference combination part 110 according to one embodiment may be a combination part of the first reference pad 111 and the second reference pad 112. The first reference pad 111 according to one embodiment may be a reference pad selected from a plurality of first pads, and the second reference pad 112 may be a reference pad selected from a plurality of second pads. Furthermore, the plurality of first pads may be located Figure 1 On the first wafer WAF1, and a plurality of second pads may be located Figure 1 On the second wafer WAF2 in the embodiment. Moreover, the plurality of first pads and the plurality of second pads may be arranged to have a square matrix structure. For example, the first pads and the second pads may be arranged in a 9×9 structure, a 10×10 structure, or a 12×12 structure, but are not limited thereto, and may be arranged in a square matrix structure of various sizes.

[0029] The first reference pad 111 and the second reference pad 121 of the reference combination part 110 according to one embodiment may be 100% aligned with each other. A preset voltage may be applied to the reference combination part 110 according to one embodiment, and the reference combination part 110 may have a reference resistance value R1. In one embodiment, the voltage applied to the reference combination part 110 may be referred to as a first voltage. Moreover, the first voltage may be an external voltage applied from the outside of the semiconductor multilayer structure 100, or may be an internal voltage applied from the inside of the semiconductor multilayer structure 100.

[0030] The comparison combination part 120 according to one embodiment may be a combination part of a first pad 121 randomly selected from a plurality of first pads and a second pad 122 randomly selected from a plurality of second pads. A preset voltage may be applied to the comparison combination part 120 according to one embodiment, and the comparison combination part 120 may have a comparison resistance value R2. In one embodiment, the voltage applied to the comparison combination part 120 may be referred to as a second voltage. Moreover, the second voltage may be an external voltage applied from the outside of the semiconductor multilayer structure 100, or may be an internal voltage applied from the inside of the semiconductor multilayer structure 100.

[0031] The test circuit 130 according to one embodiment may compare a voltage distributed based on a resistance ratio of the reference combination part 110 and the comparison combination part 120 with a preset reference voltage to determine whether at least one first pad and at least one second pad are aligned with each other. For example, the test circuit 130 may compare a voltage distributed according to a first voltage applied to the reference combination part 110 and a second voltage applied to the comparison combination part 120 with a preset reference voltage to determine whether the first pad 121 and the second pad 122 are aligned with each other.

[0032] Moreover, the test circuit 130 may determine the degree of misalignment of the first pad 121 and the second pad 122 of the comparison combination part 120. According to one embodiment, the test circuit 130 may compare the voltage according to the distribution of the first voltage applied to the reference combination part 110 and the second voltage applied to the comparison combination part 120 with a preset reference voltage, and compare the distributed voltage with a preset answer sheet (e.g., (one or more) preset or predetermined values ​​that may be stored in a memory), thereby determining the degree to which the first pad 121 and the second pad 122 are aligned with each other. For example, the test circuit 130 may compare the voltage according to the distribution of the first voltage and the second voltage with the reference voltage of the preset answer sheet, and when misalignment is found, the test circuit 130 may check the change of the voltage according to the distribution of the first voltage and the second voltage that is changed by the change of the reference voltage, and compare the voltage with the preset answer sheet, thereby determining the degree of alignment of the first pad 121 and the second pad 122.

[0033] Moreover, the test circuit 130 may determine the alignment tendency of the first pad 121 and the second pad 122 of the comparison combination part 120. According to one embodiment, the test circuit 130 may repeat the process of comparing the voltage according to the distribution of the first voltage applied to the reference combination part 110 and the second voltage applied to the comparison combination part 120 with the preset reference voltage and determining the degree of alignment of the first pad 121 and the second pad 122. For example, the test circuit 130 may determine whether the plurality of pads are aligned with each other and the degree of alignment of the plurality of pads by comparing the voltage according to the distribution of the first voltage applied to the reference combination part 110 and the second voltage applied to the comparison combination part 120 with the preset reference voltage of the comparison combination part 120 including at least one of the plurality of first pads and at least one of the plurality of second pads.

[0034] refer to Figure 2B , the semiconductor multilayer structure 100 according to one embodiment may include a reference combination part 110 , a comparison combination part 120 , and a scanner 140 .

[0035] The description of the reference combination part 110 and the comparison combination part 120 is the same as Figure 2A and therefore, the following Figure 2B Only the scanner 140 is described in the embodiment.

[0036] The scanner 140 according to one embodiment may perform an electron beam (e-beam) scan on the reference combination part 110 and the comparison combination part 120. The scanner 140 according to one embodiment may determine whether the at least one first pad is aligned with the at least one second pad based on the amount of electrons reflected from the reference combination part 110 and the comparison combination part 120 as a result of the electron beam scanning. For example, the scanner 140 may determine whether the at least one first pad is aligned with the at least one second pad based on the colors obtained from the reference combination part 110 and the comparison combination part 120 as a result of the electron beam scanning or not.

[0037] For example, the scanner 140 emits an electron beam to the reference combination part 110 and the comparison combination part 120, and determines whether the first pad is aligned with the second pad, the alignment degree of the first pad with the second pad, and the alignment trend based on the brightness according to the amount of reflected electrons. According to one embodiment, when the first reference pad 111 and the second reference pad 121 of the reference combination part 110 are aligned with each other, the amount of reflected electrons is equal to the amount of emitted electrons, and therefore, the scanning result of the reference combination part 110 can display a brightness with a low grayscale (e.g., relatively bright). However, when the first pad 121 and the second pad 122 of the comparison combination part 120 are not aligned with each other, some of the emitted electrons are lost, and the amount of reflected electrons can be less than the amount of emitted electrons. When the amount of reflected electrons is less than the amount of emitted electrons, the scanning result of the comparison combination part 120 can display a brightness with a high grayscale (e.g., relatively dark). As a result of the scan, the reference combination part 110 according to one embodiment can be displayed as relatively bright, and the portion of the comparison combination part 120 in which there is misalignment can be displayed as dark.

[0038] The scanner 140 according to one embodiment may determine the alignment trend and misalignment degree of the first pad and the second pad based on the scanning result. For example, when there are many bright parts as the scanning result, the scanner 140 may determine that the plurality of first pads are aligned with the second pad. However, when there are many dark parts as the scanning result, the scanner 140 may determine that there are many misaligned combined parts among the combined parts of the plurality of first pads and the plurality of second pads.

[0039] Figure 3 is a block diagram illustrating the test circuit 130 according to one embodiment.

[0040] refer to Figure 3, the test circuit 130 according to one embodiment may include a multiplexer (MUX) 131, a comparator 132, a reference voltage pad 133, and an output terminal 134. The reference combination part 110 according to one embodiment may be connected to the first voltage pad 113 to receive the first voltage, and may have a reference resistance value R1. The comparison combination part 120 according to one embodiment may be connected to the second voltage pad 123 to receive the second voltage, and may have a comparison resistance value R2.

[0041] According to one embodiment, the test circuit 130 may be connected to the reference combination part 110 and the comparison combination part 120 through a multiplexer 131. The comparison combination part 120 according to one embodiment may include a plurality of first pads 121_1, 121_2, 121_3, 121_4, ..., 121_n and a plurality of second pads 122_1, 122_2, 122_3, 122_4, ..., 122_n, and the plurality of first pads 121_1, 121_2, 121_3, 121_4, ..., 121_n may be connected to the plurality of second pads 122_1, 122_2, 122_3, 122_4, ..., 122_n, respectively. The test circuit 130 according to one embodiment may independently determine whether the combination of the plurality of first pads and the plurality of second pads is aligned. The test circuit 130 compares the voltage Vfb according to the distribution of the first voltage and the second voltage with the reference voltage VREF, and when it is determined that the voltage Vfb according to the distribution of the first voltage and the second voltage is equal to the reference voltage VREF, the test circuit 130 can determine that the multiple first pads are aligned with the multiple second pads.

[0042] The test circuit 130 according to one embodiment may compare the voltage Vfb according to the distribution of the first voltage and the second voltage with the reference voltage VREF and adjust the reference voltage VREF according to the comparison result. For example, the test circuit 130 may adjust the reference voltage VREF based on the output voltage of the comparator 132.

[0043] When the output voltage of the comparator 132 according to one embodiment is different from the preset answer sheet, the semiconductor multilayer structure 100 may input a reference voltage VREF higher than the first voltage and the second voltage to the comparator 132, so that the output voltage of the comparator 132 is at a logic high level, and then reduce the reference voltage VREF. For example, when the reference voltage VREF is higher than the voltage Vfb according to the distribution of the first voltage and the second voltage, the test circuit 130 may reduce the reference voltage. When the reference voltage VREF is reduced, the voltage Vfb according to the distribution of the first voltage and the second voltage may be equal to the reference voltage VREF at a certain time point. The test circuit 130 according to one embodiment may determine the alignment degree and alignment trend of the plurality of first pads with the plurality of second pads based on the amount of change of the reference voltage VREF. For example, until the voltage Vfb according to the distribution of the first voltage and the second voltage is equal to the reference voltage VREF, the alignment degree and alignment trend of the plurality of first pads with the plurality of second pads may be determined based on the change of the reference voltage VREF, and when the change increases, the test circuit 130 may determine that the misalignment rate of the plurality of first pads with the plurality of second pads has increased.

[0044] Figure 4A and Figure 4B is a diagram illustrating a process of determining whether a semiconductor multilayer structure 100 is aligned according to one embodiment.

[0045] Figure 4A FIG. 1 illustrates a preset answer sheet for determining whether the semiconductor multilayer structure 100 is aligned according to an embodiment. Figure 4A , according to one embodiment, the reference combination part 110 may have a misalignment of 0%. According to one embodiment, the preset answer sheet may include a comparison combination part having a high misalignment rate toward the edge of the semiconductor multilayer structure 100. According to one embodiment, the semiconductor multilayer structure 100 may include a first wafer and a second wafer, the first wafer including a plurality of first pads 121_1, 121_2, 121_3, 121_4, ..., 121_n, and the second wafer including a plurality of second pads 122_1, 122_2, 122_3, 122_4, ..., 122_n. According to one embodiment, the semiconductor multilayer structure 100 may compare the preset answer sheet with the reference combination part 110. Figure 1 and Figure 3 The outputs of the disclosed test circuit 130 are compared to determine the alignment or misalignment and alignment trends of the plurality of first pads 121_1, 121_2, 121_3, 121_4, ..., 121_n and the plurality of second pads 122_1, 122_2, 122_3, 122_4, ..., 122_n.

[0046] refer to Figure 4B , when a test operation is performed on the semiconductor multilayer structure 100 according to an embodiment, there is Figure 3 The region where the voltage Vfb increases according to the distribution of the first voltage and the second voltage and the region where the voltage Vfb decreases according to the distribution of the first voltage and the second voltage. In the semiconductor multilayer structure 100 according to one embodiment, the region where the voltage Vfb decreases according to the distribution of the first voltage and the second voltage may be determined to have a high misalignment combination ratio.

[0047] Figure 5 and Figure 6 A process of determining the alignment of the semiconductor multilayer structure 100 by using a scanner according to one embodiment is illustrated.

[0048] refer to Figure 3 , Figure 5 and Figure 6 , the amount of reflected electrons when the plurality of first pads 121 and the plurality of second pads 122 are aligned with each other according to one embodiment may be greater than the amount of reflected electrons when the plurality of first pads 121 and the plurality of second pads 122 are not aligned with each other. According to one embodiment, when the plurality of first pads 121 are not aligned with the plurality of second pads 122, some of the emitted electrons are lost, and the amount of reflected electrons may be less than the amount of emitted electrons. When the amount of reflected electrons is less than the amount of emitted electrons, a brightness with a high grayscale level may be displayed as a scanning result. The scanner 140 according to one embodiment may determine the alignment trend and misalignment degree of the plurality of first pads 121 and the plurality of second pads 122 based on the scanning result. For example, when there are many bright parts as a scanning result, the scanner 140 may determine that the plurality of first pads 121 are aligned with the plurality of second pads 122. In contrast, when there are many dark parts as a scanning result, the scanner 140 may determine that there are many misaligned combined parts among the combined parts of the plurality of first pads 121 and the plurality of second pads 122.

[0049] refer to Figure 6 , the scan results (scan output) according to one embodiment can be derived so that the misaligned parts can be visually detected. For example, the part including the misaligned combined parts may be darker than the part including the aligned combined parts. Moreover, because electrons are irregularly reflected from the misaligned combined parts, the misaligned combined parts may be larger in size than the aligned combined parts.

[0050] Figure 7 is a flow chart illustrating a method of operation of a test circuit according to one embodiment.

[0051] Refer to Figure 2 and Figure 7, the test circuit 130 according to one embodiment may apply a first voltage to the reference combination portion 110 in which a preset first reference pad 111 among a plurality of first pads is combined with a preset second reference pad 121 among a plurality of second pads (S710).

[0052] The first reference pad 111 and the second reference pad 121 of the reference combination part 110 according to one embodiment may be 100% aligned with each other. A preset voltage may be applied to the reference combination part 110 according to one embodiment, and the reference combination part 110 may have a reference resistance value R1. In one embodiment, the voltage applied to the reference combination part 110 may be a first voltage. Moreover, the first voltage may be an external voltage applied from the outside of the semiconductor multilayer structure 100, or may be an internal voltage applied from the inside of the semiconductor multilayer structure 100.

[0053] When the first voltage is applied to the test circuit 130 , the test circuit 130 may apply a second voltage to the comparison combination part 120 in which at least one first pad is combined with at least one second pad ( S720 ).

[0054] The comparison combination part 120 according to one embodiment may be a combination part of a first pad 121 randomly selected from a plurality of first pads and a second pad 122 randomly selected from a plurality of second pads. A preset voltage is applied to the comparison combination part 120 according to one embodiment, and the comparison combination part 120 may have a comparison resistance value R2. In one embodiment, the voltage applied to the comparison combination part 120 may be a second voltage. Moreover, the second voltage may be an external voltage applied from the outside of the semiconductor multilayer structure 100, or may be an internal voltage applied from the inside of the semiconductor multilayer structure 100.

[0055] When the first voltage and the second voltage are applied to the test circuit 130, the test circuit 130 can compare the voltage distributed based on the resistance ratio of the reference combination part 110 and the comparison combination part 120 with a preset reference voltage to determine whether at least one first pad and at least one second pad combined with each other are aligned with each other (S730).

[0056] Furthermore, the test circuit 130 may determine the degree of misalignment of the first pad 121 and the second pad 122 of the comparison combination part 120. According to one embodiment, the test circuit 130 may compare the voltage according to the distribution of the first voltage applied to the reference combination part 110 and the second voltage applied to the comparison combination part 120 with a preset reference voltage, and compare the distributed voltage with a preset answer sheet, thereby determining the degree of alignment of the first pad 121 and the second pad 122. For example, the test circuit 130 may compare the voltage according to the distribution of the first voltage and the second voltage with the reference voltage of the preset answer sheet, and when misalignment is found, the test circuit 130 may check the change of the voltage according to the distribution of the first voltage and the second voltage through the change of the reference voltage, and compare the voltage with the preset answer sheet, thereby determining the degree of alignment of the first pad 121 and the second pad 122. Furthermore, the test circuit 130 may determine the alignment trend of the first pad 121 and the second pad 122 of the comparison combination part 120.

[0057] According to one embodiment, the test circuit 130 may repeat the process of comparing the voltage according to the distribution of the first voltage applied to the reference combination part 110 and the second voltage applied to the comparison combination part 120 with the preset reference voltage and determining the degree of alignment of the first pad 121 and the second pad 122. For example, the test circuit 130 may determine whether the plurality of pads are aligned with each other and the degree of alignment of the plurality of pads by comparing the voltage according to the distribution of the first voltage applied to the reference combination part 110 and the second voltage applied to the comparison combination part 120 with the preset reference voltage of the comparison combination part 120 including at least one of the plurality of first pads and at least one of the plurality of second pads.

[0058] Figure 8 is a flow chart illustrating a method of determining an alignment tendency of a first pad and a second pad in an operating method of a test circuit according to one embodiment.

[0059] refer to Figure 3 and Figure 8 , the test circuit 130 according to one embodiment may start a misalignment detection operation ( S810 ).

[0060] When the misalignment detection operation starts, the test circuit 130 according to one embodiment may select a comparison combination part 120 in which at least one first pad is combined with at least one second pad (S820). The comparison combination part 120 according to one embodiment may be selected randomly or by a user.

[0061] When the comparison combination part is selected, the test circuit 130 according to one embodiment may input a reference voltage VREF higher than the first voltage and the second voltage to the comparator 132 (S830). The test circuit 130 according to one embodiment may compare the voltage Vfb according to the distribution of the first voltage and the second voltage with the reference voltage VREF, and may adjust the reference voltage VREF according to the comparison result. For example, the test circuit 130 may adjust the reference voltage VREF based on the output voltage of the comparator 132.

[0062] When the reference voltage VREF is input to the test circuit 130 , the test circuit 130 may determine whether the output voltage of the comparator 132 is at a logic low level ( S840 ).

[0063] When it is determined that the output voltage of the comparator 132 is not at a logic low level, the test circuit 130 according to one embodiment may reduce the reference voltage VREF (S850). When the output voltage of the comparator 132 according to one embodiment is at a logic high level, the semiconductor multilayer structure 100 may reduce the reference voltage VREF. For example, when the reference voltage VREF is higher than the voltage Vfb according to the distribution of the first voltage and the second voltage, the test circuit 130 may reduce the reference voltage. When the reference voltage VREF is reduced, the voltage Vfb according to the distribution of the first voltage and the second voltage may be equal to the reference voltage VREF at a certain time point. The test circuit 130 according to one embodiment may determine the degree of alignment of the plurality of first pads with the plurality of second pads based on the amount of change in the reference voltage VREF. For example, until the voltage Vfb according to the distribution of the first voltage and the second voltage is equal to the reference voltage VREF, the degree of alignment of the plurality of first pads with the plurality of second pads may be determined based on the change in the reference voltage VREF, and when the change increases, the test circuit 130 may determine that the misalignment rate of the plurality of first pads with the plurality of second pads has increased.

[0064] However, when it is determined that the output voltage of the comparator is at a logic low level, the test circuit 130 according to one embodiment may determine whether the comparison combination section 120 of the test target is the last comparison combination section (S860). The test circuit 130 according to one embodiment may repeat the determination of the alignment of each combination section of the plurality of first pads and the plurality of second pads until the determination of the last comparison combination section is made.

[0065] When it is determined that the comparison combination part 120 of the test target is the last comparison combination part, the test circuit 130 according to one embodiment can determine the alignment trend of the combination part of the plurality of first pads and the plurality of second pads (S870). According to one embodiment, at the time point when the output voltage of the comparator 132 changes from a logic high level to a logic low level, the test circuit 130 can determine the alignment trend of the plurality of first pads and the plurality of second pads. For example, when each reference voltage VREF changed in all comparison combination parts 120 is less than the voltage Vfb according to the distribution of the first voltage and the second voltage, it is determined that the distribution voltage of all comparison combination parts 120 can be changed, and the test circuit 130 can determine the alignment trend of the combination part of the plurality of first pads and the plurality of second pads.

[0066] However, when it is determined that the comparison combination part 120 of the test target is not the last comparison combination part, the test circuit 130 according to one embodiment can again select the comparison combination part of at least one first pad and at least one second pad, and determine whether the multiple first pads are aligned with the multiple second pads in all areas on the semiconductor multilayer structure 100.

[0067] Figures 9 to 11 is a diagram illustrating a three-dimensional V-NAND structure that may be applied to a memory device included in a semiconductor wafer according to one embodiment.

[0068] Applies to Figure 1 The nonvolatile memory of the memory device included in the semiconductor multilayer structure 100 according to the embodiment may include a plurality of memory blocks. Fig. 9 and Fig.10 The structure of a storage block BLKi among a plurality of storage blocks is shown in the figure, and Fig.11 An example of implementation of a non-volatile memory is illustrated.

[0069] refer to Fig. 9 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. For the sake of simplicity of the drawings, Fig.10 It is illustrated that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1 to MC8 , but is not limited thereto.

[0070] The string selection transistor SST may be connected to a corresponding string selection line among a plurality of string selection lines SSL1, SSL2, and SSL3. A plurality of memory cells MC1 to MC8 may be connected to a plurality of gate lines GTL1 to GTL8, respectively. A plurality of gate lines GTL1 to GTL8 may correspond to a plurality of word lines, and some of the plurality of gate lines GTL1 to GTL8 may correspond to dummy word lines. A ground selection transistor GST may be connected to a corresponding ground selection line among a plurality of ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST may be connected to a corresponding bit line among bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to a common source line CSL.

[0071] Gate lines (eg, GTL1) of the same height may be connected to each other, and a plurality of ground selection lines GSL1, GSL2, and GSL3 may be selected from a plurality of string selection lines SSL1, SSL2, and SSL3. Fig. 9 It is illustrated that the memory block BLKi is connected to eight gate lines GTL1 to GTL8 and three bit lines BL1 , BL2 , and BL3 , but the inventive concept is not limited thereto.

[0072] refer to Fig.10 , the memory block BLKi is formed in a vertical direction with respect to the substrate SUB. The memory cells constituting each of the memory NAND strings NS11 to NS33 are formed by stacking in a plurality of semiconductor layers.

[0073] A common source line CSL extending in a first direction (Y direction) is located on a substrate SUB. A plurality of insulating layers IL extending in the first direction (Y direction) are sequentially arranged in a region between two adjacent common source lines CSL on the substrate SUB along a third direction (Z direction), and may be separated from each other by a specific distance in the third direction (Z direction). A plurality of pillars P may be sequentially arranged in a region between two adjacent common source lines CSL on the substrate SUB along the first direction (Y direction), and pass through a plurality of insulating layers IL. A plurality of pillars P may pass through a plurality of insulating layers IL to contact the substrate SUB. A surface layer S of each of the plurality of pillars P may include a silicon material doped with impurities of a first conductive type, and may be used as a channel region.

[0074] The inner layer I of each of the plurality of pillars P may include an insulating material such as silicon oxide or an air gap. In the region between two adjacent common source lines CSL, a charge storage layer CS may be disposed along the exposed surfaces of the plurality of insulating layers IL, the plurality of pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (also referred to as a "tunnel insulating layer"), a charge trapping layer, and a blocking insulating layer. Moreover, in the region between the two adjacent common source lines CSL, gate electrodes GE such as selection lines GSL and SSL and a plurality of word lines WL1 to WL8 may be disposed on the exposed surface of the charge storage layer CS. The drain or drain contact DR may be located on the plurality of pillars P, respectively. The bit lines BL1 to BL3 extending in the second direction (X direction) and separated from each other by a specific distance in the first direction (Y direction) may be located on the drain contact DR, respectively.

[0075] like Fig.10 As illustrated, each of the plurality of memory NAND strings NS11 to NS33 may also have a structure in which a first storage stack ST1 and a second storage stack ST2 are stacked. The first storage stack ST1 may be connected to a common source line CSL, the second storage stack ST2 may be connected to bit lines BL1 to BL3, and the first storage stack ST1 and the second storage stack ST2 are stacked to share a channel hole with each other.

[0076] refer to Fig.11 , the non-volatile memory 130_1 may have a chip-to-chip (C2C) structure. In the C2C structure, an upper chip including a cell region CELL may be located on a first wafer, a lower chip including a peripheral circuit region PERI may be located on a second wafer different from the first wafer, and the upper chip may be connected to the lower chip by bonding. For example, bonding may refer to electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip to a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal is copper (Cu), the bonding may be Cu-Cu bonding, and the bonding metal may also include aluminum (Al) or tungsten (W).

[0077] Each of the peripheral circuit region PERI and the cell region CELL of the nonvolatile memory 130_1 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0078] The peripheral circuit region PERI may include: a first substrate 210; an interlayer insulating layer 215; a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210; first metal layers 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, respectively; and second metal layers 240a, 240b, and 240c formed on the first metal layers 230a, 230b, and 230c, respectively. In one embodiment, the first metal layers 230a, 230b, and 230c may be formed of tungsten having a relatively high resistivity, and the second metal layers 240a, 240b, and 240c may be formed of copper having a relatively low resistivity.

[0079] Although only the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are illustrated and described, the inventive concept is not limited thereto, and at least one metal layer may be further formed on the second metal layers 240a, 240b, and 240c. At least some of the one or more metal layers formed on the second metal layers 240a, 240b, and 240c may be formed of aluminum or the like having a higher resistivity than copper forming the second metal layers 240a, 240b, and 240c.

[0080] The interlayer insulating layer 215 may be located on the first substrate 210 to cover the plurality of circuit elements 220a, 220b, 220c, the first metal layers 230a, 230b and 230c, and the second metal layers 240a, 240b and 240c, and may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0081] The lower bonding metals 271b and 272b may be formed on the second metal layer 240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 371b and 372b of the cell area CELL by a bonding method, and the lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b may each be formed of aluminum, copper, or tungsten.

[0082] The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate 310 and a common source line 320. A plurality of word lines 331 to 338 (or 330) may be stacked on the second substrate 310 in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 310. A string selection line and a ground selection line may be arranged above and below the word line 330, respectively, and a plurality of word lines 330 may be located between the string selection line and the ground selection line.

[0083] In the bit line bonding area BLBA, the channel structure CH may extend in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 310 to pass through a plurality of word lines 330, string selection lines, and ground selection lines. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be referred to as a bit line 360c. In one embodiment, the bit line 360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0084] The region in which the channel structure CH and the bit line 360c are arranged may be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA and the peripheral circuit region PERI, the bit line 360c may be electrically connected to the circuit element 220c included in the page buffer 393. For example, the bit line 360c may be connected to the upper bonding metals 371c and 372c, and the upper bonding metals 371c and 372c may be connected to the lower bonding metals 271c and 272c of the circuit element 220c connected to the page buffer 393 in the peripheral circuit region PERI.

[0085] In the word line bonding area WLBA, a plurality of word lines 330 may extend in a second direction (X-axis direction) perpendicular to the first direction and parallel to the upper surface of the second substrate 310, and may be connected to a plurality of cell contact plugs 341 to 347 (or 340). The plurality of word lines 330 may be respectively connected to the plurality of cell contact plugs 340 through pads formed by extending at least some of the plurality of word lines 330 in different lengths in the second direction, respectively. The first metal layer 350b and the second metal layer 360b may be sequentially connected to the upper portion of each of the plurality of cell contact plugs 340 respectively connected to the plurality of word lines 330. The plurality of cell contact plugs 340 in the word line bonding area WLBA may be connected to the lower bonding metals 271b and 272b in the peripheral circuit area PERI through the upper bonding metals 371b and 372b in the cell area CELL.

[0086] The plurality of cell contact plugs 340 may be electrically connected to the circuit element 220b included in the row decoder 394 in the peripheral circuit region PERI. In one embodiment, the operating voltage of the circuit element 220b included in the row decoder 394 may be different from the operating voltage of the circuit element 220c included in the page buffer 393. For example, the operating voltage of the circuit element 220c included in the page buffer 393 may be greater than the operating voltage of the circuit element 220b included in the row decoder 394.

[0087] The common source line contact plug 380 may be located in the external pad bonding area PA. The common source line contact plug 380 may be formed of a conductive material such as a metal, a metal compound, or polysilicon, and may be electrically connected to the common source line 320. The first metal layer 350a and the second metal layer 360a may be sequentially stacked on the common source line contact plug 380. For example, an area in which the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are arranged may be defined as the external pad bonding area PA.

[0088] In addition, the first input / output pad 205 and the second input / output pad 305 may be located in the external pad bonding area PA. A lower insulating layer 201 covering the lower surface of the first substrate 210 may be formed on a lower portion of the first substrate 210, and the first input / output pad 205 may be formed on the lower insulating layer 201. The first input / output pad 205 may be connected to at least one of the plurality of circuit elements 220a, 220b, and 220c in the peripheral circuit area PERI through the first input / output contact plug 203, and may be separated from the first substrate 210 by the lower insulating layer 201. Moreover, a side insulating layer may be located between the first input / output contact plug 203 and the first substrate 210 to electrically separate the first input / output contact plug 203 from the first substrate 210.

[0089] An upper insulating layer 301 covering the upper surface of the second substrate 310 may be formed on the second substrate 310, and a second input / output pad 305 may be located on the upper insulating layer 301. The second input / output pad 305 may be connected to at least one of the plurality of circuit elements 220a, 220b, and 220c in the peripheral circuit region PERI through a second input / output contact plug 303. In one embodiment, the second input / output pad 305 may be electrically connected to the circuit element 220a.

[0090] According to an embodiment, the second substrate 310, the common source line 320, etc. may not be located in the region where the second input / output contact plug 303 is arranged. Moreover, the second input / output pad 305 may not overlap with the plurality of word lines 330 in the third direction (Z-axis direction). The second input / output contact plug 303 may be separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310, and may pass through the interlayer insulating layer 315 in the cell region CELL to be connected to the second input / output pad 305.

[0091] According to an embodiment, the first input / output pad 205 and the second input / output pad 305 may be selectively formed. For example, the nonvolatile memory 130_1 may include the first input / output pad 205 only on the upper portion of the first substrate 210, or may include the second input / output pad 305 only on the upper portion of the second substrate 310. Alternatively, the nonvolatile memory 130_1 may include both the first input / output pad 205 and the second input / output pad 305.

[0092] The metal pattern of the uppermost metal layer may be formed as a dummy pattern, or the uppermost metal layer may not be formed in each of the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell region CELL and the peripheral circuit region PERI.

[0093] In the external pad bonding area PA of the nonvolatile memory 130_1, a lower metal pattern 273a having the same shape as the upper metal pattern 372a of the cell area CELL may be formed on the uppermost metal layer in the peripheral circuit area PERI to correspond to the upper metal pattern 372a formed on the uppermost metal layer in the cell area CELL. The lower metal pattern 273a formed on the uppermost metal layer in the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, an upper metal pattern 373a having the same shape as the lower metal pattern 273a in the peripheral circuit area PERI may also be formed on the upper metal layer in the cell area CELL to correspond to the lower metal pattern 273a formed on the uppermost metal layer in the peripheral circuit area PERI.

[0094] Lower bonding metals 271b and 272b may be formed on the second metal layer 240b in the word line bonding area WLBA. In the word line bonding area WLBA, lower bonding metals 271b and 272b in the peripheral circuit area PERI may be electrically connected to upper bonding metals 371b and 372b in the cell area CELL by a bonding method.

[0095] Also, in the bit line bonding area BLBA, an upper metal pattern 392 having the same shape as the lower metal pattern 252 in the peripheral circuit area PERI may be formed on the uppermost metal layer in the cell area CELL to correspond to the lower metal pattern 252 formed on the uppermost metal layer in the peripheral circuit area PERI. Contact may not be formed on the upper metal pattern 392 formed on the uppermost metal layer in the cell area CELL.

[0096] According to the above embodiments, when manufacturing one semiconductor device by combining two or more semiconductor dies or manufacturing multiple semiconductor devices by combining two or more semiconductor wafers, the apparatus and method may accurately determine whether multiple semiconductor wafers are aligned with each other by including the above configuration.

[0097] The semiconductor die and semiconductor wafer according to the embodiment may support a test operation for determining the accuracy of alignment. The semiconductor die and semiconductor wafer may have pads for the test operation. The alignment and combination of the semiconductor die and semiconductor wafer according to the embodiment may be easily and accurately checked by performing the test operation.

[0098] While aspects of the inventive concept have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor multilayer structure, comprising: a first semiconductor wafer, the first semiconductor wafer comprising a plurality of first pads; a second semiconductor wafer including a plurality of second pads combined with the plurality of first pads; and a test circuit configured to apply a first voltage to a reference combination portion in which a preset first reference pad among the plurality of first pads is combined with a preset second reference pad among the plurality of second pads, and to apply a second voltage to a comparison combination portion in which at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads, The test circuit compares a voltage distributed based on a resistance ratio of the reference combination part to the comparison combination part with a preset reference voltage to determine whether the at least one first pad is aligned with the at least one second pad.

2. The semiconductor multilayer structure according to claim 1, wherein: The test circuit includes a comparator that compares the voltage distributed based on the resistance ratio of the reference combination part and the comparison combination part with the preset reference voltage.

3. The semiconductor multilayer structure according to claim 1, wherein: The test circuit determines a degree of misalignment of the at least one first pad and the at least one second pad in combination with each other.

4. The semiconductor multilayer structure according to claim 1, wherein: The test circuit compares the voltage distributed based on the resistance ratio of the reference combination part and the comparison combination part with the preset reference voltage, and determines an alignment tendency of the plurality of first pads and the plurality of second pads based on the comparison result.

5. The semiconductor multilayer structure according to claim 1, wherein: The plurality of first pads and the plurality of second pads are arranged to have a square matrix structure.

6. The semiconductor multilayer structure according to claim 2, wherein: When misalignment is found, the test circuit inputs the preset reference voltage higher than the first voltage and the second voltage to the comparator, and When the output voltage of the comparator is at a logic high level, the preset reference voltage is lowered.

7. The semiconductor multilayer structure according to claim 2, wherein: When misalignment is detected, the test circuit inputs the preset reference voltage higher than the first voltage and the second voltage to the comparator, and At a time point when an output voltage of the comparator changes from a logic high level to a logic low level, an alignment tendency of the plurality of first pads and the plurality of second pads is determined.

8. The semiconductor multilayer structure according to claim 7, wherein: The alignment trends of the plurality of first pads and the plurality of second pads are determined based on a preset answer sheet.

9. The semiconductor multilayer structure according to claim 1, wherein: The test circuit comprises: a first voltage pad configured to receive the first voltage; a second voltage pad configured to receive the second voltage; and A reference voltage pad is configured to receive the preset reference voltage.

10. A semiconductor multilayer structure, comprising: a first semiconductor wafer, the first semiconductor wafer comprising a plurality of first pads; a second semiconductor wafer including a plurality of second pads combined with the plurality of first pads; and a scanner configured to perform electron beam scanning of a reference combination part and a comparison combination part, in which a preset first reference pad among the plurality of first pads is combined with a preset second reference pad among the plurality of second pads, and in which at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads, wherein the scanner determines whether the at least one first pad is aligned with the at least one second pad based on an amount of electrons reflected from the reference combination portion and the comparison combination portion during scanning of the electron beam.

11. The semiconductor multilayer structure according to claim 10, wherein: The scanner determines whether the at least one first pad is combined with the at least one second pad based on colors obtained from the reference combination part and the comparison combination part as a result of the electron beam scanning.

12. The semiconductor multilayer structure according to claim 10, wherein: The scanner determines a degree of misalignment of the at least one first pad and the at least one second pad in combination with each other.

13. The semiconductor multilayer structure according to claim 10, wherein: The scanner determines an alignment tendency of the plurality of first pads and the plurality of second pads based on a result of the electron beam scanning.

14. The semiconductor multilayer structure according to claim 10, wherein: The plurality of first pads and the plurality of second pads are arranged to have a square matrix structure.

15. An operating method of a test circuit for determining whether there is a misaligned test circuit in a semiconductor multilayer structure including a three-dimensional memory device, the operating method comprising: applying a first voltage to a reference combination portion in which a preset first reference pad among a plurality of first pads included in a first wafer is combined with a preset second reference pad among a plurality of second pads included in a second wafer; Applying a second voltage to a comparison combination portion where at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads; as well as Whether the at least one first pad is aligned with the at least one second pad is determined by comparing a voltage distributed based on a resistance ratio of the reference combined part and the comparison combined part with a preset reference voltage.

16. The operating method according to claim 15, wherein: In determining whether the at least one first pad is aligned with the at least one second pad, a degree of misalignment of the at least one first pad and the at least one second pad combined with each other is determined.

17. The operating method according to claim 15, wherein: In determining whether the at least one first pad is aligned with the at least one second pad, an alignment tendency of the plurality of first pads with the plurality of second pads is determined.

18. The operating method according to claim 15, wherein: In determining whether the at least one first pad is aligned with the at least one second pad, an output voltage of a comparator included in the test circuit is determined, and When the output voltage of the comparator is at a logic high level, the preset reference voltage is lowered.

19. The operating method according to claim 15, wherein: Determining whether the at least one first pad is aligned with the at least one second pad comprises: determining an output voltage of a comparator included in the test circuit; and When misalignment is detected, the preset reference voltage higher than the first voltage and the second voltage is input to the comparator, and at the time point when the output voltage of the comparator changes from a logic high level to a logic low level, the alignment trend of the multiple first pads and the multiple second pads is determined.

20. The operating method according to claim 19, wherein: Determining the alignment trends of the plurality of first pads and the plurality of second pads includes: The alignment trends of the plurality of first pads and the plurality of second pads are determined based on a preset answer sheet.

Images