RDL fan-out structure based on DDR bare chip

Abstract

The invention discloses an RDL fan-out structure based on a DDR bare chip. The present invention relates to a semiconductor device including an EMC layer (130) formed on a DDR die, a pad (110) formed on the EMC layer (130), a dielectric layer (DL2140) formed over the DDR die and electrically connected to the pad (110), an RDL layer (150) formed over the dielectric layer (DL2140) and electrically connected to the pad (110), a dielectric layer (DL1160) formed over the RDL layer (150), a UBM layer (170) formed over the dielectric layer (DL1160) and electrically connected to the RDL layer (150), and a BGA solder ball (180) formed over the UBM layer (170). According to the invention, the solution of three-dimensional integrated interconnection is realized through the rewiring technology, and the bonding pad array located in the middle of the DDR bare chip is innovatively changed into the FC salient points which are uniformly distributed on the chip, so that the power supply distribution and the signal integrity are optimized.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit packaging, and relates to an RDL fan-out structure based on a DDR bare chip. Background Art

[0002] At present, with the advancement of semiconductor process technology, the size of transistors continues to shrink, the integration level is greatly improved, the size of bare chips is also decreasing, and the functions are more complex. This has led to a significant increase in the number of I / O (input / output) on the bare chip, which has put forward higher requirements for packaging technology. Traditional wire bonding technology has gradually encountered bottlenecks because a large number of wires will cause signal delays and interference problems. In order to solve these problems, various advanced packaging technologies have been developed, such as flip chip technology.

[0003] As data transmission rates increase, signal integrity issues become more prominent, and various technologies need to be used to ensure signal quality, such as using differential signal pairs and controlling signal impedance matching. As die power consumption increases, how to effectively provide stable and sufficient power to the die becomes a challenge. The design of the power distribution network (PDN) becomes particularly important, and many factors such as power noise, voltage regulation, and thermal management need to be considered. Effective thermal management can ensure that the temperature of the die remains within an acceptable range, avoiding performance degradation or device damage due to overheating.

[0004] RDL (rewiring) fan-out technology was developed under such a technical background. RDL is a metal interconnect structure formed on the package substrate or interposer, which can redistribute the signal and power pins on the die to other parts of the package, such as under the BGA (ball grid array). This technology can provide a shorter signal path, reduce signal delay and interference, and improve signal integrity; it can also optimize power distribution and thermal management, and improve the overall performance of the package. Summary of the invention

[0005] (I) Purpose of the invention

[0006] The purpose of the present invention is to provide an RDL fan-out structure based on a DDR die to solve the problem of rearranging the electrical connection points of the DDR die.

[0007] (II) Technical solution

[0008] In order to solve the above technical problems, the present invention provides an RDL fan-out structure based on a DDR die, which includes: an EMC layer 130 formed on the DDR die, a pad 110 formed on the EMC layer 130, a dielectric layer DL2140 formed above the DDR die and electrically connected to the pad 110, an RDL layer 150 formed above the dielectric layer DL2140 and electrically connected to the pad 110, a dielectric layer DL1160 formed above the RDL layer 150, a UBM layer 170 formed above the dielectric layer DL1160 and electrically connected to the RDL layer 150, and a BGA solder ball 180 formed above the UBM layer 170.

[0009] A sealing ring 120 is formed on the periphery of the EMC layer 130 .

[0010] The pad 110 is used to connect the metallization area on the DDR die and the contact point of the external circuit.

[0011] The pad 110 is made of aluminum or copper conductive material and is located on the surface of the DDR die.

[0012] The sealing ring 120 is annular and is located between the chip and the packaging shell. The sealing ring is made of metal, plastic or rubber.

[0013] The EMC layer 130 is made of thermosetting resin.

[0014] Among them, the dielectric layer DL2140 and the dielectric layer DL1160 are used to insulate different conductive layers; there is a DL2 window 141 on the dielectric layer DL2140, and there is a DL1 window 161 on the dielectric layer DL1160; the RDL layer 150 is electrically connected to the pad 110 through the DL2 window 141, and the UBM layer 170 is electrically connected to the RDL layer 150 through the DL1 window 161.

[0015] The RDL layer 150 is used to rewire the circuits on the chip. The RDL layer 150 is electrically connected to the pad 110 , and the RDL layer 150 is electrically connected to the UBM layer 170 .

[0016] Among them, the UBM layer 170 , a Ti / Cu metal layer is sputtered on the dielectric layer DL1160 as the UBM layer 170 , and the UBM layer 170 forms a metallization transition between the BGA solder ball 180 and the RDL layer 150 .

[0017] The BGA solder balls 180 are arranged in an array to form FC bumps, and the BGA solder balls 180 are electrically connected to the UBM layer 170 .

[0018] (III) Beneficial effects

[0019] The RDL fan-out structure based on DDR die provided by the above technical solution realizes a three-dimensional integrated interconnection solution through rewiring technology, and innovatively transforms the pad array located in the middle of the DDR die into FC bumps evenly arranged on the chip, thereby optimizing power distribution and signal integrity; it expands the three-dimensional integration capability and technical level of RDL technology, and provides effective technical support for similar product designs or more complex system chip integration; the invention has high signal quality and good reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of an RDL fan-out structure based on a DDR die of the present invention.

[0021] Figure 2 It is a schematic diagram of the arrangement of electrical connection points before and after RLD fan-out of the present invention, Figure a is a schematic diagram before RDL fan-out, and Figure b is a schematic diagram after RDL fan-out. DETAILED DESCRIPTION

[0022] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0023] The present invention fans out to a Flip Chip format through RDL. Based on the DDR3 wafer, the RDL is designed to convert the original WB pads into FC bumps evenly arranged on the DDR die, which optimizes the substrate design to a great extent, reduces the layout design area, and can provide a higher interconnection density. The following solutions are provided based on process feasibility.

[0024] Reference Figure 1 As shown, the RDL fan-out structure based on the DDR die in this embodiment includes an EMC layer 130 formed on the DDR die, a pad 110 formed on the EMC layer 130, a dielectric layer DL2140 formed above the DDR die and electrically connected to the pad 110, an RDL layer 150 formed above the dielectric layer DL2140 and electrically connected to the pad 110, a dielectric layer DL1160 formed above the RDL layer 150, a UBM layer 170 formed above the dielectric layer DL1160 and electrically connected to the RDL layer 150, and a BGA solder ball 180 formed above the UBM layer 170.

[0025] A sealing ring 120 is formed on the periphery of the EMC layer 130 .

[0026] The pads 110 are used to connect the metallization area on the DDR die to the contact points of the external circuit. These pads are usually made of aluminum, copper or other conductive materials and are located on the surface of the DDR die. The pads 110 are electrically connected to the dielectric layer DL2140, thereby forming an electrical connection between the DDR die and the RDL layer.

[0027] The sealing ring 120 is a key component in semiconductor packaging, used to protect the chip from external environmental influences, such as moisture, dust and other pollutants, and also to prevent damage to the internal circuit during dicing. The sealing ring is a ring-shaped metal or non-metal material, which is placed on the outside of the package, usually between the chip and the package shell. Common materials for the sealing ring include metal (such as copper, aluminum), plastic and rubber.

[0028] The EMC layer 130 can use thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, and the above resins are impregnated with reinforcing materials such as glass or pre-filled organic materials. Prepregs, or thermosetting resins and / or photocurable resins can be used to protect the semiconductor chip from physical damage and environmental factors.

[0029] The dielectric layer DL2140 and the dielectric layer DL1160 are used to insulate different conductive layers. Generally, PI glue is used to prevent electrical short circuits and provide mechanical support. There is a DL2 window 141 on the dielectric layer DL2140, and there is a DL1 window 161 on the dielectric layer DL1160. There is no solder mask printed on the DL2 window 141 and the DL1 window 161, and welding can be performed at the position of the window.

[0030] The RDL layer 150 is used to rewire the circuits on the chip. The RDL layer 150 is electrically connected to the pad 110 , and the RDL layer 150 is electrically connected to the UBM layer 170 .

[0031] UBM layer 170 , a Ti / Cu metal layer is sputtered on the dielectric layer DL1160 as the UBM layer 170 , and the UBM layer 170 forms a metallization transition between the BGA solder ball 180 and the RDL layer 150 .

[0032] The BGA solder balls 180 are arranged in an array to form FC bumps, and the BGA solder balls 180 are electrically connected to the UBM layer 170 .

[0033] like Figure 2 As shown, a schematic diagram of the electrical connection arrangement before and after RLD fan-out. The schematic diagram includes: a schematic diagram 210 before RDL fan-out, a schematic diagram 220 after RDL fan-out, a pad 211, and a BGA solder ball 221.

[0034] The schematic diagram 210 includes a pad 211 . The pad 211 is arranged in the middle of the DDR die. The pad 211 corresponds to the pad 110 .

[0035] The schematic diagram 220 includes a BGA solder ball 221 . The BGA solder ball 221 is evenly arranged in an array on the DDR package chip. The BGA solder ball 221 corresponds to the BGA solder ball 180 .

[0036] It can be seen from the above technical scheme that the present invention re-arranges the pads of the DDR bare chip to a new area with a wider space by re-arranging the IO port, and forms an array arrangement. Through RDL fan-out to Flip Chip form, on the basis of DDR3 wafer, RDL is designed to convert the original WB (Wire Bonding) pads into FC (FlipChip) bump form, which greatly optimizes the substrate design, reduces the layout design area, and can provide higher interconnection density. It provides an effective technical approach and solution for subsequent high-density, heterogeneous chip three-dimensional integration.

[0037] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An RDL fan-out structure based on a DDR die, characterized in that: include: An EMC layer (130) is formed on a DDR die, a pad (110) is formed on the EMC layer (130), a dielectric layer DL2 (140) is formed above the DDR die and electrically connected to the pad (110), an RDL layer (150) is formed above the dielectric layer DL2 (140) and electrically connected to the pad (110), a dielectric layer DL1 (160) is formed above the RDL layer (150), a UBM layer (170) is formed above the dielectric layer DL1 (160) and electrically connected to the RDL layer (150), and a BGA solder ball (180) is formed above the UBM layer (170).

2. The RDL fan-out structure based on DDR die according to claim 1, characterized in that: A sealing ring (120) is also formed on the periphery of the EMC layer (130).

3. The RDL fan-out structure based on DDR die as claimed in claim 2, characterized in that: The pad (110) is used to connect the metallization area on the DDR die and the contact point of the external circuit.

4. The RDL fan-out structure based on DDR bare die as claimed in claim 3, characterized in that: The pad (110) is made of aluminum or copper conductive material and is located on the surface of the DDR bare chip.

5. The RDL fan-out structure based on DDR bare die as claimed in claim 4, characterized in that: The sealing ring (120) is annular and is located between the chip and the packaging shell. The material of the sealing ring is one of metal, plastic or rubber.

6. The RDL fan-out structure based on DDR die as claimed in claim 5, characterized in that: The EMC layer (130) is made of thermosetting resin.

7. The RDL fan-out structure based on DDR die as claimed in claim 6, characterized in that: The dielectric layer DL2 (140) and the dielectric layer DL1 (160) are used to insulate different conductive layers; the dielectric layer DL2 (140) has a DL2 window (141), and the dielectric layer DL1 (160) has a DL1 window (161); the RDL layer (150) is electrically connected to the pad (110) through the DL2 window (141), and the UBM layer (170) is electrically connected to the RDL layer (150) through the DL1 window (161).

8. The RDL fan-out structure based on DDR bare die as claimed in claim 7, characterized in that: The RDL layer (150) is used to rewire the circuits on the chip. The RDL layer (150) and the pad (110) form an electrical connection. The RDL layer (150) and the UBM layer (170) form an electrical connection.

9. The RDL fan-out structure based on DDR die as claimed in claim 8, characterized in that: A Ti / Cu metal layer is sputtered on the dielectric layer DL1 (160) as the UBM layer (170), and the UBM layer (170) forms a metallization transition between the BGA solder ball (180) and the RDL layer (150).

10. The RDL fan-out structure based on DDR bare die according to claim 9, characterized in that: BGA solder balls (180) are arranged in an array to form FC bumps, and the BGA solder balls (180) are electrically connected to the UBM layer (170).

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